NCV4299D1 [ONSEMI]
150 mA Low−Dropout Voltage Regulator; 150毫安低压差稳压器
| 型号： | NCV4299D1 |
| 厂家： | 
ONSEMI |
| 描述： | 150 mA Low−Dropout Voltage Regulator |
| 文件： | 总23页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV4299
150 mA Low−Dropout
Voltage Regulator
The NCV4299 is a family of precision micropower voltage regulators
with an output current capability of 150 mA. It is available in 5.0 V or
3.3 V output voltage, and is housed in an 8−lead SON and in a 14−lead
SON (fused) package.
The output voltage is accurate within "2% with a maximum
dropout voltage of 0.5 V at 100 mA. Low Quiescent current is a
feature drawing only 90 mA with a 1 mA load. This part is ideal for any
and all battery operated microprocessor equipment.
The device features microprocessor interfaces including an
adjustable reset output and adjustable system monitor to provide
shutdown early warning. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and the device
consumes less than 1.0 mA of quiescent current.
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MARKING
DIAGRAMS
8
SO−8
D SUFFIX
CASE 751
4299
ALYW
G
8
1
1
14
The part can withstand load dump transients making it suitable for
use in automotive environments.
NCV4299G
AWLYWW
Features
SO−14
1
• 5.0 V, 3.3 V "2%, 150 mA
14
D SUFFIX
CASE 751A
14
• Extremely Low Current Consumption
♦ 90 mA (Typ) in the ON Mode
♦ t1.0 mA in the Off Mode
• Early Warning
1
V4299xxG
AWLYWW
1
• Reset Output Low Down to V = 1.0 V
Q
xx
= 33 (3.3 V Version)
= 50 (5.0 V Version)
= Assembly Location
L, WL = Wafer Lot
= Year
W, WW = Work Week
= Pb−Free Package
= Pb−Free Package
(Note: Microdot may be in either location)
• Adjustable Reset Threshold
• Wide Temperature Range
A
• Fault Protection
Y
♦ 60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
G
G
♦ Thermal Overload
• Internally Fused Leads in the SO−14 Package
• Inhibit Function with mA Current Consumption in the Off Mode
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
PIN CONNECTIONS
1
8
I
Q
SI
RADJ
D
SO
• Pb−Free Packages are Available
RO
GND
1
14
RADJ
D
SI
I
GND
GND
GND
INH
RO
GND
GND
GND
Q
SO
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 16
NCV4299/D
NCV4299
Q
I
Current Limit and
Saturation Sense
Bandgap
Reference
−
+
R
SO
R
RO
SO
RO
1.36 V
+
−
SI
8 mA
+
+
−
−
+
RADJ
1.85 V
D
GND
Figure 1. SO−8 Simplified Block Diagram
PIN FUNCTION DESCRIPTION − SO−8 PACKAGE
Pin
1
Symbol
Description
Input. Battery Supply Input Voltage. Bypass directly to GND with ceramic capacitor.
I
2
SI
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
Connect to Q if not used.
3
4
5
6
RADJ
D
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
Reset Delay. Connect external capacitor to ground to set delay time.
Ground.
GND
RO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condi-
tion. Leave open if not used.
7
8
SO
Q
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition. Leave open if not used.
5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 5.0 W to ground.
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2
NCV4299
Q
I
Current Limit and
Saturation Sense
Bandgap
Reference
−
+
R
SO
R
RO
INH
SO
RO
1.36 V
+
−
SI
8 mA
+
+
−
−
+
RADJ
1.85 V
D
GND
Figure 2. SO−14 Simplified Block Diagram
PIN FUNCTION DESCRIPTION − SO−14 PACKAGE
Pin
1
Symbol
RADJ
D
Description
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
2
Reset Delay. Connect external capacitor to ground to set delay time.
3
GND
GND
GND
INH
Ground.
4
Ground.
5
Ground.
6
Inhibit. Connect to I if not needed. A high turns the regulator on.
7
RO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condi-
tion.
8
SO
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition.
9
Q
GND
GND
GND
I
5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 5.0 W to ground.
10
11
12
13
14
Ground.
Ground.
Ground.
Input. Battery Supply Input Voltage.
SI
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
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NCV4299
MAXIMUM RATINGS
Rating
Symbol
Min
−40
−
Max
45
60
45
45
1.0
7.0
10
7.0
7.0
7.0
16
−
Unit
V
Input Voltage to Regulator (DC)
Input Peak Transient Voltage to Regulator wrt GND
Inhibit (INH) (Note 1)
V
I
−
V
V
−40
−0.3
−1.0
−0.3
−10
−0.3
−0.3
−0.3
−0.3
−5.0
2.0
V
INH
Sense Input (SI)
V
V
SI
Sense Input (SI)
I
mA
V
SI
Reset Threshold (RADJ)
Reset Threshold (RADJ)
Reset Delay (D)
V
RE
RE
I
mA
V
V
D
Reset Output (RO)
V
V
RO
SO
Sense Output (SO)
V
V
Output (Q)
V
V
Q
Output (Q)
I
mA
kV
V
Q
ESD Capability, Human Body Model (Note 5)
ESD Capability, Machine Model (Note 5)
ESD Capability, Charged Device Model (Note 5)
Junction Temperature
ESD
−
HB
MM
CDM
J
ESD
200
1.0
−
ESD
T
−
kV
°C
°C
−
150
150
Storage Temperature
T
stg
−50
OPERATING RANGE
Input Voltage
5.0 V Version
3.3 V Version
V
T
V
I
4.5
4.4
45
45
Junction Temperature
−40
150
°C
J
LEAD TEMPERATURE SOLDERING REFLOW (Note 3)
Lead Temperature Soldering (Note 5)
Reflow (SMD styles only), leaded
60−150 sec above 183, 30 sec max at peak
T
T
°C
°C
SLD
SLD
−
−
240 Pk
265 Pk
Reflow (SMD styles only), lead free
60s−150 sec above 217, 40 sec max at peak
Moisture Sensitivity Level
MSL
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 14 pin package only.
2. Preliminary numbers.
3. Per IPC / JEDEC J−STD−020C.
4. Measured to Pin 4. All ground pins connected to ground.
5. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model.
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NCV4299
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Value)
Unit
Note 6
Note 7
Note 8
SO−8
°C/W
Junction−to−Tab (y , q
)
54
52
48
JLx JLx
172
144
118
Junction−to−Ambient (R , q
)
)
θ
JA JA
SO−14
°C/W
Junction−to−Tab (y , q
)
19
112
21
89
20
67
JLx JLx
Junction−to−Ambient (R , q
θ
JA JA
6. 2 oz Copper, 50 mm sq Copper area, 1.5 mm thick FR4
7. 2 oz Copper, 150 mm sq Copper area, 1.5 mm thick FR4
8. 2 oz Copper, 500 mm sq Copper area, 1.5 mm thick FR4
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C; V = 13.5 V unless otherwise noted.)
J
I
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Q
Output Voltage (5.0 V Version)
Output Voltage (3.3 V Version)
Current Limit
V
V
1.0 mA < I < 150 mA, 6.0 V < V < 16 V
4.9
3.23
250
−
5.0
3.3
400
86
5.1
3.37
500
100
105
500
2.0
1.0
0.50
30
V
Q
Q
Q
I
1.0 mA < I < 150 mA, 5.5 V < V < 16 V
V
Q
I
I
−
mA
mA
mA
mA
mA
mA
V
Q
Quiescent Current (I = I – I )
I
INH ON, I < 1.0 mA, T = 25°C
Q J
q
I
Q
q
q
q
q
q
Quiescent Current (I = I – I )
I
I
I
I
INH ON, I < 1.0 mA
−
90
q
I
Q
Q
Quiescent Current (I = I – I )
INH ON, I = 10 mA
−
170
0.7
−
q
I
Q
Q
Quiescent Current (I = I – I )
INH ON, I = 50 mA
−
q
I
Q
Q
Quiescent Current (I = I – I )
INH = 0 V, T = 25°C
−
q
I
Q
J
Dropout Voltage (Note 9)
Load Regulation
V
I
I
= 100 mA
−
0.22
5.0
10
dr
Q
Q
DV
DV
= 1.0 mA to 100 mA
−
mV
mV
dB
Q
Q
Line Regulation
V = 6.0 V to 28 V, I = 1.0 mA
−
25
I
Q
Power Supply Ripple Rejection
Inhibit (INH) (14 Pin Package Only)
Inhibit Off Voltage
P
ƒr = 100 Hz, Vr = 1.0 Vpp, I = 100 mA
−
66
−
SRR
Q
V
V
< 1.0 V
−
−
0.8
V
V
INHOFF
Q
Inhibit On Voltage
5.0 V Version
V
INHON
V
V
> 4.85 V
> 3.2 V
3.5
3.5
−
−
−
−
Q
Q
3.3 V Version
Input Current
I
INH ON
−
−
3.0
0.5
10
mA
INHON
I
INH = 0 V
2.0
INHOFF
Reset (RO)
Switching Threshold
5.0 V Version
V
−
−
V
rt
4.50
2.96
4.60
3.06
4.80
3.16
3.3 V Version
Output Resistance
R
V
10
20
40
kW
RO
Reset Output Low Voltage
5.0 V Version
V
RO
Q < 4.5 V, Internal R , I = −1.0 mA
−
−
0.17
0.17
0.40
0.40
RO RO
3.3 V Version
Q < 2.96 V, Internal R , I = −1.0 mA
RO RO
Allowable External Reset Pullup Resistor
Delay Upper Threshold
V
External Resistor to Q
5.6
1.5
0.4
−
−
kW
V
ROext
V
−
−
1.85
0.5
2.2
0.6
UD
Delay Lower Threshold
V
V
LD
9. Measured when the output voltage V has dropped 100 mV from the nominal value obtained at V = 13.5 V.
Q
I
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NCV4299
ELECTRICAL CHARACTERISTICS (continued) (−40°C < T < 150°C; V = 13.5 V unless otherwise noted.)
J
I
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Reset (RO)
Delay Output Low Voltage
5.0 V Version
V
V
D
Q < 4.5 V, Internal R
Q < 2.96 V, Internal R
−
−
−
0.1
0.1
RO
RO
3.3 V Version
0.017
Delay Charge Current
5.0 V Version
I
mA
D
Q < 4.5 V, Internal R , V = 1.0 V
4.0
−
7.1
−
12
−
RO
D
3.3 V Version
Q < 2.96 V, Internal R , V = 1.0 V
RO D
Power On Reset Delay Time
Reset Reaction Time
t
C
C
= 100 nF
= 100 nF
17
28
35
ms
ms
V
d
D
t
0.5
2.2
4.0
rr
D
Reset Adjust Switching Threshold
5.0 V Version
V
RADJ,TH
Q > 3.5 V
Q > 2.3 V
1.26
−
1.36
−
1.44
−
3.3 V Version
Input Voltage Sense (SI and SO)
Sense Input Threshold High
Sense Input Threshold Low
Sense Input Hysteresis
V
−
−
1.34
1.26
50
1.45
1.36
90
1.54
1.44
130
V
V
SI,HIGH
V
SI,LOW
−
(Sense Threshold High) −
(Sense Threshold Low)
mV
Sense Input Current
I
R
V
−
−
−1.0
10
0.1
20
0.1
−
1.0
40
0.4
−
mA
kW
V
SI
Sense Output Resistance
Sense Output Low Voltage
SO
SO
V
< 1.20 V, V > 4.2 V, I = 0 mA
−
SI
I
SO
Allowable External Sense Out
Pullup Resistor
R
SOext
−
5.6
kW
SI High to SO High Reaction Time
SI Low to SO Low Reaction Time
t
t
−
−
−
−
4.4
3.8
8.0
5.0
ms
ms
pdSOLH
pdSOHL
I
I
Q
I
V
V
I
Q
Q
I
I
INH
V
INH
D
INH
(14−Pin Part Only)
I
D
V
RO
SO
RO
C
D
I
D
100 nF
I
RADJ
V
RADJ
SI
RADJ
V
I
SO
SI
V
SI
GND
I
q
Figure 3. Measurement Circuit
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NCV4299
TYPICAL PERFORMANCE CHARACTERISTICS − 5.0 V OPTION
5.1
6
V = 13.5 V
I
R = 1 kW
L
5
4
3
5.0
4.9
2
1
0
R = 50 W
L
−40 −20
0
20 40
60 80 100 120 140 160
0
5
10
15
TEMPERATURE C
INPUT VOLTAGE, VI VOLTS
Figure 5. Output Voltage VQ vs. Input Voltage
Figure 4. Output Voltage VQ vs. Temperature TJ
8.0
500
V = 13.5 V
I
V
= 1 V
D
125°C
400
R = 5 kW
L
25°C
300
200
100
0
7.0
6.0
−40°C
−40 −20
0
20 40
60 80 100 120 140 160
0
50
100
150
TEMPERATURE C
OUTPUT CURRENT IQ, mA
Figure 6. Charge Current ld, c vs. Temperature TJ
Figure 7. Drop Voltage Vdr vs. Output Current IQ
3.2
1.5
2.8
2.4
1.4
1.3
V
UD
2.0
1.6
1.2
1.2
1.1
1.0
0.9
0.8
0.4
0.0
V
V = 13.5V
I
LD,
−40
0
40
80
120
160
−40
0
40
80
120
160
TEMPERATURE, C
TEMPERATURE TJ, C
Figure 8. Switching Voltage VUD and VLD vs.
Temperature TJ
Figure 9. Reset Adjust Switching Threshold
VRADJTH vs. Temperature TJ
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NCV4299
1.6
1.5
1.4
350
300
VSIU
VSIL
T = 25°C
J
250
200
T = 125°C
J
1.3
1.2
150
100
50
1.1
1.0
V
= 0 V
Q
0
−40
0
40
80
120
160
0
10
20
30
40
TEMPERATURE, C
INPUT VOLTAGE, VI, V
Figure 11. Output Current Limit IQ vs. Input
Voltage, VI
Figure 10. Sense Threshold VSI vs. Temperature TJ
2.0
1.5
1.0
8.0
6.0
4.0
0.5
0.0
2.0
0.0
0
10
20
30
40
50
60
0
40
80
120
160
OUTPUT CURRENT IQ, mA
OUTPUT CURRENT IQ, mA
Figure 12. Current Consumption Iq vs. Output
Current IQ
Figure 13. Current Consumption Iq vs. Output
Current IQ
16.0
14.0
40
30
V = 13.5V
R = 5 kW
L
I
12.0
10.0
R 200W R 100W
R 50W
L
R 33W
L
L
L
8.0
6.0
20
10
4.0
2.0
0.0
−40
0
40
80
120
160
0
10
20
INPUT VOLTAGE VI, V
30
40
TEMPERATURE C
Figure 14. RRO, RSO Resistance vs. Temperature
Figure 15. Current Consumption Iq vs. Input
Voltage VI
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NCV4299
90
85
80
75
70
65
60
6
5
4
3
2
1
0
IQ 100mA
IQ 100 mA
IQ 50mA
IQ 10mA
6
8
10
12 14 16
18 20 22
24 26
6
8
10
12 14 16
18 20 22
24 26
INPUT VOLTAGE VI, V
INPUT VOLTAGE VI, V
Figure 17. Current Consumption Iq vs. Input
Voltage VI
Figure 16. Current Consumption Iq vs. Input
Voltage VI
45
40
V = 13.5V
T = 25°C
A
I
Unstable
Region
35
30
25
20
1 mF to 100 mF
0.1 mF
15
10
5
Stable
Region
Unstable Region
0.1 mF Only
0
0
20
40
60
80
100 120
140 160
OUTPUT CURRENT, mA
Figure 18. Stability vs. Output Capacitor ESR
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NCV4299
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
1000
100
10
12
10
V = 13.5 V
I
8
I
= 1 mA
Q
T = 25°C
J
6
4
T = 150°C
J
T = −40°C
J
1
2
0
0.1
−40 −20
0
20 40 60 80 100 120 140
0
20 40
60
80 100 120 140 160 180
T , JUNCTION TEMPERATURE (°C)
J
I , OUTPUT CURRENT (mA)
Q
Figure 19. Current Consumption vs. Junction
Temperature
Figure 20. Current Consumption vs. Output
Current
5
4
3.5
3.4
T = 25°C
J
V = 13.5V
R = 1 kW
L
I
3.3
3.2
3.1
3
2
R = 33 W
L
R = 50 W
L
1
0
3.0
2.9
R = 100 W
L
200
50
0
10
20
30
40
−40
0
40
80
120
160
V , INPUT VOLTAGE (V)
I
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Current Consumption vs. Input
Voltage
Figure 22. Output Voltage vs. Junction
Temperature
0
−50
350
V = 0 V
I
300
250
200
T = 25°C
J
T = 125°C
J
T = 125°C
J
−100
−150
−200
150
100
T = 25°C
J
T = −40°C
J
−250
−300
50
0
V
= 0 V
Q
0
10
20
30
40
50
0
25
V , INPUT VOLTAGE (V)
50
V , OUTPUT VOLTAGE (V)
Q
I
Figure 23. Reverse Output Current vs. Output
Voltage
Figure 24. Maximum Output Current vs. Input
Voltage
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NCV4299
6
5
4
3
2
1000
100
10
T = 25°C
J
Max ESR for V = 6 V
in
R = 50 W
L
Max ESR for V = 25 V
in
1
Stable Region
0.1
1
0
C
Q
= 22 mF
T = 150°C
J
0.01
5
0
0
0
1
2
3
4
0
10
40
70
100
130
V , INPUT VOLTAGE (V)
I , OUTPUT CURRENT (mA)
I
Q
Figure 25. Output Voltage at Input Voltage
Extremes
Figure 26. 3.3 V Output Stability with Output
Capacitor ESR
1000
100
10
0.02
0.01
0
INH = OFF
T = −40°C
J
Max ESR for V = 6 V
in
T = 25°C
J
Max ESR for V = 25 V
T = 125°C
J
in
−0.01
−0.02
−0.03
1
Stable Region
0.1
−0.04
−0.05
C
= 22 mF
T = 150°C
J
Q
T = −40°C
J
0.01
10
40
70
100
130
0
10
20
30
40
I , OUTPUT CURRENT (mA)
V , INPUT VOLTAGE (V)
I
Q
Figure 27. 3.3 V Output Stability with Output
Capacitor ESR
Figure 28. Inhibit Input Current at Input
Voltage Extremes
6
5
4
3
2
3.25
3.20
V = 13.5 V
I
T = −40°C
J
T = 25°C
J
3.15
3.10
3.05
T = 125°C
J
Reset
1
0
3.00
2.95
10
V
20
30
40
−40 −20
0
20 40 60 80 100 120 140
, INHIBIT INPUT VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
INH
J
Figure 29. Inhibit Input Current at Inhibit Input
Voltage Extremes
Figure 30. Reset Trigger Threshold vs.
Junction Temperature
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NCV4299
35
30
25
20
1.50
1.45
1.40
V = 13.5 V
I
V = 13.5 V
I
C
D
= 100 nF
V
V
SI High
1.35
1.30
SI Low
15
10
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 31. Reset Delay Time vs. Junction
Temperature
Figure 32. Sense Threshold vs. Junction
Temperature
8
7
6
5
4
3
2
1.15
1.14
1.13
T = 125°C
J
1.12
1.11
1.10
1.09
1.08
1.07
T = −40°C
J
T = 25°C
J
V = 13.5 V
I
1
0
1.06
1.05
V
= V
− V
Imin Q
V
= 1 V
DR
D
−40 −20
0
20
40 60
80 100 120 140
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
I , OUTPUT CURRENT (mA)
Q
Figure 33. Delay Capacitor Charge Current vs.
Junction Temperature
Figure 34. Drop Voltage vs. Output Current
3.0
2.5
2.0
1.5
1.4
1.3
1.2
1.1
V = 13.5 V
I
V
UD
1.5
1.0
V
LD
0.5
0
1.0
0.9
−40
0
40
80
120
160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 35. Switching Voltage VUD and VLD vs.
Junction Temperature
Figure 36. Reset Adjust Switching Threshold
vs. Junction Temperature
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12
NCV4299
1.5
1.0
40
35
30
25
20
T = 25°C
J
0.5
0
I
= 10 mA
I
= 1 mA
Q
Q
15
10
0
10
20
30
40
−40
0
40
80
120
160
V , INPUT VOLTAGE (V)
I
T , JUNCTION TEMPERATURE (°C)
J
Figure 37. Current Consumption vs. Input
Voltage
Figure 38. RRO, RSO Resistance vs. Junction
Temperature
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NCV4299
APPLICATION DESCRIPTION
NCV4299
Other features of the regulator include an undervoltage
reset function and a sense circuit. The reset function has an
adjustable time delay and an adjustable threshold level. The
sense circuit trip level is adjustable and can be used as an
early warning signal to the controller. An inhibit function
that turns off the regulator and reduces the current
consumption to less than 1.0 mA is a feature available in the
14 pin package.
The NCV4299 is a family of precision micropower
voltage regulators with an output current capability of
150 mA at 5.0 V and 3.3 V.
The output voltage is accurate within "2% with a
maximum dropout voltage of 0.5 V at 100 mA. Low
quiescent current is a feature drawing only 90 mA with a
100 mA load. This part is ideal for any and all battery
operated microprocessor equipment.
Output Regulator
Microprocessor control logic includes an active reset
output RO (with delay), and a SI/SO monitor which can be
used to provide an early warning signal to the
microprocessor of a potential impending reset signal. The
use of the SI/SO monitor allows the microprocessor to finish
any signal processing before the reset shuts the
microprocessor down. Internal output resistors on the RO
and SO pins pulling up to the output pin Q reduce external
component count. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and
the device consumes less that 1.0 mA of quiescent current.
The active reset circuit operates correctly at an output
voltage as low as 1.0 V. The reset function is activated
during the powerup sequence or during normal operation if
the output voltage drops outside the regulation limits.
The reset threshold voltage can be decreased by the
connection of an external resistor divider to the RADJ lead.
The regulator is protected against reverse battery, short
circuit, and thermal overload conditions. The device can
withstand load dump transients making it suitable for use in
automotive environments.
The output is controlled by a precision trimmed reference.
The PNP output has saturation control for regulation while
the input voltage is low, preventing oversaturation. Current
limit and voltage monitors complement the regulator design
to give safe operating signals to the processor and control
circuits.
Stability Considerations
The input capacitor C is necessary for compensating
I
input line reactance. Possible oscillations caused by input
inductance and input capacitance can be damped by using a
resistor of approximately 1.0 W in series with C .
I
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
NCV4299 Circuit Description
The low dropout regulator in the NCV4299 uses a PNP
pass transistor to give the lowest possible dropout voltage
capability. The current is internally monitored to prevent
oversaturation of the device and to limit current during over
current conditions. Additional circuitry is provided to
protect the device during overtemperature operation.
The regulator provides an output regulated to 2%.
The value for the output capacitor C shown in Figures 39
Q
and 40 should work for most applications, however, it is not
necessarily the optimized solution. Stability is guaranteed at
values C w 22 mF and an ESR v 5.0 W within the
Q
operating temperature range. Actual limits are shown in a
graph in the typical performance characteristics section.
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14
NCV4299
V
I
Q
V
DD
BAT
C *
I
R
R
C **
RADJ1
Q
0.1 mF
22 mF
RADJ
RADJ2
D
R
S11
C
D
SI
R
S12
I/O
SO
RO
GND
I/O
*C required if regulator is located far from the power supply filter.
I
**C required for stability. Cap must operate at minimum temperature expected.
Q
Figure 39. Test and Application Circuit Showing all Compensation and Sense
Elements for the 8 Pin Package Part
V
I
Q
V
DD
BAT
C *
I
R
R
C **
RADJ1
Q
0.1 mF
22 mF
RADJ
RADJ2
D
R
S11
C
D
SI
R
S12
INH
INH
SO
I/O
RO
GND
I/O
*C required if regulator is located far from the power supply filter.
I
**C required for stability. Cap must operate at minimum temperature expected.
Q
Figure 40. Test and Application Circuit Showing all Compensation and Sense
Elements for the 14 Pin Package Part with Inhibit Function
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15
NCV4299
Reset Output (RO)
the delay timer (V ) drops below the lower threshold
D
A reset signal, Reset Output (RO, low voltage) is
voltage V , the reset output voltage V is brought low to
LD
RO
generated as the IC powers up. After the output voltage V
reset the processor.
Q
increases above the reset threshold voltage V , the delay
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
RT
timer D is started. When the voltage on the delay timer V
D
passes V , the reset signal RO goes high. A discharge of
UD
the delay timer (V ) is started when V drops and stays
guaranteeing that RO is valid for V as low as 1.0 V.
D
Q
Q
below the reset threshold voltage V . When the voltage of
RT
V
I
t
< t
RR
V
Q
V
RT
t
t
t
I
C
dV
dt
D
D
+
V
D
V
UD
V
LD
t
RR
t
d
V
RO
V
,
RO SAT
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Figure 41. Reset Timing Diagram
Reset Delay (D)
Reset Adjust (RADJ)
The reset threshold V can be decreased from a typical
The reset delay circuit provides a delay (programmable by
capacitor C ) on the reset output RO lead. The delay lead D
RT
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figures 39 and 40. The resistor divider keeps the
D
provides charge current I (typically 8.0 mA) to the external
D
delay capacitor C during the following times:
D
voltage above the V
, (typ. 1.35 V), for the desired
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device
is back in regulation. The delay capacitor is
RADJ,TH
input voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
set to discharge when the regulation (V , reset
threshold voltage) has been violated. When
RT
V
+ V
RADJ, TH
· (R
ADJ1
) R
)ńR
ADJ2
THRES
ADJ2
(eq. 1)
the delay capacitor discharges to down to V
the reset signal RO pulls low.
,
LD
If the reset adjust option is not needed, the RADJ−pin
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.65 V).
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16
NCV4299
Setting the Delay Time
The delay time is set by the delay capacitor C and the
Sense Input (SI)/Sense Output (SO) Voltage Monitor
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figures 39 and 40). The
typical threshold is 1.35 V on the SI Pin.
D
charge current I . The time is measured by the delay
D
capacitor voltage charging from the low level of V
to the
D,sat
higher level V . The time delay follows the equation:
UD
(eq. 2)
t
+ [C (V −V )]ńI
UD D, sat D
d
D
Example:
Using C = 100 nF.
D
Use the typical value for V
Use the typical value for V = 1.8 V.
Use the typical value for Delay Charge Current I = 6.5 mA.
= 0.1 V.
D,sat
UD
D
(eq. 3)
t
+ [100 nF(1.8−0.1 V)]ń6.5 mA + 26.2 ms
d
Signal Output
When the output voltage V drops below the reset
Q
Figure 42 shows the SO Monitor waveforms as a result of
the circuits depicted in Figures 39 and 40. As the output
threshold voltage V , the voltage on the delay capacitor V
RT
D
starts to drop. The time it takes to drop below the lower
threshold voltage of V is the reset reaction time, t . This
time is typically 1.0 ms for a delay capacitor of 0.1 mF. The
voltage V falls, the monitor threshold V
This causes the voltage on the SO output to go low sending
a warning signal to the microprocessor that a reset signal may
is crossed.
Q
SI,LOW
LD
RR
reset reaction time can be estimated from the following
occur in a short period of time. T
is the time the
WARNING
relationship:
microprocessor has to complete the function it is currently
working on and get ready for the reset shutdown signal.
(eq. 4)
t
+ 10 nsńnF C
D
RR
Sense
Input
Voltage
V
V
SL, High
Q
V
SL, Low
S
I
V
SI,LOW
t
Sense
Output
V
RO
t
t
PD SO HL
PD SO LH
High
S
O
Low
T
WARNING
t
Figure 42. SO Warning Timing Waveform
Figure 43. Sense Timing Diagram
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator is:
I is the quiescent current the regulator consumes at I
.
q
Q(max)
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
qJA
(eq. 6)
R
+ (150°C−T )ńP
qJA
A
D
P
+ [V
−V
] I
) V Iq
I(max)
D(max)
I(max) Q(min) Q(max)
The value of R
can then be compared with those in the
qJA
(eq. 5)
package section of the data sheet. Those packages with
’s less than the calculated value in Equation 6 will keep
where:
R
qJA
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the application,
I(max)
Q(min)
Q(max)
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required.
and
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17
NCV4299
Heatsinks
where:
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
R
R
R
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
qJC
qCS
qSA
R
appears in the package section of the data sheet. Like
qJC
R
qJA
, it too is a function of package type. R
and R
are
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers. Thermal, mounting, and
heatsinking are discussed in the ON Semiconductor
application note AN1040/D, available on the
ON Semiconductor website.
determine the value of R
:
qJA
(eq. 7)
R
qJA
+ R
qJC
) R ) R
qCS qSA
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18
NCV4299
SOIC 8 LEAD
1000
100
10
2
Cu Area = 10 mm , 1.0 oz
2
25 mm , 1.0 oz
2
100 mm , 1.0 oz
2
250 mm , 1.0 oz
2
500 mm , 1.0 oz
1
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (sec)
Figure 44. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log−Log)
1000
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
1
0.1
Single Pulse (SOIC−8)
0.01
Psi LA (SOIC−8)
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.1
1
10
100
1000
Pulse Time (sec)
Figure 45. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)
(PCB = 50 mm2 1 oz)
1000
50% Duty Cycle
20%
10%
100
10
1
5%
2%
1%
0.1
Single Pulse (SOIC−8)
0.01
Psi LA (SOIC−8)
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.1
1
10
100
1000
Pulse Time (sec)
Figure 46. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)
(PCB = 250 mm2 1 oz)
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19
NCV4299
SOIC 14 LEAD
1000
100
10
2
Cu Area = 10 mm , 1.0 oz
2
25 mm , 1.0 oz
2
100 mm , 1.0 oz
2
250 mm , 1.0 oz
2
500 mm , 1.0 oz
1
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (sec)
Figure 47. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log−Log)
1000
100
10
50% Duty Cycle
20%
10%
5%
2%
1
1%
0.1
Single Pulse (SOIC−14)
0.01
Psi LA (SOIC−14)
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Time (sec)
Figure 48. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)
(PCB = 50 mm2 1 oz)
100
50% Duty Cycle
20%
10%
5%
2%
1%
10
1
0.1
Single Pulse (SOIC−14)
0.01
Psi LA (SOIC−14)
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.1
1
10
100
1000
Pulse Time (sec)
Figure 49. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)
(PCB = 250 mm2 1 oz)
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20
NCV4299
ORDERING INFORMATION
†
Device
NCV4299D1
Package
Shipping
SO−8
98 Units/Rail
98 Units/Rail
NCV4299D1G
SO−8
(Pb−Free)
NCV4299D1R2
SO−8
2500 Tape & Reel
2500 Tape & Reel
NCV4299D1R2G
SO−8
(Pb−Free)
NCV4299D2
SO−14
55 Units/Rail
55 Units/Rail
NCV4299D2G
SO−14
(Pb−Free)
NCV4299D2R2
SO−14
2500 Tape & Reel
2500 Tape & Reel
NCV4299D2R2G
SO−14
(Pb−Free)
NCV4299D233G
SO−14
(Pb−Free)
55 Units/Rail
NCV4299D233R2G
SO−14
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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21
NCV4299
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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22
NCV4299
PACKAGE DIMENSIONS
SO−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
K
M
P
R
_
_
_
_
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NCV4299/D
相关型号：
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