NCV57255DR2G [ONSEMI]
Isolated Dual-Channel IGBT Gate Driver;
| 型号： | NCV57255DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Isolated Dual-Channel IGBT Gate Driver 栅 双极性晶体管 |
| 文件： | 总24页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Isolated Dual Channel
IGBT/MOSFET Gate Driver
1
SOIC−16
D SUFFIX
NCD57252, NCD57253,
NCD57255, NCD57256,
NCV57252, NCV57253,
NCV57255, NCV57256
NCx5725y are high−current two channel isolated IGBT/MOSFET
SOIC−16 WB
CASE 751B−05
CASE 751G−03
MARKING DIAGRAMS
16
5725y
AWLYYWWG
5725y
AWLYWWG
gate drivers with 2.5 or 5 kV * internal galvanic isolation from input
rms
to each output and functional isolation between the two output
channels. The device accepts 3.3 V to 20 V bias voltage and signal
levels on the input side and up to 32 V bias voltage on the output side.
The device accepts complementary inputs and offers separate pins for
Disable and Dead Time control for system design convenience.
Drivers are available in wide body SOIC−16 and narrow body
SOIC−16 package.
1
1
5725y
= Specific Device Code
y = 2, 3, 5 or 6
= Assembly Location
= Wafer Lot
A
WL
YY, Y
WW
G
= Year
= Work Week
= Pb−Free Package
Features
(See page 21)
• High Peak Output Current ( 6.5 A*, 3.5 A*)
• Configurable as a Dual Low−Side or Dual High−Side or Half−Bridge
PIN CONNECTIONS
Driver
• Programmable Overlap or Dead Time control
• Disable Pin to Turn Off Outputs for Power Sequencing
INA
INB
V
DDA
OUTA
GNDA
NC
• ANB Function to Offer Flexibility to Set up the Driver as
Half−bridge Driver Operating with a Single Input Signal
• IGBT/MOSFET Gate Clamping during Short Circuit
• Short Propagation Delays with Accurate Matching
V
DDI
GND
DIS
DT
NC
V
DDB
• Tight UVLO Thresholds on all Power Supplies
• 3.3 V, 5 V, and 15 V Logic Input
ANB
OUTB
GNDB
• 2.5 or 5 kV * Galvanic Isolation from Input to each Output
rms
V
DDI
and 1.5 kV Differential Voltage between Output Channels
rms
NCx5725y
x = D or V
• 1200 V Working Voltage (per VDE0884−11 Requirements)
• High Common Mode Transient Immunity
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of
this data sheet.
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
• EV Chargers
• Motor Control
• Uninterruptible Power Supplies (UPS)
• Industrial Power Supplies
• Solar Inverters
• Automotive Applications
*Depends on package variant, see Page 6, 21.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
June, 2023 − Rev. 5
NCD57252/D
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
V
V
DDI
V
DDA
UVLOI
DDI
UVLOA
RESET
CONTROL
INA
DT
OUTA
GNDA
RESET
CONTROL
NC
NC
Functional Isolation
Deadtime
and
Interlock
DIS
V
DDB
ANB
UVLOB
RESET
CONTROL
OUTB
GNDB
RESET
CONTROL
INB
GNDI
Figure 1. Simplified Block Diagram
+V2
INA
V
DDA
OUTA
INB
V1
V
DDI
GNDA
V
DDI
GND2
+V3
Functional
Isolation
V
DDB
GNDI
GND1
OUTB
DIS
DT
ANB
GNDB
GND3
Figure 2. Typical Application, High and Low Side IGBT Gate Drive
*Depends on package variant, see Page 6, 21.
www.onsemi.com
2
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
+V2
V
DDA
INA
OUTA
INB
V1
V
V
DDI
GNDA
DDI
GND2
+V3
Function
Isolation
GNDI
V
DDB
GND1
OUTB
DIS
DT
ANB
GNDB
GND3
Figure 3. Typical Application, Two Channels IGBT Gate Drive
+V2
V
INA
INB
DDA
OUTA
V1
V
DDI
GNDA
V
DDI
GND2
+V3
Functional
Isolation
V
DDB
GNDI
GND1
OUTB
DIS
DT
ANB
GNDB
GND3
Figure 4. Typical Application, High and Low Side IGBT Gate Drive with PWM Controller
−
*Depends on package variant, see Page 6, 21.
www.onsemi.com
3
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
INA
1
Input
A non-inverting gate driver input that defines OUTA. It has an equivalent pull−down resistor of 125 kW
to ensure that output is low in the absence of an input signal.
A positive or negative going pulse with pulse width longer than maximum value of t
before OUTA reacts.
is required at INA
MIN2
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
the same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
INB
2
Input
A non−inverting gate driver input that defines OUTB. It has an equivalent pull−down resistor of 125 kW
to ensure that output is low in the absence of an input signal.
A positive or negative going pulse with pulse width longer than maximum value of t
before OUTB reacts.
is required at INB
MIN2
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
the same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
V
DDI
3, 8
Power Low voltage side power supply. A good quality bypassing capacitor is required from this pin to GNDI
and should be placed close to the pins for best results.
The under voltage lockout (UVLOI) circuit enables the device to operate at power on when a typical
supply voltage higher than V
Please see Figure 7 and 8 for more details.
is present.
−
−
UVLOI OUT ON
GNDI
DIS
4
5
Power Low voltage side ground.
Input
Input
A high level on disable pin turns both OUTA and OUTB low simultaneously regardless of the states
of INA, INB, DT and ANB. Minimum pulse width filter and propagation delays apply. It has an equivalent
pull−down resistor of 125 kW to ensure that OUTA and OUTB react to INA, INB, DT and ANB in the
absence of an input signal.
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
the same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
DT
6
7
A deadtime pin is used to configure the two outputs sequence. The deadtime (t ) and interlocking logic
DT
between INA and INB is defined by the value of the external resistor (R ) connected between DT pin
DT
and GNDI. The deadtime can be estimated as t (ns) ≈ 10 x R (kW). If DT pin is pulled up to VDDI
DT
DT
for disabling the deadtime and interlocking logic the OUTA and OUTB can be high simultaneously.
Minimum deadtime will be observed between OUTA and OUTB when DT pin is left floating.
Allowed resistance between this pin and GNDI is in range of 5 to 500 kW.
Maximum voltage on this pin is V
Corresponding waveforms are on Figure 5.
.
DDI
ANB
Input
A high signal on ANB (A−and−B) pin enables OUTA and OUTB as complementary outputs from one
PWM input signal on INA. INB must be connected to INA when ANB is high. ANB should be kept low
when OUTA and OUTB are controlled individually by INA, INB. It has an equivalent pull−down resistor
of 100 k to ensure that ANB pin will not be floating. Leaving this pin floating for proper security features
is not recommended.
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
the same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
GNDB
OUTB
9
Power Ground for channel B.
10
Output Output of channel B on the high voltage side. It has galvanic isolation from low voltage side and from
channel A. OUTB provides the appropriate drive voltage and source/sink current to the IGBT/MOSFET
gate. OUTB is actively pulled low during startup, when DIS is high and under UVLOB, UVLOI condition.
INB must be connected to INA when ANB is high.
There is interlocking logic that prevents OUTA and OUTB cross conduction when DT pin is not connected
to V
.
DDI
V
DDB
11
Power High voltage side power supply for channel B. A good quality bypassing capacitor is required from this pin
to GNDB and should be placed close to the pins for best results.
The under voltage lockout (UVLOB) circuit enables the device to operate at power on when a typical
supply voltage higher than V
Please see Figure 9 and 10 for more details.
is present.
−
−
UVLOB OUT ON
NC
12, 13
14
−
Not connected internally.
GNDA
OUTA
Power Ground for channel A.
15
Output Output of channel A on the high voltage side. It has galvanic isolation from low voltage side and from
channel B. OUTA provides the appropriate drive voltage and source/sink current to the IGBT/MOSFET
gate. OUTA is actively pulled low during startup, when DIS is high and under UVLOA, UVLOI condition.
There is interlocking logic that prevents OUTA and OUTB cross conduction when DT pin is not
connected to V
.
DDI
www.onsemi.com
4
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 1. FUNCTION DESCRIPTION (continued)
Pin Name
No.
I/O
Description
V
DDA
16
Power High voltage side power supply for channel A. A good quality bypassing capacitor is required from this pin
to GNDA and should be placed close to the pins for best results.
The under voltage lockout (UVLOA) circuit enables the device to operate at power on when a typical
supply voltage higher than V
Please see Figure 9 and 10 for more details.
is present.
−
−
UVLOA OUT ON
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Min
−
Typ
I−IV
I−IV
I−IV
I−IV
I−III
−
Max
−
Unit
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
< 150 V
RMS
RMS
RMS
RMS
< 300 V
< 450 V
< 600 V
−
−
−
−
−
−
< 1000 V
−
−
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
600
−
−
40/100/21
2
−
Pollution Degree (DIN VDE 0110/1.89)
−
−
V
Input−to−Output Test Voltage, Method b, V
× 1.875 = V , 100%
2250
−
−
V
V
PR
IORM
PR
PK
Production Test with t = 1 s, Partial Discharge < 5 pC
m
V
IORM
Maximum Repetitive Peak Voltage
Maximum Working Insulation Voltage
1200
870
−
−
−
−
PK
V
IOWM
V
RMS
V
IOTM
Highest Allowable Over Voltage
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
V
PK
4200
8400
−
−
−
−
E
External Creepage
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
mm
mm
mm
CR
4.0
8.0
−
−
−
−
E
External Clearance
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
CL
4.0
8.0
−
−
−
−
DTI
Insulation Thickness
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
8.65
17.3
−
−
−
−
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
150
264
−
−
−
−
°C
T
Case
P
mW
mW
S,INPUT
P
Safety Limit Values – Maximum Values in Failure; Output Power
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
S,OUTPUT
796
1136
−
−
−
−
9
R
Insulation Resistance at TS, V = 500 V
−
−
W
IO
IO
10
www.onsemi.com
5
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Symbol
Parameter
Supply voltage, low voltage side
Minimum
−0.3
Maximum
Unit
V
V
−GNDI
−GNDA
−GNDB
22
36
36
DDI
V
Supply voltage, high voltage side, channel A
Supply voltage, high voltage side, channel B
Gate driver output voltage, channel A
Gate driver output voltage, channel B
−0.3
V
DDA
DDB
V
−0.3
V
V
GNDA − 0.3
GNDB − 0.3
V
DDA
V
DDB
+ 0.3
+ 0.3
V
OUTA
OUTB
V
V
I
Gate−driver output sourcing current
A
PK−SRC
(maximum pulse width = 10 ms, minimum period = 5 ms,
V
– GNDA = V
(NCx57252, NCx57253)
(NCx57255, NCx57256)
– GNDB = 15 V)
DDA
DDB
−
−
6.5
3.5
I
Gate−driver output sinking current
A
PK−SNK
(maximum pulse width = 10 ms, minimum period = 5 ms,
V
DDA
– GNDA = V
– GNDB = 15 V )
DDB
(NCx57252, NCx57253)
(NCx57255, NCx57256)
−
−
6.5
3.5
t
Maximum Short Circuit Clamping Time
(I = I = 500 mA)
−
10
ms
CLP
OUTA_CLAMP
OUTB_CLAMP
V
LIM
−GNDI
Voltage at INA, INB, DIS, DT, ANB
−0.3
V
DDI
+ 0.3
V
PD
Power Dissipation (Note 3)
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
mW
−
−
1400
1060
T (max)
Maximum Junction Temperature
−40
−65
−
150
150
4
°C
°C
kV
kV
−
J
T
STG
Storage Temperature Range
ESDHBM
ESDCDM
MSL
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Moisture Sensitivity Level
−
2
−
1
T
SLD
Lead Temperature Soldering Reflow, Pb−Free Versions
(Note 5)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. The minimum value is verified by characterization with a single pulse of 100 mA for 100 ms.
2
3. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm , 1 oz copper, 2 surface layers and 2 internal
power plane layers. Power dissipation is affected by the PCB design and ambient temperature.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Parameter
Conditions
Symbol
Value
164
Unit
2
Thermal Resistance, Junction−to−Air
SOIC−16 (NCx 57255, NCx 57256)
R
°C/W
100 mm , 2 oz Copper, 1 Surface Layer
q
JA
2
118
100 mm , 2 oz Copper, 2 Surface Layers
and 2 Internal Power Plane Layers
2
Thermal Resistance, Junction−to−Air
SOIC−16WB (NCx 57252, NCx 57253)
R
°C/W
81
57
100 mm , 2 oz Copper, 1 Surface Layer
q
JA
2
100 mm , 2 oz Copper, 2 Surface Layers
and 2 Internal Power Plane Layers
www.onsemi.com
6
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 5. RECOMMENDED OPERATING RANGES (Note 6)
Symbol
Parameter
Supply voltage, low voltage side
Minimum
UVLOI
UVLOA
UVLOB
GNDI
Maximum
Unit
V
V
−GNDI
−GNDA
−GNDB
20
32
32
DDI
V
Supply voltage, high voltage side, channel A
Supply voltage, high voltage side, channel B
Logic Input Voltage at INA, INB, DIS, DT, ANB
ꢀCommon Mode Transient Immunity (CMTI)
Ambient Temperature
V
DDA
DDB
V
V
V
IN
V
DDI
V
| dV /dt |
ISO
100
kV/ms
°C
T
A
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Table 6. ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Input−Output Isolation
Voltage
T = 25°C, Relative Humidity < 50%,
V
RMS
ISO, IINPUT
A
t = 1.0 minute, I
10 A, 50 Hz
I−O
TO OUTPUT
(Notes 7, 8, 9)
SOIC−16 (NCx 57255, NCx 57256)
2500
5000
−
−
−
−
SOIC−16WB (NCx 57252, NCx 57253)
V
Output−Output Isolation
Voltage
T = 25°C, Relative Humidity < 50%,
V
RMS
ISO, OUTPUT
TO OUTPUT
A
t = 1.0 minute, I
10 A, 50 Hz
I−O
(Notes 7, 8, 9)
SOIC−16 (NCx 57255, NCx 57256)
1500
1500
−
−
−
−
SOIC−16WB (NCx 57252, NCx 57253)
11
R
Isolation Resistance
V
I−O
= 500 V (Note 7)
10
W
ISO
7. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
2,500 VRMS for 1−minute duration is equivalent to 3,000 VRMS for 1−second duration.
9. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table.
Table 7. ELECTRICAL CHARACTERISTICS
V
DDI
= 5V, V
= V
= 15 V
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
V
V
Supply Under Voltage Output
3.1
V
V
V
UVLOI−OUT−ON
DDI
Enabled
V
V
DDI
Supply Under Voltage Output
2.4
0.1
UVLOI−OUT−OFF
Disabled
V
V
DDI
Supply Voltage Output
UVLOI−HYST
Enabled/Disabled Hysteresis
V
V
V
/V Supply Under Voltage
NCx57252/NCx57255
12.4
8.6
12.9
9.1
12
13.4
9.6
V
V
V
V
V
UVLOA−OUT−ON
DDA DDB
Output Enabled
UVLOB−OUT−ON
NCx57253/NCx57256
NCx57252/NCx57255
NCx57253/NCx57256
V
V
V
/V Supply Under Voltage
11.5
7.6
12.5
8.6
UVLOA−OUT−OFF
DDA DDB
Output Disabled
UVLOB−OUT−OFF
8.1
1.0
V
V
/V
Supply Voltage Output
0.8
UVLOA/B−HYST
DDA DDB
Enabled/Disabled Hysteresis
I
Low Voltage Side Quiescent Current
V
= V = 0 V
INB
2
4
mA
mA
QDDI−0
INA
I
Low Voltage Side Operating Current
at 50% Duty Cycle
INA PWM, INB Low (or INA Low,
INB PWM), f = 200 kHz
QDDI−50
I
Low Voltage Side Operating Current
at 100% Duty Cycle
INA or INB High
6
mA
QDDI−100
www.onsemi.com
7
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 7. ELECTRICAL CHARACTERISTICS (continued) V
= 5V, V
= V
= 15 V
DDI
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
, I
Parameter
Test Conditions
Min
Typ
Max
Unit
I
High Voltage Side Quiescent
Current
V
INA
= V = 0 V,
INB
Current per Channel
2
mA
QDDA−0 QDDB−0
I
,
High Voltage Side Operating
Current at 50% Duty Cycle
Current per Channel,
2
2
mA
mA
QDDA−50
I
f = 200 kHz, C = 1 nF
QDDB−50
G
I
,
High Voltage Side Operating
Current at 100% Duty Cycle
Current per Channel
QDDA−100
I
QDDB−100
LOGIC INPUT
V
V
, V
,
Low Level Input Voltage
High Level Input Voltage
Input Hysteresis
Level scale for V = 3.3 to 5 V
DDI
0.3 ×
V
DDI
V
V
V
INAL
INBL
for V
> 5 V is the same
DDI
, V
DISL ANBL
as for V
= 5 V
DDI
V
V
, V
INBH
,
Level scale for V = 3.3 to 5 V
DDI
0.7 ×
V
DDI
INAH
for V
> 5 V is the same
DDI
DDI
, V
DISH ANBH
as for V
= 5 V
V
V
V
,
,
,
Level scale for V
= 3.3 to 5 V
0.15 ×
V
DDI
INA−HYS
INB−HYS
DIS−HYS
DDI
for V
> 5 V is the same
DDI
as for V
= 5 V
DDI
V
ANB−HYS
V
V
, V
,
Negative Input Transient
50 ns
−5
V
INAN
INBN
, V
DISN ANBN
(Note 10)
I
I
, I
,
Logic “1” Input Bias Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
V
V
= V
= V
= V
= V
= V
= V
= V
=
50
50
1
mA
mA
mA
INAH INBH
INA
DDI
INB
DIS
DIS
DIS
ANB
ANB
ANB
= 3.3 V
, I
DISH ANBH
I
I
, I
, I
,
V
INA
V
DDI
= V
=
INAH INBH
INB
= 20 V
DISH ANBH
I
, I
,
V
INA
= V
= 0 V
INAL INBL
INB
I
, I
DISL ANBL
DRIVER OUTPUT
V
V
, V
, V
Output Low State
Output High State
I
I
= 200 mA, T = 25°C
0.1
0.22
0.5
V
V
A
OUTAL1
OUTBL1
SINK
A
= 200 mA, T = −40°C to 125°C
OUTAL2
OUTBL2
SINK
A
V
V
, V
, V
I
I
= 200 mA, T = 25°C
14.7
14.8
OUTAH1
OUTBH1
SRC
A
= 200 mA, T = −40°C to 125°C 14.2
OUTAH2
OUTBH2
SRC
A
I
I
Peak Driver Current, Sink (Note 10)
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
PK−SNK1
3.5
6.5
Peak Miller Plateau Current, Sink
(Note 10)
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
V
= V
= 6 V
A
PK−SNK2
OUTA
OUTB
(near IGBT Miller Plateau)
3
6
I
I
Peak Driver Current, Source (Note 10)
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
A
A
PK−SRC1
3.5
6.5
Peak Miller Plateau Current, Source
(Note 7)
SOIC−16 (NCx 57255, NCx 57256)
SOIC−16WB (NCx 57252, NCx 57253)
V
= V
= 9 V
PK−SRC2
OUTA
OUTB
(near IGBT Miller Plateau)
3
6
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
V
,
I
= I = 500 mA
OUTB
0.4
0.6
V
CLAMP−OUTA
OUTA
V
(V
(V
− V
− V
),
(pulse test, t
= 10 ms)
CLAMP−OUTB
CLAMP−OUTA
CLAMP−OUTB
DDA
DDB
CLPmax
)
www.onsemi.com
8
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Table 7. ELECTRICAL CHARACTERISTICS (continued) V
= 5V, V
= V
= 15 V
DDI
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
DYNAMIC CHARACTERISTIC
Parameter
Test Conditions
Min
Typ
Max
Unit
t
OUTA High Propagation Delay
OUTA Low Propagation Delay
Propagation Delay Distortion
C
= 10 nF, V to 10%
INAH
40
40
60
60
0
80
80
20
80
80
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD−ON−A
LOAD
of Output Change for PW > 150 ns
C = 10 nF, V to 90%
LOAD
t
PD−OFF−A
INAL
of Output Change for PW > 150 ns
t
PW >150 ns
−20
40
DISTORT−A
(Channel A) (t
− t
)
)
PD−ON−A
PD−OFF−A
t
OUTB High Propagation Delay
OUTB Low Propagation Delay
Propagation Delay Distortion
C
= 10 nF, V to 10%
INBH
60
60
0
PD−ON−B
LOAD
of Output Change for PW > 150 ns
t
C
= 10 nF, V to 90%
40
PD−OFF−B
DISTORT−B
LOAD
INBL
of Output Change for PW > 150 ns
t
PW >150 ns
−20
−20
−20
(Channel B) (t
− t
PD−OFF−B
PD−ON−B
t
Rising Edge Propagation Delay
Distortion (t − t
PW >150 ns
PW >150 ns
0
DISTORT−ON
)
PD−ON−A
PD−ON−B
t
Falling Edge Propagation Delay
0
DISTORT−OFF
Distortion (t
− t
PD−OFF−B
)
PD−OFF−A
t
t
Rise Time for Both Channel A and B
Fall Time for Both Channel A and B
Deadtime between channels
C
= 1 nF, 10% to 90%
LOAD
12
10
RISE
FALL
of Output Change
C
= 1 nF, 90% to 10%
LOAD
of Output Change
t
DT
DT pin Float
<20
5
ns
ms
ns
ns
R
R
= 500 kW
= 20 kW
DT
DT
200
60
t
Disable Delay
DIS
Positive pulse (L−H−L), T = 25°C
10
10
ns
ns
ns
ns
t
Input Pulse Width for no output
A
MIN1
Negative pulse (H−L−H), T = 25°C
A
Positive pulse (L−H−L), T = 25°C
40
40
t
Input Pulse Width for guaranteed
output
A
MIN2
Negative pulse (H−L−H), T = 25°C
A
t
UVLOI/UVLOA/UVLOB Fall Delay
UVLOI/UVLOA/UVLOB Rise Delay
(Note 10)
(Note 10)
1.5
20
ms
ms
UVF
t
10
UVR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Values based on design and/or characterization.
11. PW = Pulse Width
Modes of Operation
the driver generates dead−time which is adjustable by DT
pin.
The typical application schematics are on Figure 2 and 3.
The NCx5725y can operate in 3 distinct modes:
1. The low−side, high−side half−bridge driver with two
inputs and programmable dead−time.
2. The low−side, high−side half−bridge driver with
one input and programmable dead−time.
3. The two independent (potentially overlapping)
channels with two inputs.
• ANB pin has to be connected to GNDI in this mode.
• The dead−time is set by resistor R connected between
DT
DT pin and GNDI. Adjusting dead−time is described in
the section Dead−time (DT).
nd
2
mode – half−bridge driver with one input and
st
1
mode – half−bridge driver with two inputs and
st
adjustable dead−time is very similar to 1 mode but just
high−side PWM is needed. The low−side PWM is internally
generated by the driver. Interlock and dead−time generator
adjustable dead−time is for applications where you have
high−side and low−side PWM available. The driver
provides interlock function to prevent activation of
high−side and low−side outputs at the same time. In addition
st
works the same as in 1 mode.
www.onsemi.com
9
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
enabled. The dead−time can be adjusted in range from
• Both INA and INB have to be connected together.
200 ns (R ≈ 20 kW) to 5 ms (R ≈ 500 kW). Dead−time
DT
DT
• ANB pin has to be connected to V . This enables the
DDI
can be estimated by the equation t (ns) ≈ 10 x R (kW).
DT
DT
internal complementary low−side PWM generator.
With high R values the potential noise pick−up on high
DT
• The dead−time is set by resistor R connected between
DT
impedance of R should be considered. R should be
DT
DT
DT pin and GNDI. Adjusting dead−time is described in
the section Dead−time (DT).
as close to driver pins as possible and the loop should be
minimized.
rd
3 mode – driver with two independent channels and two
• If R is below 20 kW the DT is not closely following the
DT
inputs is different from previous two modes because it
allows for completely independent and even overlapping
PWMs to drive the outputs individually.
equation but dead−times lower than 200 ns could be
achieved. The lowest allowed value of R = 5 kW which
DT
reduces the dead−time to about 70 ns.
• The ANB pin has to be connected to GNDI.
The Figures 2 and 3 illustrate the behavior of the
NCx5725y in 1 mode (high−side, low−side half−bridge
driver with two inputs). The outputs for various input PWM
combinations are shown in Figure 5.
The dead−time is a time from low−side output going low
to high−side output going high or from high−side output
going low to low side output going high. The overlap is
a situation where both signals are high at the same time.
Overlap causes cross conduction in the half−bridge and must
be avoided.
• DT pin has to be connected to V . This disables the
DDI
st
interlock function and dead−time generator and allows
the overlapping PWMs. So the channel A and B can be
driven completely independently.
Dead−Time (DT)
The dead−time pin is controlling the integrated interlock
and dead−time generator.
• If DT pin is connected to V
the interlock and
dead−time generator are disabled. The channels A and B
DDI
In the “Non−overlap and Dead−time are met” column in
Fig. 5, the channel A PWM, INA (high−side), and channel
B PWM, INB (low−side), are not overlapping and have
sufficient dead−time. Therefore, the driver does not apply
corrections to the signals and passes them as they are to their
respective output.
are completely independent.
• If DT pin is floating the interlock is enabled but dead−time
generator is disabled. There is a minimal dead−time
shorter than 20 ns.
• If there is a resistor R connected between the DT pin
DT
and GNDI the interlock and dead−time generator are both
Figure 5. Deadtime, Interlock and Output Minimum Pulse Width
In the “Dead−time corrected” column, the high−side and
low−side signals are not overlapping but the dead−time
value is less than the value set through the DT pin.
Consequently, the driver increases the dead−time value to
the value set by the DT pin.
In the “Overlap and Dead−time corrected” column, the
high−side and low−side input signals are high at the same
time (overlapping). This condition could cause
cross−conduction in the half−bridge. Therefore, the driver’s
interlock function trims signal OUTB which is going low
www.onsemi.com
10
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Edge Triggered Inputs
when INA goes high, and not when INB goes low. The driver
also inserts the dead−time set through DT pin, thus the
output pulses are not overlapping and cross−conduction in
the half−bridge is avoided.
In the “Overlap, Dead−time corrected and Short pulses
filtered out” column, the high−side and low side signals are
overlapping and could cause cross−conduction in the
half−bridge. Therefore, the driver’s interlock function trims
the output signals and a short spike remains on each output
signal. If the spike is shorter than tMIN1 (Minimum pulse
width filtering time), it will be suppressed and no output is
generated.
The INA, INB and DIS inputs are activated by a signal
edge (edge triggered), not with signal level. This means that
after power cycling the driver, a rising edge has to occur on
INA, INB for OUTA and OUTB to go high, respectively.
The same conditions apply if the output signals are disabled
through the DIS pin. Therefore, after DIS signal goes low,
a rising edge has to occur on INA, INB for OUTA and OUTB
to go high, respectively.
Under Voltage Lockout UVLOI, UVLOA, UVLOB
UVLOA and UVLOB ensures correct driving of the gates
of the IGBTs (NCx57252, NCx57255) or MOSFETs
(NCx57253, NCx57256). Driving the IGBT/MOSETS with
low gate voltage causes it to switch outside the saturation
region (in the linear region) which significantly increases
the power losses and there is a danger of damage.
In the “Overlap corrected” column the dead−time is met
but the signals are overlapping so just the non−overlapping
parts pass to the output.
Inputs INA, INB, DIS, ANB
UVLOI ensures correct transmission of the signals from
the primary side to the secondary side of the driver.
NCx5725y is equipped by edge triggered inputs in order
to prevent output pulse trimming. Therefore, after returning
from safe state to active state, a rising edge has to occur on
INA, INB in order to set OUTA and OUTB high,
respectively (see Figures 7, 8 and Figures 9, 10).
Unused inputs should be tied to GNDI.
Input Voltage Levels
The NCx5725y has a two modes for high and low levels
on all input pins:
1. For V
from 3.3 to 5 V the high and low input
DDI
levels are scaling with the V
as stated in the
DDI
Electrical characteristics table. Low input level is
0.3 × V , high input level is 0.7 × V
As a side effect of this feature is that the t
time is
UVR
.
DDI
DDI
always prolonged by a t
. The t
is the
UVR−spread
UVR−spread
2. For V
above 5 V the high and low input levels
DDI
delay caused by the time before next rising edge of PWM
signal comes.
clamp at the same value as for V
means the low input level is 0.3 × 5 = 1.5 V and the
high input level is 0.7 × 5 = 3.5 V.
= 5 V. That
DDI
Another note for the t
is that it is valid if the V
rises
UVR
DD2
from just below V
to V
. The
UVLO−OUT−OFF
UVLO−OUT−ON
cold−start time from V
= 0 V to PWM at the output
DDA(B)
VDDI
is t
+ startup time of the internal bias circuits. The whole
UVR
time is about 20 ms and the internal bias circuit startup time
is about 10 ms.
Clamping
Circuit
INA
(INB)
Figure 6. Input Pin Structure
www.onsemi.com
11
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
V
DDA
V
DDB
V
UVLOI-HYST
V
V
UVLOI-OUT-ON
UVLOI-OUT-OFF
V
DDI
t
t
t
t
t
UVF
UVF
UVR
UVR
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 7. Output Ramp−up and Ramp−down Times during UVLOI
V
DDA
V
DDB
V
V
UVLOI-OUT-ON
UVLOI-OUT-OFF
V
DDI
t
t
UVF
t
t
t
UVR
UVR
UVF
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 8. VDDI Glitch Filtering
www.onsemi.com
12
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
V
V
DDI
V
UVLOA,B-HYST
UVLOA,B-OUT-ON
UVLOA,B-OUT-OFF
V
V
/V
DDA DDB
t
t
t
UVR
t
t
UVR
UVF
UVR
UVF
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 9. Output Ramp−up and Ramp−down Times during UVLOA, UVLOB
V
DDI
V
V
UVLOA,B-OUT-ON
UVLOA,B-OUT-OFF
V
/V
DDA DDB
t
t
t
UVR
t
t
UVF
UVF
UVR
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 10. VDDA/VDDB Glitch Filtering
Power Supply
switching frequencies. They have to be connected to GNDA
and GNDB (See Figure 14 and 15).
Decoupling (VDDI, VDDA, VDDB)
Suitable external power capacitors are required for
reliable driving of IGBT/MOSFET gate with high current.
Parallel combination of 100 nF + 4,7 mF low ESR ceramic
capacitors is optimal for a wide range of applications using
IGBT/MOSFET. For reliable driving of IGBT modules
(containing several parallel IGBT’s) with a gate capacitance
over 10 nF a higher decoupling capacity is required
(typically 100 nF + 10 mF). Capacitors should be as close as
possible to the driver’s power pins. The recommended
layout is provided in the Figure 14.
Output Current on GNDA/GNDB
The NCx5725y has a high current, low−drop MOSFET
output stage. It is capable of driving IGBTs with gate
capacitance CG of up to 100 nF. For optimal
IGBT/MOSFET driving a few conditions have to be met:
• Low inductance (wide and short) traces from OUTA
(OUTB) to R and to IGBT/MOSFET gate and from
G
emitter (source) to GNDA (GNDB).
• Sufficient power rating of gate resistors RG.
• Reasonable combination of switching frequency f and
Cooling Polygons on GNDA/GNDB
It is important to provide cooling polygons if driving
IGBTs with higher gate capacitance values and using higher
gate capacitance C of the IGBT/MOSFET.
G
• Good V
and V
decoupling (discussed above).
DDA
DDB
• Sufficient cooling pads (discussed above).
www.onsemi.com
13
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
Low Inductance Traces
All the traces have to be as low inductance as possible due
to the high current path from the driver output to
High−speed
signals
10 mils
0.25 mm
10 mils
0.25 mm
IGBT/MOSFET gate. In practice that means wide tracks
which are as short as possible. Tracks also have to be routed
in order to not create big loops. The driving path (driver
output, RG, IGBT/MOSFET gate) and return path (IGBT
emitter/MOSFET source, GNDA or GNDB pin) have to be
routed as a pair and not enclosing other components.
Ground plane
Keep this space free
from traces, pads
and vias
40 mils
1 mm
40 mils
1 mm
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low−speed
signals
314 mils
(8 mm)
Disable (DIS) Pin
DIS (disable) pin allows to deactivate both outputs
independently of inputs INA, INB, DT, ANB.
If the pin is set high both OUTA and OUTB are set low
immediately.
If DIS is set low, the outputs OUTA/OUTB are restored
after rising edge is detected on the INA/INB respectively.
It has an internal pull−down resistor of 125 kW to ensure
that OUTA and OUTB react to INA, INB, DT and ANB in
the absence of an external signal. External pull−down
resistor 10−47 kW is recommended to prevent unwanted
DIS activation by external interference. Direct connection to
GNDI is recommended if the pin is not used.
Figure 12. SOIC−16WB Recommended Layer Stack
High-speed
signals
10 mils
10 mils
0.25 mm
0.25 mm
Ground plane
Keep this
space free
from traces,
pads and vias
40 mils
1 mm
40 mils
1 mm
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low-speed
signals
157 mils
(4 mm)
DISABLE
Figure 13. SOIC−16 Recommended Layer Stack
t
DIS
OUTX
Figure 11. Disable Function
NOTE: Purple – Recommended isolation gap.
Figure 14. Recommended Layout
(NCx57252, NCx57253)
Figure 15. Recommended Layout
(NCx57255, NCx57256)
www.onsemi.com
14
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(6)
(3)
(6)
(3)
(5)
(5)
(2)
(4)
(2)
(4)
(1)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
−0, I = 0 V, I = 0 V, D = 5 V
NA NB T
QDDI
(1) I
, I = 0 V, I = 0 V, D = 5 V
NB T
QDDI−0 NA
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
(2) I
(3) I
(4) I
(5) I
(6) I
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
QDDI−50 NA
NB
T
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 V
, I = 5 V, I = 0 V, D = 5 V
QDDI−100 NA
NB
T
QDDI−100 NA
NB
T
, I = 0 V, I = 0 V, D = 5 k
, I = 0 V, I = 0 V, D = 5 k
QDDI−0 NA
NB
T
QDDI−0 NA
NB
T
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
QDDI−50 NA
NB
T
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 k
, I = 5 V, I = 0 V, D = 5 k
QDDI−100 NA
NB
T
QDDI−100 NA
NB
T
(Note: V
DDI
= 5 V, V
DDA
= 15 V, V
= 15 V)
(Note: V
= 3.3 V, V
DDA
= 15 V, V
= 15 V)
DDB
DDI
DDB
Figure 17. IQDDI Supply Current, VDDI = 5 V
Figure 16. IQDDI Supply Current, VDDI = 3.3 V
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(5)
(6)
(3)
(5)
(2)
(6)
(2)
(4)
(1)
(3)
(4)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
, V
, V
, V
= 15 V, I = 0 V, I = 0 V, D = 5 V
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
, I = 0 V, I = 0 V, D = 5 V
QDDA−0 DDA NA NB T
QDDI−0 NA
NB
T
= 15 V, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
NA NB T
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
QDDA−50 DDA
QDDI−50 NA
NB
T
= 15 V, I = 5 V, I = 0 V, D = 5 V
NA NB T
, I = 5 V, I = 0 V, D = 5 V
QDDA−100 DDA
QDDI−100 NA
NB
T
, V
= 32 V, I = 0 V, I = 0 V, D = 5 V
NA NB T
, I = 0 V, I = 0 V, D = 5 k
QDDA−0 DDA
QDDI−0 NA
NB
T
, V
, V
= 32 V, I = 5 V/200 kHz/50%, I = 0 V, DT = 5 V
NA NB
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
QDDA−50 DDA
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 k
= 32 V, I = 5 V, I = 0 V, D = 5 V
QDDA−100 DDA NA NB T
QDDI−100 NA
NB
T
(Note: V
= 5 V, V
= 15 V)
(Note: V
= 20 V, V
DDA
= 15 V, V
= 15 V)
DDI
DDB
DDI
DDB
Figure 19. IQDDA Supply Current
Figure 18. IQDDI Supply Current, VDDI = 20 V
www.onsemi.com
15
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
20
15
10
5
8
7
6
5
4
3
2
1
0
(5)
(1)
(3)
(2)
(2)
(6)
(3)
(4)
(1)
0
−40 −20
0
20
40
60
80
100 120
1
10
100
1000
Temperature (5C)
Frequency (kHz)
(1) I
, V
= 15 V, I = 0 V, I = 0 V, D = 5 V
QDDB−0 DDB NA NB T
(2) I
(3) I
(4) I
(5) I
(6) I
, V
= 15 V, I = 0 V, I
= 15 V, I = 0 V, I = 5 V, D = 5 V
NA NB T
= 32 V, I = 0 V, I = 0 V, D = 5 V
NA NB T
5 V/200 kHz/50%, D = 5 V
(1) C = 1 nF
(2) C = 10 nF
G
(3) C = 100 nF
G
QDDB−50 DDB
NA
NB = T
G
, V
QDDB−100 DDB
, V
QDDB−0 DDB
, V
= 32 V, I = 0 V, I = 5 V/200 kHz/50%, D = 5 V
QDDB−50 DDB
NA
NB
T
(Note: V
= 5 V, V
= 15 V, V = 15 V, I = 5 V/50%, I = 0 V,
DDB NA NB
DDI
DDA
, V
= 32 V, I = 0 V, I = 5 V, D = 5 V
NA NB T
QDDB−100 DDB
D = V , ANB = GNDI, DIS = GNDI, R = 0 Ω)
T DDI G
(Note: V
= 5 V, V
= 15 V)
DDI
DDA
Figure 21. IQDDA (IQDDB) Supply Current
vs. Switching Frequency
Figure 20. IQDDB Supply Current
−0.1
−0.2
−0.3
−0.4
−0.5
28
27
26
25
24
23
22
21
(3)
(4)
(3)
(4)
(2)
(1)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(3) I
(2) I
(4) I
(2) I
(3) I
(4) I
(1) I
INAL
(1) I
DISL
INBL
ANBL
INBH
DISH
ANBH
INAH
(Note: V
= 3.3 V, V
= V
INB
= V
DIS
= V
ANB
= GNDI, V
= V
DDB
= 15 V)
(Note: V
= V
INA
= V
INB
= V
DIS
= V
ANB
= 3.3 V, V
= V
DDB
= 15 V)
DDI
INA
DDA
DDI
DDA
Figure 23. Input Bias Current − Logic “0”
Figure 22. Input Bias Current − Logic “1”
www.onsemi.com
16
Temperature (5
Temperature (5C)
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
41
40
39
38
37
36
35
34
33
32
−0.1
−0.2
−0.3
−0.4
−0.5
(3)
(4)
(2)
(3)
(4)
(1)
(2)
(1)
−40 −20
0
20
40
60
C)
80
100 120
−40 −20
0
20
40
60
80
100 120
(2) I
(3) I
(4) I
(3) I
DISL
(1) I
(2) I
(4) I
ANBL
(1) I
INBH
DISH
ANBH
INAH
INBL
INAL
(Note: V
= V
INA
= V
INB
= V
DIS
= V
ANB
= 5 V, V
= V
DDB
= 15 V)
(Note: V
= 5 V, V
= V
INB
= V
DIS
= V
ANB
= GNDI, V
= V
DDB
= 15 V)
DDI
DDA
DDI
INA
DDA
Figure 24. Input Bias Current − Logic “1”
Figure 25. Input Bias Current − Logic “0”
−0.1
−0.2
−0.3
−0.4
−0.5
49
48
47
46
45
44
43
42
41
40
39
38
37
(3)
(4)
(2)
(3)
(4)
(1)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(3) I
(2) I
(4) I
DDA
(2) I
(3) I
(4) I
(1) I
INAL
(1) I
DISL
INBL
ANBL
INBH
DISH
ANBH
INAH
(Note: V
= 20 V, V
= V
= V
DIS
= V
ANB
= GNDI, V
= V
DDB
= 15 V
(Note: V
= V
= V
INB
= V
DIS
= V
= 20 V, V
= V
DDB
= 15 V)
DDI
INA
INB
DDI
INA
ANB
DDA
Figure 26. Input Bias Current − Logic “1”
Figure 27. Input Bias Current − Logic “0”
www.onsemi.com
17
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
9,1
8,9
8,7
8,5
8,3
8,1
7,9
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
(1)
(3)
(1)
(3)
(2)
(2)
(4)
(4)
11.9
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(4) V
(1) V
UVLOA−OUT−OFF
UVLOA−OUT−ON
(2) V
(4) V
(1) V
UVLOA−OUT−OFF
UVLOA−OUT−ON
(3) V
UVLOB−OUT−ON
UVLOB−OUT−OFF
(3) V
UVLOB−OUT−ON
UVLOB−OUT−OFF
Figure 28. NCx57252 UVLOA and UVLOB
Threshold Voltage
Figure 29. NCx57253 UVLOA and UVLOB
Threshold Voltage
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.9
2.8
2.7
2.6
2.5
(3)
(2)
(1)
(1)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(1) V
UVLOI−OUT−OFF
UVLOI−OUT−ON
(1) V
(2) V
(3) V
UVLOB−HYST
UVLOI−HYST
UVLOA−HYST
Figure 31. UVLOx Enable/Disable Voltage
Hysteresis
Figure 30. UVLOI Threshold Voltage
www.onsemi.com
18
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
140
1.5
1.4
1.3
(1)
130
120
110
100
90
(1)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t
(1) t
(1) t
UVFB
UVFA
UVFI
Figure 32. UVLOI Fall Delay
Figure 33. UVLOA and UVLOB Fall Delay
1.1
84
82
80
78
76
74
72
70
1.05
1
(1)
(1)
(2)
(5)
(6)
(2)
(3)
0.95
0.9
0.85
0.8
(4)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) V
(2) V
CLAMP−OUTB
CLAMP−OUTA
(1) t
(3) t
(5) t
, V
= 3.3 V
= 5 V
= 20 V
(2) t
(4) t
(6) t
, V
= 3.3 V
, V = 5 V
PD−ON−B DD1
PD−ON−A DD1
PD−ON−B DD1
, V
PD−ON−A DD1
, V
, V = 20 V
PD−ON−B DD1
PD−ON−A DD1
Figure 34. IGBT Short Circuit Clamping Voltage
Figure 35. Propagation Delay Turn−on
www.onsemi.com
19
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
80
78
76
74
72
70
16.5
16
(1)
(2)
(4)
(1)
15.5
15
(3)
(2)
14.5
14
(5)
(6)
13.5
13
12.5
12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) t
(3) t
(5) t
, V
= 3.3 V
= 5 V
= 20 V
(2) t
, V = 3.3 V
, V = 5 V
(1) t
(2) t
FALL
PD−OFF−A DD1
PD−OFF−B DD1
RISE
, V
(4) t
PD−OFF−A DD1
PD−OFF−B DD1
, V
(6) t , V = 20 V
PD−OFF−B DD1
PD−OFF−A DD1
Figure 36. Propagation Delay Turn−off
Figure 37. Rise Time / Fall Time
76
74
72
70
68
18
16
14
12
10
8
(1)
(1)
(3)
(3)
(2)
6
4
2
(2)
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t , V
= 5 V
(3) t , V
= 20 V
(1) t , V
= 3.3 V
DT DDI
DT DDI
DT DDI
(3) t , V
= 20 V
(1) t , V
= 3.3 V
(2) t , V
= 5 V
DIS DD1
DIS DD1
DIS DD1
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
Figure 38. Disable Delay Time
Figure 39. Deadtime, DT pin FLOAT
www.onsemi.com
20
NCD57252, NCD57253, NCD57255, NCD57256, NCV57252, NCV57253, NCV57255,
NCV57256
TYPICAL CHARACTERISTICS
80
78
76
74
72
70
5.5
5.3
5.1
4.9
4.7
4.5
(1)
(2)
(3)
(1)
(2)
(3)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t , V
= 5 V
(1) t , V
= 3.3 V
(3) t , V
= 20 V
DT DDI
DT DDI
DT DDI
(2) t , V
= 5 V
(3) t , V
= 20 V
(1) t , V
= 3.3 V
DT DDI
DT DDI
DT DDI
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
Figure 41. Deadtime, DT pin 500 kW to GNDI
Figure 40. Deadtime, DT pin 5 kW to GNDI
ORDERING INFORMATION
†
Device
Package
Shipping
NCD57252DWR2G
NCV57252DWR2G*
NCD57253DWR2G
NCV57253DWR2G*
NCD57255DR2G
NCV57255DR2G*
NCD57256DR2G
NCV57256DR2G*
SOIC−16 Wide Body (Pb−Free)
SOIC−16 Wide Body (Pb−Free)
SOIC−16 Wide Body (Pb−Free)
SOIC−16 Wide Body (Pb−Free)
SOIC−16 Narrow body (Pb−Free)
SOIC−16 Narrow body (Pb−Free)
SOIC−16 Narrow body (Pb−Free)
SOIC−16 Narrow body (Pb−Free)
1,000 / Tape & Reel
1,000 / Tape & Reel
1,000 / Tape & Reel
1,000 / Tape & Reel
2,500 / Tape & Reel
2,500 / Tape & Reel
2,500 / Tape & Reel
2,500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
DATE 08 OCT 2021
1
SCALE 1:1
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明