NCV59745 [ONSEMI]
Linear Voltage Regulator - Bias Rail, Low Noise, Very Low Dropout, Programmable Soft-Start;
| 型号： | NCV59745 |
| 厂家： | 
ONSEMI |
| 描述： | Linear Voltage Regulator - Bias Rail, Low Noise, Very Low Dropout, Programmable Soft-Start |
| 文件： | 总12页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Linear Voltage Regulator -
Bias Rail, Low Noise, Very
Low Dropout, Programmable
Soft-Start
3 A
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NCV59745
Description
The NCV59745 is very low dropout low noise dual−rail voltage
regulator that is capable of providing an output current in excess of
3.0 A with a dropout voltage of 115 mV typ. at full load current. This
series contains fixed output voltage devices. The high output current
capability with high accuracy, broad bandwidth high PSRR and low
noise makes this VLDOs ideal for powering noise sensitive high speed
communication devices, high end FPGAs and microprocessors.
The NCV59745 is offered in QFNW20 4.0 mm x 4.0 mm package.
Features
QFNW20
MW SUFFIX
CASE 484AP
MARKING DIAGRAM
59745
V100A
ALLYWG
G
• Output Current in Excess of 3.0 A
• 0.25% Typical Accuracy Over Line and Load
• VIN Range: 0.8 V to 5.5 V
• VBIAS Range: 2.2 V to 5.5 V
A
LL
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Output Voltage Range: 0.8 V to 3.6 V
• Dropout Voltage: 105 mV typ. at 3 A
• Programmable Soft Start
• Open Drain Power Good Output
(Note: Microdot may be in either location)
• Low Noise, 6 mV
Typically
• Excellent Transient Response
RMS
PIN CONNECTIONS
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
20
1
• These are Pb−Free Devices, Wettable Flank for AOI
OUT
SNS
NC
PG
NC
IN
EN
SS
BIAS
NC
Applications
Thermal Pad
• High Speed Analog VCO, DAC, ADC
• FPGAs, DSPs, SerDes
• Imaging Sensors and ASICs
• Automotive, Telecom and Industrial Equipment Point of Load
Regulation
NCV59745
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 10 of this data sheet.
VIN
IN
PG
RPG
EN
CIN
VOUT
OUT
SNS
BIAS
SS
VBIAS
COUT
GND
CSS
CBIAS
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
April, 2020 − Rev. 3
NCV59745/D
NCV59745
Current
Limit
OUT
IN
BIAS
Active
Discharge*
VREF Voltage
Reference
+
+
-
ISS
SS
SNS
CSS
Discharge
UVLO
PG
-
Hysteresis
& Deglitch
Internal
Controller
+
EN
Thermal
Limit
0.9 x VREF
*Active output discharge function is present only in NCV59745A option devices.
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Name
IN
QFNW20
15−17
14
Description
Unregulated voltage input to the device.
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shut-
down mode. This pin must not be left floating.
SS
BIAS
PG
13
12
4
Soft−Start pin. A capacitor connected on this pin to ground sets the Soft − Start time.
Bias input voltage for error amplifier, reference, and internal control circuits.
Power−Good (PG) is an open−drain, active−high output that indicates the status of V
. When V
OUT
OUT
OUT
exceeds the PG trip threshold, the PG pin goes into a high−impedance state. When V
is below this
threshold the pin is driven to a low−impedance state. A pull−up resistor from 10 kW to 100 kW should be
connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
SNS
OUT
NC
2
Output voltage sense input pin. This pin must not be left floating.
1, 19, 20
Regulated output voltage. It is recommended that the output capacitor ≥ 10 mF (effective value).
3, 5−7, 9−11 No connection. Each one pin is “true NC” and can be left floating or connected to GND to allow better
thermal contact to the PCB top−side plane.
GND
8, 18
Ground pins. Both these pins must be connected to ground.
PAD/TAB
Should be soldered to the ground plane for increased thermal performance
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NCV59745
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
Input Voltage Range
V
IN
−0.3 to +6
−0.3 to +6
−0.3 to +6
−0.3 to +6
0 to +1.5
Bias Voltage Range
V
BIAS
V
Enable Voltage Range
V
V
EN
PG
PG
Power−Good Voltage Range
PG Sink Current
V
V
I
mA
V
SS Pin Voltage Range
V
SS
−0.3 to (V
+ 0.3) ≤ 6
BIAS
Output Sense Pin Voltage Range
Output Voltage Range
V
V
−0.3 to +6
V
SNS
OUT
OUT
−0.3 to (V + 0.3) ≤ 6
V
IN
Maximum Output Current
I
Internally Limited
Output Short Circuit Duration
Continuous Total Power Dissipation
Maximum Junction Temperature
Storage Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Indefinite
P
See Thermal Characteristics Table and Formula
D
T
+150
−55 to +150
2000
°C
°C
V
JMAX
T
STG
ESD
ESD
HBM
CDM
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Charged Device Model tested per AEC−Q100−011
Latch−up Current Maximum Rating 100 mA per AEC−Q100−004.
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, QFNW20, 4.0x4.0, 0.5P package
Thermal Resistance, Junction−to−Ambient (Note 5)
Thermal Resistance, Junction−to−Board (Note 6)
Thermal Resistance, Junction−to−Case (top)
Symbol
Value
Unit
RqJA
RqJB
40
3.6
27
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJC(bot)
YJT
Thermal Resistance, Junction−to−Case (bottom) (Note 7)
Characterisation Parameter, Junction−to−Top
3.6
1.0
3.5
Characterisation Parameter, Junction−to−Board
YJB
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
These data were generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
JEDEC51.7 guidelines. Top and Bottom layer 2 oz. copper, inner planes 1 oz. copper.
The exposed pad is connected to the PCB ground inner layer through a 3 x 3 thermal via array. Vias are 0.3 mm diameter, plated.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−board thermal resistance is simulated in an environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51−8.
7. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 8)
Rating
Symbol
Min
+ V
Max
5.5
Unit
V
Input Voltage
V
IN
V
OUT
DO
Bias Voltage
V
BIAS
V
OUT
+ 1.6
5.5
V
Junction Temperature
T
J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCV59745
Table 5. ELECTRICAL CHARACTERISTICS (At V = 1.1 V, V = V
+ 0.25 V, C
= 1 mF, C = 4.7 mF, C = 10 mF,
OUT
EN
IN
OUT(NOM)
BIAS
J
IN
I
= 50 mA, V
= 5.0 V, T = −40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C.)
OUT
BIAS
J
Symbol
Parameter
Test Conditions
Min
+V
Typ
Max
Unit
V
V
IN
Input voltage range
V
5.5
5.5
OUT
DO
V
BIAS
Bias pin voltage range
Undervoltage Lock−out
V
+ 1.4
V
OUT
UVLO
V
BIAS
Rising
Hysteresis
1.2
−
1.5
0.45
2.0
−
V
V
OUT
Accuracy
2.4 V ≤ V
1.6 V ≤ V
≤ 5.25 V, V
+
OUT
−1.0
0.3
+1.0
%
BIAS
BIAS
OUT
50 mA ≤ I
≤ 3.0 A
V
/V
Line regulation
Load regulation
V
+ 0.25 ≤ V ≤ 5.5 V
0.0006
0.005
0.01
%/V
%/mA
%/A
OUT IN
OUT(NOM)
IN
V
/I
0 mA ≤ I
≤ 50 mA
OUT OUT
OUT
50 mA ≤ I
≤ 3.0 A
OUT
V
V
V
dropout voltage (Note 9)
I
= 3.0 A,
105
195
mV
DO
IN
OUT
V
– V
= 1.6 V
BIAS
OUT(NOM)
dropout voltage (Note 9)
I
= 3.0 A, V = V
1.2
4.3
1.3
1
1.4
7
V
A
BIAS
OUT
IN
BIAS
I
CL
Current limit
V
= 80% x V
3.5
OUT
OUT(NOM)
I
Bias pin current
0 mA ≤ I
≤ 3.0 A
2
mA
mA
mA
nA
dB
BIAS
OUT
I
V
BIAS
shutdown current
V
≤ 0.4 V
15
15
250
BSHDN
EN
EN
I
V
IN
shutdown current
V
≤ 0.4 V, V = 0 V
OUT
1
INSHDN
I
Sense pin current
0 mA ≤ I
≤ 3.0 A
−250
95
75
SNS
OUT
PSRR
Power−supply rejection
(V to V
1 kHz, I
V
= 2 A,
OUT
)
= 1.25 V, V
= 1.0 V
= 1.0 V
= 1.0 V
= 1.0 V
IN
OUT
IN
OUT
3 MHz, I
V
= 2 A,
18
75
18
OUT
= 1.25 V, V
IN
OUT
Power−supply rejection
(V to V
dB
1 kHz, I
V
= 2 A,
OUT
)
OUT
= 1.25 V, V
BIAS
IN
OUT
3 MHz, I
V
= 2 A,
OUT
= 1.25 V, V
IN
OUT
Noise
Output noise voltage
10 Hz to 100 kHz, l
= 2 A
6
350
V
mVrms
ms
OUT
t
Minimum startup time
Soft−start charging current
I
= 3 A, C = open (Note 10)
STRT
OUT
SS
I
SS
V
SS
= 0.4 V
mA
OUT(NOM)
6.2
0.8 V
VEN, HI
Enable input high level
1.1
0
5.5
0.4
V
V
VEN, LO Enable input low level
VEN,HYS Enable pin hysteresis
100
mV
ms
mA
VEN,DG
Enable pin deglitch time
Enable pin current
PG trip threshold
20
0.3
88
91
3
I
V
V
V
= 5 V
1
EN
EN
V
V
decreasing
increasing
82
83
93
96
%V
%V
%V
IT−
OUT
OUT
OUT
OUT
OUT
PG trip threshold
IT+
V
PG trip hysteresis
PG output low voltage
PG leakage current
HYS
V
I
= 1 mA (sinking), V
< V
IT
0.3
1
V
PG, LO
PG
OUT
I
V
PG
= 5.25 V, V
> V
IT
0.03
600
mA
PG, LKG
OUT
R
Output Active Discharge Resistance V
(NCV59745A option only)
= 5.0 V, V = 0 V,
= 1.25 V, V
W
AD
BIAS
IN
EN
OUT
V
= 1.0 V
TSD
Thermal shutdown temperature
Shutdown, temperature increasing
Reset, temperature decreasing
+165
+140
_C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Dropout is defined as the voltage from the input to V
when V
is 3% below nominal.
OUT
OUT
10.Time from EN rising edge to 98% of V
OUT(NOM)
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NCV59745
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.25 V, V
= V
+ 1.6 V, V = 1.1 V, V
= 1.0 V,
J
IN
OUT(NOM)
BIAS
OUT(NOM)
EN
OUT(NOM)
C
= 10 mF, C
= 1 mF, and C = 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
160
140
120
100
80
120
100
80
I
= 1.5 A
OUT
+125°C
+25°C
−40°C
+125°C
+25°C
60
40
−40°C
60
40
20
0
20
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
− V
3
3.5
(V)
4
4.5
5
5.5
I
OUTPUT CURRENT (A)
OUT
V
BIAS
OUT
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 4. VIN Dropout Voltage vs. (VBIAS
–
V
OUT) and Temperature TJ
1500
1400
1300
1200
1100
260
240
220
200
180
160
140
120
100
80
I
= 3 A
OUT
−40°C
+125°C
+25°C
−40°C
60
40
20
0
+125°C
1000
900
+25°C
0
0.5
1
1.5
2
2.5
− V
3
3.5
(V)
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
I
OUTPUT CURRENT (A)
V
OUT
BIAS
OUT
Figure 5. VIN Dropout Voltage vs. (VBIAS
VOUT) and Temperature TJ
–
Figure 6. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
V
OUT
V
OUT
2 A/ms
1 A/ms
2 A/ms
1 A/ms
I
I
OUT
OUT
50 ms/div
50 ms/div
Figure 7. Load Transient Response, IOUT
=
Figure 8. Load Transient Response, IOUT =
10 mA to 3 A, COUT = 10 mF MLCC
10 mA to 3 A, COUT = 10 mF MLCC
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NCV59745
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.25 V, V
= V
+ 1.6 V, V = 1.1 V, V
= 1.0 V,
J
IN
OUT(NOM)
BIAS
OUT(NOM)
EN
OUT(NOM)
C
= 10 mF, C
= 1 mF, and C = 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
V
OUT
V
OUT
1 A/ms
1 A/ms
2 A/ms
2 A/ms
I
I
OUT
OUT
50 ms/div
50 ms/div
Figure 9. Load Transient Response, IOUT
=
Figure 10. Load Transient Response, IOUT =
10 mA to 3 A, COUT = 47 mF MLCC
10 mA to 3 A, COUT = 47 mF MLCC
V
OUT
V
OUT
2 A/ms
2 A/ms
1 A/ms
1 A/ms
I
I
OUT
OUT
50 ms/div
50 ms/div
Figure 11. Load Transient Response, IOUT
10 mA to 3 A, COUT = 330 mF Tantalum
Polymer Cap + 3x 10 mF MLCC
=
Figure 12. Load Transient Response, IOUT
10 mA to 3 A, COUT = 330 mF Tantalum
Polymer Cap + 3x 10 mF MLCC
=
V
V
ENABLE
ENABLE
V
OUT
V
OUT
I
OUT
I
OUT
500 ms/div
500 ms/div
Figure 13. Enable Transient Response, IOUT
=
Figure 14. Enable Transient Response, IOUT =
0 A, COUT = 10 mF MLCC, CSS = 0 nF
3 A, COUT = 10 mF MLCC, CSS = 0 nF
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NCV59745
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.25 V, V
= V
+ 1.6 V, V = 1.1 V, V
= 1.0 V,
J
IN
OUT(NOM)
BIAS
OUT(NOM)
EN
OUT(NOM)
C
= 10 mF, C
= 1 mF, and C
= 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
V
V
ENABLE
ENABLE
V
OUT
V
OUT
I
I
OUT
OUT
500 ms/div
500 ms/div
Figure 15. Enable Transient Response, IOUT
=
=
=
Figure 16. Enable Transient Response, IOUT
3 A, COUT = 330 mF Tantalum Polymer
Cap + 3x 10 mF MLCC, CSS = 10 nF
=
3 A, COUT = 47 mF MLCC, CSS = 0 nF
V
ENABLE
V
OUT
V
OUT
Output Active Discharge
t
R
= t = 5 ms
F
V
IN
I
OUT
500 ms/div
50 ms/div
Figure 17. Enable Transient Response, IOUT
Figure 18. VIN Line Transient Response, VIN
1.25 V to 2.25 V, IOUT = 0 mA, CIN = 0, COUT
10 mF MLCC
=
=
0 A, COUT = 47 mF MLCC, CSS = 0 nF
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
OUT
V
V
V
= 1.25 V
= 5 V
IN
BIAS
= 1.0 V
OUT
= 2 A
I
OUT
t
R
= t = 5 ms
F
Cout = 3x 10 uF
Cout = 2x 10 uF
Cout = 10 uF
V
IN
10
100
1k
10k
100k
1M
10M
50 ms/div
f, FREQUENCY [Hz]
Figure 19. VIN Line Transient Response, VIN
Figure 20. VIN Power Supply Rejection Ratio
vs. Frequency
1.25 V to 2.25 V, IOUT = 3 A, CIN = 0, COUT
=
10 mF MLCC
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NCV59745
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.25 V, V
= V
+ 1.6 V, V = 1.1 V, V
= 1.0 V,
J
IN
OUT(NOM)
BIAS
OUT(NOM)
EN
OUT(NOM)
C
= 10 mF, C
= 1 mF, and C = 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−10
−20
Cout = 3x 10 uF
Cout = 2x 10 uF
Cout = 10 uF
= 5 V
= 1.0 V
= 2 A
V
V
BIAS
OUT
OUT
−30
I
−40
−50
−60
−70
−80
−90
−100
C
= 2x 10 uF
OUT
V
I
= 5 V
BIAS
= 2 A
OUT
Vin = 1.25 V
Vin = 1.5 V
−90
−100
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
f, FREQUENCY [Hz]
f, FREQUENCY [Hz]
Figure 21. VIN Power Supply Rejection Ratio
vs. Frequency
Figure 22. VBIAS Power Supply Rejection Ratio
vs. Frequency
10
RMS Output Noise (uV)
C
(uF)
OUT
10 Hz − 100 kHz
100 Hz − 100 kHz
10
47
5.6
5.7
5.3
5.4
1
V
= 5 V
= 2 A
BIAS
I
OUT
0.1
0.01
Cout = 10 uF
Cout = 47 uF
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY [Hz]
Figure 23. Output Voltage Noise Spectral
Density
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NCV59745
APPLICATIONS INFORMATION
Programmable Soft−Start
The NCV59745 very low dropout low noise dual−rail
The Soft−Start time is programmable by external C
voltage regulator is using NMOS pass transistor for output
SS
capacitor value. If C capacitor not used, the device is
voltage regulation from V voltage. All the low current
SS
IN
starting with Minimum Start−up time specified in the
Electrical Characteristics table.
The output voltage ramping time during Soft−Start
internal controll circuitry is powered from the V
voltage.
BIAS
The use of an NMOS pass transistor offers several
advantages in applications. Unlike a PMOS topology
devices, the output capacitor has reduced impact on loop
depends on the Soft−Start charging current I and
SS
Soft−Start capacitor value C
stability. V to V
operating voltage difference can be
.
SS
IN
OUT
very low compared with standard PMOS regulators in very
low Vin applications.
The Soft–Start time can be calculated using following
equation:
The NCV59745 offers programmable smooth monotonic
start−up. The controlled voltage rising limits the inrush
current what is advantageous in applications with large
capacitive loads. The Voltage Controlled Soft Start time is
t
= C x 0.13
SS
SS
where
= Soft−Start time in miliseconds
t
C
SS
= Soft−Start capacitor value in nano Farads
SS
programmable by external C capacitor value.
SS
Soft−Start time vs C capacitor value examples can be
found in the Table 6. The maximal recommended value of
SS
The Enable (EN) input is equipped with internal
hysteresis and deglitch filter.
Open Drain type Power Good (PG) output is available for
Vout monitoring and sequencing of other devices.
NCV59745 is a Fixed Voltage linear regulator.
C
capacitor is 1 mF.
SS
Unlike other LDO devices with external Noise Reduction
/ Soft−Start capacitor, the CSS capacitor value has no
connection with NCV59745 noise performance. After
the Soft−Start phase the SS pin voltage persists in ramping
up to the VBIAS supply level.
Dropout Voltage
Because of two power supply inputs V and V
and
IN
BIAS
one V
regulator output, there are two Dropout voltages
OUT
Table 6. CAPACITOR VALUES FOR PROGRAMMING
THE SOFT−START TIME
specified.
The first, the V Dropout voltage is the voltage
IN
difference (V – V
) when V
starts to decrease by
IN
OUT
OUT
CSS
Open
4.7 nF
10 nF
47 nF
100 nF
Soft−Start Time
0.35 ms
0.6 ms
percents specified in the Electrical Characteristics table.
is high enough, specific value is published in the
V
BIAS
Electrical Characteristics table.
The second, V dropout voltage is the voltage
BIAS
1.3 ms
difference (V
– V
) when V and V
OUT
pins are
BIAS
IN
BIAS
6 ms
joined together and V
starts to decrease.
OUT
13 ms
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with effective capacitance in the range from
10 mF up to 1000 mF. The device is also stable with multiple
capacitors in parallel.
Output Noise
Internal Noise Reduction filter is implemented to reduce
the output voltage noise. Unlike LDO devices with external
noise reduction capacitor this solution is not sensitive to the
external capacitor quality.
In applications where no low input supply impedance is
available (PCB inductance in V and/or V
inputs as an
IN
BIAS
Output Active Discharge
example) the recommended C
≥ 1 mF and C ≥ 4.7 mF
BIAS
IN
The NCV59745A option devices are equipped with
Output Active Discharge feature. When EN input level is
Low and/or Thermal Shutdown is active, the Output Active
Discharge transistor is On and the output voltage node V
is pulled down to GND through a 600 W resistor. The C
of effective capacitance value. For the best performance all
capacitors should be connected to the NCV59745 respective
pins directly in the device PCB copper layer, not through
vias having not negligible impedance.
OUT
OUT
Enable Operation
output capacitor is discharged what is advantageous for
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. To get the full functionality of Soft
applications requiring next V
0 V.
Start−Up ramping from
OUT
Power Good
Start, it is recommended to turn on the V and V
supply
IN
BIAS
Power−Good (PG) is an open−drain, logic active−high
output that indicates the status of the Output Voltage V
voltages first and activate the Enable pin no sooner than V
IN
.
OUT
and V
are on their nominal levels. If the enable function
BIAS
When V
exceeds the PG trip threshold, the PG pin goes
OUT
is not to be used then the pin should be connected to V or
IN
into a high−impedance state. When V
is below this
OUT
V
BIAS
.
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9
NCV59745
threshold the pin is driven to a low−impedance state pulling
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
the PG pin to GND. An external pull−up resistor from 10 kW
to 100 kW should be connected from this pin to a supply up
to 5.5 V. The supply voltage can be higher than the input
voltage. Alternatively, the PG pin can be left floating if
output monitoring is not necessary.
Power Dissipation
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125_C.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
Table 7. ORDERING INFORMATION
Output
Current
Output
Voltage
Device
Option
Marking
Wettable Flank
Package
Shipping†
SLP
Step cut
Output Active
Discharge
NCV59745AMW100TAG
3.0 A
3.0 A
3.0 A
3.0 A
1.00 V
1.015 V
1.80 V
2.50 V
59745
V100A
QFNW20
3000 /
(Pb−Free)
Tape & Reel
SLP
Step cut
Output Active
Discharge
NCV59745AMW1015TAG
NCV59745AMW180TAG
NCV59745AMW250TAG
59745
V1015A
QFNW20
(Pb−Free)
3000 /
Tape & Reel
SLP
Step cut
Output Active
Discharge
59745
V180A
QFNW20
(Pb−Free)
3000 /
Tape & Reel
SLP
Step cut
Output Active
Discharge
59745
V250A
QFNW20
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW20 4x4, 0.5P
CASE 484AP
ISSUE A
DATE 03 JUL 2018
GENERIC
MARKING DIAGRAM*
XXXXXX= Specific Device Code
*This information is generic. Please refer to
A
LL
Y
= Assembly Location
= Wafer Lot
= Year
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXXX
XXXXXX
ALLYWG
G
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON91716G
QFNW20 4x4, 0.5P
PAGE 1 OF 1
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