NCV6357MTWCTXG [ONSEMI]
Synchronous Buck Converter, Processor Supply, I2C Programming, 5.0 A;
| 型号： | NCV6357MTWCTXG |
| 厂家： | 
ONSEMI |
| 描述： | Synchronous Buck Converter, Processor Supply, I2C Programming, 5.0 A 开关 光电二极管 |
| 文件： | 总34页 (文件大小：2467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV6357
Step Down Converter, AOT,
Configurable 5.0 A
The NCV6357 is a synchronous AOT (Adaptive On−time) buck
converter optimized to supply the different sub systems of automotive
applications post regulation system up to 5 V input. The device is able
to deliver up to 5.0 A, with programmable output voltage from 0.6 V
to 3.3 V. Operation at up to 2.4 MHz switching frequency allows the
use of small components. Synchronous rectification and automatic
PFM Pseudo−PWM (PPWM) transitions improve overall solution
efficiency. The NCV6357 is in low profile 3.0 × 4.0 mm DFN−14
package.
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MARKING
DIAGRAM
1
6357
XX
AYWW
G
WDFNW14 4x3, 0.5P
CASE 511CM
Features
• Input Voltage Range from 2.5 V to 5.5 V: Battery, 3.3 V and 5.0 V
Rail Powered Applications
XX
= A: 1.80 V /1.10 V
= B: 0.90 V / 1.00 V
• Power Capability: 3.0 A T = 105°C − 5.0 A T = 85°C
A
A
• Programmable Output Voltage: 0.6 V to 3.3 V in 12.5 mV Steps
• Up to 2.4 MHz Switching Frequency with On Chip Oscillator
• Uses 330 nH Inductor and at Least 22 mF Capacitors for Optimized
Footprint and Solution Thickness
= C: 1.80 V /1.10 V
= D: 1.25 V / 1.25 V
= F: 1.00 V / 1.10 V
= Assembly Location
= Year
A
Y
• PFM/PPWM Operation for Optimum Efficiency
• Low 60 mA Quiescent Current
WW
G
= Work Week
= Pb−Free Package
2
(Note: Microdot may be in either location)
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
Support
• Enable / VSEL Pins, Power Good / Interrupt Signaling
• Thermal Protections and Temperature Management
• Transient Load Helper: Share the Same Rail with another Rail
• 3.0 × 4.0 mm / 0.5 mm Pitch DFN 14 Package
• AEC−Q100 Qualified and PPAP Capable
PIN CONNECTIONS
(Top View)
14− Pin 0.50 mm pitch
DFN
Typical Applications
• Snap Dragon
• Automotive POL
• Instrumentation, Clusters
• Infotainment
• ADAS System (Vision, Radar)
NCV6357
Supply Input
AVIN
PVIN
SW
4.7 mF
AGND
Supply Input
Core
10 mF
Thermal
Protection
DCDC
5 A
Enable Control
Input
EN
Operating
Mode
Control
Modular
Driver
330 nH
VSEL
Voltage
Selection
2 × 22 mF
PGND
PG
Output
Monitoring
Power Good
FB
DCDC
2.4 MHz
Controller
Processor
Core
GND
SDA
GND
ORDERING INFORMATION
See detailed ordering and shipping information on page 32 of
this data sheet.
2
Sense
2
I
C
Processor I
C
Control Interface
SCL
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2019 − Rev. 3
NCV6357/D
NCV6357
PVIN
PVIN
POWER INPUT
SUPPLY INPUT
AVIN
Core
ANALOG GROUND
AGND
SW
SW
SW
5.0 A
DC−DC
Thermal
Protection
SWITCH NODE
Output Voltage
Monitoring
ENABLE CONTROL INPUT
VOLTAGE SELECTION
EN
Up to 2.4 MHz
DC−DC converter
Controller
Operating
Mode Control
VS EL
PGND
PGND
POWER GROUND
FEEDBACK
PG
SCL
SDA
Logic Control
Power Good
I2C
PROCESSOR I2C
CONTROL INTERFACE
VOUT
Sense
Figure 2. Simplified Block Diagram
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2
NCV6357
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
REFERENCE
4
AVIN
Analog Input
Analog Supply. This pin is the device analog and digital supply. Could be connected
directly to the VIN plane with a dedicated 4.7 mF ceramic capacitor. Must be equal to
PVIN
15
AGND
Analog
Ground
Analog Ground. Analog and digital modules ground. Must be connected to the system
ground
CONTROL AND SERIAL INTERFACE
14
EN
Digital Input
Enable Control. Active high will enable the part. There is an internal pull down resistor
on this pin
13
VSEL
Digital Input
Output voltage / Mode Selection. The level determines which of two programmable
configurations to utilize (operating mode / output voltage). There is an internal pull down
resistor on this pin; could be left open if not used
3
1
PG
SCL
SDA
Digital
Output
Power Good Indicator open drain output. Must be connected to the ground plane if
not used
2
Digital Input
I C interface Clock line. There is an internal pull down resistor on this pin; could be left
open if not used
2
12
Digital
Input/Output
I C interface Bi−directional Data line. There is an internal pull down resistor on this pin;
could be left open if not used
DC TO DC CONVERTER
8, 9
PVIN
Power Input
Switch Supply. These pins must be decoupled to ground by at least a 10 mF ceramic
capacitor. It should be placed as close as possible to these pins. All pins must be used
with short heavy connections. Must be equal to AVIN
5, 6, 7
SW
Power
Output
Switch Node. These pins supply drive power to the inductor. Typical application uses
0.33 mH inductor; refer to application section for more information.
All pins must be used with short heavy connections
10, 11
PGND
VOUT
Power
Switch Ground. This pin is the power ground and carries the high switching current.
High quality ground must be provided to prevent noise spikes. To avoid high−density
current flow in a limited PCB track, a local ground plane that connects all PGND pins
together is recommended. Analog and power grounds should only be connected
together in one location with a trace
Ground
2
Analog Input
Feedback Voltage input. Must be connected to the output capacitor positive terminal
with a trace, not to a plane. This is the positive input to the error amplifier
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3
NCV6357
MAXIMUM RATINGS
Rating
Analog and power pins (Note 1):
AVIN, PVIN, SW, PG, VOUT, DC non switching
PVIN−PGND pins, transient 3 ns – 2.4 MHz
Symbol
Value
Unit
V
− 0.3 to + 6.0
−0.3 to +7.5
V
A
2
2
I C pins: SDA, SCL
V
V
− 0.3 to + 6.0
V
I C
Digital pins : EN, VSEL
Input Voltage
−0.3 to V +0.3 ≤ 6.0
V
mA
DG
DG
A
Input Current
I
10
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
ESD HBM
ESD CDM
2500
2000
V
V
Latch Up Current: (Note 3)
Digital Pins
I
LU
100
100
mA
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
T
− 65 to + 150
−40 to +150
Level 1
°C
°C
STG
T
JMAX
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.5 kV per JEDEC standard: JESD22*A114.
Charged Device Model (CDM) 2.0 kV per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
OPERATING CONDITIONS
Symbol
Parameter
Conditions
PV
Min
2.5
− 40
−
Typ
Max
5.5
+125
−
Unit
V
AV PV
Power Supply
AV
IN =
IN,
IN
IN
T
J
Junction Temperature Range (Note 6)
Thermal Resistance Junction to Ambient (Note 7)
Power Dissipation Rating (Note 8)
25
30
°C
R
DFN−14 on Demo−board
≤ 105°C,
°C/W
mW
q
JA
P
D
T
A
−
666
−
R
= 30°C/W
q
JA
T
R
≤ 85°C
−
−
1333
2000
−
−
mW
mW
A
= 30°C/W
q
JA
T = 65°C
A
R
= 30°C/W
q
JA
L
Inductor for DC to DC converter (Note 5)
0.15
15
0.33
−
0.47
200
−
mH
mF
mF
Co
Output Capacitor for DC to DC Converter (Note 5)
Input Capacitor for DC to DC Converter (Note 5)
Cin
Per 1.0 A of I
6.0
10.0
OUT
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The R
is dependent of the PCB heat dissipation. Board used to drive this data was a NCV6357EVB board. It is a multilayer board with
q
JA
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
8. The maximum power dissipation (PD) is dependent on input voltage, maximum output current, pcb stack up and layout, and external
components selected.
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4
NCV6357
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for TJ = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Typical values are referenced to TA = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN – PVINx
I
Operating quiescent current PPWM
Operating quiescent current PFM
Product sleep mode current
DCDC active in Forced
PPWM no load
−
−
−
22
60
5
25
90
10
mA
mA
mA
Q−PPWM
I
DCDC active in Auto mode
no load – minimal switching
Q PFM
SLEEP
I
Product in sleep mode
V
IN
= 5.5 V, T up to 85°C
J
I
Product in off mode
EN, VSEL and Sleep_Mode
−
0.8
3
mA
OFF
2
low, No I C pull up
V
IN
= 5.5 V, T up to 85°C
J
DC TO DC CONVERTER
PV
Input Voltage Range
Load Current Range
2.5
−
5.5
V
A
IN
I
(Note 11, 12)
OUT
Ipeak[1..0] = 00
Ipeak[1..0] = 01
Ipeak[1..0] = 10
Ipeak[1..0] = 11
0
0
0
0
−
−
−
−
3.5
4.0
4.5
5.0
DV
Output Voltage DC Error
Forced PPWM mode, No
load
−1.5
−
1.5
%
OUT
Forced PPWM mode,
−2
−
2
I
up to I
(Note 11)
OUT
OUTMAX
Auto mode,
up to I
−3
−
2
I
(Note 11)
OUT
OUTMAX
F
Switching Frequency
2.16
2.4
39
2.64
60
MHz
SW
R
P−Channel MOSFET On Resistance
From PVIN to SW
= 5.0 V
−
mΩ
ONHS
V
IN
R
N−Channel MOSFET On Resistance
From SW to PGND
= 5.0 V
−
32
45
mΩ
ONLS
V
IN
I
PK
Peak Inductor Current
Open loop − Ipeak[1..0] = 00
Open loop − Ipeak[1..0] = 01
Open loop − Ipeak[1..0] = 10
Open loop − Ipeak[1..0] = 11
4.6
5.2
5.6
6.2
5.2
5.8
6.2
6.8
5.8
6.4
6.8
7.4
A
I
Negative Current limit
Load Regulation
−
−
1.4
5
−
−
A
PKN
DC
I
from 0 A to I
OUTMAX
mV
LOAD
OUT
Forced PPWM mode
DC
Line Regulation
2.5 V ≤ V ≤ 5.5 V
Forced PPWM mode
−
−
−
6
−
−
−
mV
mV
mV
LINE
IN
AC
Transient Load Response
Transient Line Response
t = t = 100 ns
20
20
LOAD
r
f
Load step 1.5 A
AC
t = t = 10 ms
LINE
r
f
Line step 3.0 V / 3.6 V
D
Maximum Duty Cycle
Turn on time
−
−
100
100
−
%
t
Time from EN transitions
from Low to High to 90% of
Output Voltage
130
ms
START
(DVS[1..0] = 00b),
V
OUT
= 1.10 V
R
DCDC Active Output Discharge
V
OUT
= 1.10 V
−
12
25
Ω
DISDCDC
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5
NCV6357
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for TJ = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Typical values are referenced to TA = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EN, VSEL
V
High input voltage
1.05
−
−
−
−
−
V
V
IH
V
Low input voltage
0.4
4.5
IL
T
FTR
Digital input X Filter
EN, VSEL rising and falling
DBN_Time = 01 (Note 11)
0.5
ms
I
Digital input X Pull−Down
For EN and VSEL pins
−
0.05
1.00
mA
PD
(input bias current)
PG (OPTIONAL)
V
Power Good Threshold
Falling edge as a percentage
of nominal output voltage
86
0
90
3
94
5
%
PGL
V
Power Good Hysteresis
%
PGHYS
T
RT
Power Good Reaction Time for DCDC
Falling (Note 11)
Rising (Note 11)
−
3.5
1.0
−
−
14
ms
V
Power Good low output voltage
Power Good leakage current
I
= 5 mA
−
−
−
−
0.2
V
PGL
PG
PG
3.3V at PG pin when power
good valid
100
nA
LK
V
PGH
Power Good high output voltage
Open drain
−
−
5.5
V
2
I C
2
V
High level at SCL/SCA line
SCL, SDA low input voltage
SCL high input voltage
SDA high input voltage
SDA low output voltage
1.7
−
−
−
−
−
−
−
4.5
0.4
−
V
V
V
I CINT
2
V
SCL, SDA pin
I CIL
2
V
SCL pin (Note 10, 11)
SDA pin (Note 10, 11)
1.6
1.2
−
I CIH
−
2
V
I
= 3 mA
0.4
3.4
V
I COL
SINK
2
F
SCL
I C clock frequency
(Note 11)
−
MHz
TOTAL DEVICE
V
Under Voltage Lockout
V
V
falling
rising
−
60
−
−
−
2.5
200
−
V
mV
°C
°C
°C
°C
°C
°C
UVLO
IN
V
Under Voltage Lockout Hysteresis
Thermal Shut Down Protection
Warning Rising Edge
UVLOH
IN
T
150
135
105
30
15
6
SD
WARNING
T
−
−
2
T
PWTH
Pre–Warning Threshold
I C default value
−
−
T
Thermal Shut Down Hysteresis
Thermal warning Hysteresis
Thermal pre−warning Hysteresis
−
−
SDH
WARNINGH
T
−
−
T
−
−
PWTH H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to
the V voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
12.Junction temperature must be maintained below 125°C. Output load current capability depends on the application thermal capability.
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NCV6357
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.3 V, T = +25°C
IN
IN
J
DCDC = 1.80 V, I
= 6.8 A (Unless otherwise noted). L = 0.33 mH DFE252012F – C = 2 x 22 mF 0603, C = 4.7 mF 0603.
OUT IN
PEAK
Figure 4. Efficiency vs ILOAD and VIN
VOUT = 3.3 V, SPM5030 Inductor
Figure 5. Efficiency vs ILOAD and Temperature
OUT = 3.3 V, VIN = 5.0 V, SPM5030 Inductor
V
Figure 6. Efficiency vs ILOAD and VIN
VOUT = 1.8 V, SPM5030 Inductor
Figure 7. Efficiency vs ILOAD and Temperature
OUT = 1.8 V, SPM5030 Inductor
V
Figure 8. Efficiency vs ILOAD and VIN
VOUT = 0.60 V, SPM5030 Inductor
Figure 9. Efficiency vs ILOAD and Temperature
OUT = 0.60 V, SPM5030 Inductor
V
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NCV6357
Figure 10. Efficiency vs ILOAD and VIN
VOUT = 1.80 V
Figure 13. Efficiency vs ILOAD and Temperature
OUT = 1.80 V
V
Figure 11. Efficiency vs ILOAD and VIN
VOUT = 0.60 V
Figure 12. Efficiency vs ILOAD and VIN
VOUT = 1.10 V
Figure 15. Efficiency vs ILOAD and VIN
VOUT = 1.25 V
Figure 14. Efficiency vs ILOAD and VIN
VOUT = 3.30 V
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NCV6357
Figure 17. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.80 V
Figure 18. VOUT Accuracy vs VIN and Temperature
VOUT = 1.80 V
Figure 20. VOUT Accuracy vs ILOAD and VIN
VOUT = 0.600 V
Figure 21. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.10 V
Figure 19. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.25 V
Figure 16. VOUT Accuracy vs ILOAD and VIN
VOUT = 3.3 V
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NCV6357
Figure 22. HSS RON vs VIN and Temperature
Figure 27. LSS RON vs VIN and Temperature
Figure 23. IOFF vs VIN and Temperature
Figure 24. ISLEEP vs VIN and Temperature
Figure 25. IQ PFM vs VIN and Temperature
OUT = 1.25 V
Figure 26. IQ PPWM vs VIN and Temperature
V
VOUT = 1.25 V
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NCV6357
Figure 28. Switchover Point VOUT = 1.15 V
Figure 29. Switchover Point VOUT = 1.4 V
Figure 30. Switching Frequency vs ILOAD and VIN
VOUT = 1.10 V
Figure 31. Switching Frequency vs ILOAD and
Temperature VOUT = 1.10 V
Figure 32. Ripple
Figure 33. Normal Power Up, VOUT = 1.15 V
DVS[1..0] = 00
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NCV6357
Figure 34. Transient load 0.05 to 1.5 A
Transient line 3.0 – 3.6 V Auto mode
Figure 35. Transient load 0.05 to 1.5 A
Transient line 3.6 – 3.0 V Auto mode
Figure 36. Transient load 0.05 to 1.5 A
Transient line 3.0 – 3.6 V Forced PPW
Figure 37. Transient load 0.05 to 1.5 A
Transient line 3.6 – 3.0 V Forced PPWM
Figure 38. Transient load 1.0 to 2.5 A
Figure 39. Transient load 2.0 to 3.5 A
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NCV6357
DETAILED OPERATING DESCRIPTION
Output Stage
Detailed Descriptions
NCV6357 is a 3.5 A to 5.0 A output current capable DC
to DC converter with both high side and low side
(synchronous) switches integrated.
The NCV6357 is voltage mode stand−alone DC to DC
converter optimized to supply different sub systems of
automotive applications post regulation system up to 5 V
2
input. It can deliver up to 5 A at an I C selectable voltage
Inductor Peak Current Limitation / Short Protection
During normal operation, peak current limitation
monitors and limits the inductor current by checking the
current in the P−MOSFET switch. When this current
exceeds the Ipeak threshold, the P−MOSFET is immediately
opened.
To protect again excessive load or short circuit, the
number of consecutive Ipeak is counted. When the counter
reaches 16, the DCDC is powered down during about 2 ms
and the ISHORT interrupt is flagged. It will re−start
following the REARM bit in the LIMCONF register:
• If REARM = 0, then NCV6357 does not re−start
automatically, an EN pin toggle is required
• If REARM = 1, NCV6357 re−starts automatically after
the 2 ms with register values set prior the fault
condition
ranging from 0.6 V to 3.3 V. The switching frequency up to
2.4 MHz allows the use of small output filter components.
Power Good indicator and Interrupt management are
available. Operating modes, configuration, and output
power can be easily selected either by using digital I/O pins
2
or by programming a set of registers using an I C compatible
interface capable of operation up to 3.4 MHz.
2
Default I C settings are factory programmable.
DC to DC Converter Operation
The converter integrates both high side and low side
(synchronous) switches. Neither external transistors nor
diodes are required for NCV6357 operation. Feedback and
compensation network are also fully integrated.
It uses the AOT (Adaptive On−Time) control scheme and
can operate in two different modes: PFM and PPWM
(Pseudo−PWM). The transition between modes can occur
automatically or the switcher can be placed in forced PPWM
This current limitation is particularly useful to protect the
inductor. The peak current can be set by writing
IPEAK[1..0] bits in the LIMCONF register.
2
mode by I C programming (PPWMVSEL0 / PPWMVSEL1
bits of COMMAND register).
PPWM (Pseudo Pulse Width Modulation) Operating
Mode
Table 1. IPEAK VALUES
In medium and high load conditions, NCV6357 operates
in PPWM mode to regulate the desired output voltage. In
this mode, the inductor current is in CCM (Continuous
Conduction Mode) and the AOT guaranties a pseudo−fixed
frequency with 10% accuracy. The internal N−MOSFET
switch operates as synchronous rectifier and is driven
complementary to the P−MOSFET switch.
IPEAK[1..0]
Inductor Peak Current (A)
5.2 – for 3.5 output current
5.8 – for 4.0 output current
6.2 – for 4.5 output current
6.8 – for 5.0 output current
00
01
10
11
To protect the low side switch, the negative current
protection limits potential excessive current from output.
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low
loads, the NCV6357 operates in PFM mode as the inductor
current drops into DCM (Discontinuous Conduction Mode).
The upper FET on−time is kept constant and the switching
frequency becomes proportional to the loading current. As
it does in PPWM mode, the internal N−MOSFET operates
as a synchronous rectifier after each P−MOSFET on−pulse
until there is no longer current in the coil.
Output Voltage
The output voltage is set internally by an integrated
resistor bridge and no extra components are needed to set the
output voltage. Writing in the VoutVSEL0[7..0] bits of the
PROGVSEL0 register or VoutVSEL1[7..0] bits of the
PROGVSEL1 register will change the output voltage. The
output voltage level can be programmed by 12.5 mV steps
between 0.6 V to 3.3 V. The VSEL pin and VSELGT bit will
determine which register between PROGVSEL0 and
PROGVSEL1 will set the output voltage.
• If VSELGT = 1 AND VSEL = 0 ³ Output voltage is
set by VoutVSEL0[7..0] bits (PROGVSEL0 register)
• Else ³ Output voltage is set by VoutVSEL1[7..0] bits
(PROGVSEL1 register)
When the load increases and the current in the inductor
become continuous again, the controller automatically turns
back to PPWM mode.
Forced PPWM
The NCV6357 can be programmed to only use PPWM
and the transition to PFM can be disabled if so desired,
thanks to the PPWMVSEL0 or PPWMVSEL1 I2C bits
(COMMAND register).
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NCV6357
Under Voltage Lock Out (UVLO)
discharge path is enabled and is activated during the first
NCV6357 core does not operate for voltages below the
Under Voltage Lock Out (UVLO) level. Below the UVLO
threshold, all internal circuitry (both analog and digital) is
held in reset. NCV6357 operation is guaranteed down to
UVLO as the battery voltage is dropping off. To avoid erratic
on / off behavior, a maximum 200 mV hysteresis is
implemented. Restart is guaranteed at 2.7 V when the VBAT
voltage is recovering or rising.
100 ms after battery insertion.
Enabling
The EN pin controls NCV6357 start up. EN pin Low to
High transition starts the power up sequencer. If EN is low,
the DC to DC converter is turned off and device enters:
2
• Sleep Mode if Sleep_Mode I C bit is high or VSEL is
2
high or I C pull up present
2
• Off Mode if Sleep_Mode I C bit and VSEL are low and
Thermal Management
2
no I C pull up
Thermal Shut Down (TSD)
When EN pin is set to a high level, the DC to DC converter
can be enabled / disabled by writing the ENVSEL0 or
ENVSEL1 bit of the COMMAND registers:
Battery monitoring for UVLO and Overvoltage
Protectione thermal capability of the NCV6357 can be
exceeded due to the step down converter output stage power
level.. A thermal protection circuitry with associated
interrupt is therefore implemented to prevent the IC from
damage. This protection circuitry is only activated when the
core is in active mode (output voltage is turned on). During
thermal shut down, output voltage is turned off.
During thermal shut down, the output voltage is turned
off.
When NCV6357 returns from thermal shutdown, it can
re−start in 2 different configurations depending on the
REARM bit in the LIMCONF register (refer to the register
description section):
• If REARM = 0 then NCV6357 does not re−start after
TSD. To restart, an EN pin toggle is required
• If REARM = 1, NCV6357 re−starts with register values
set prior to thermal shutdown
2
• Enx I C bit is high, the DC to DC converter is
activated.
• Enx I2C is low, the DC to DC converter is turned off
and the device enters in Sleep Mode.
A built in pull down resistor disables the device when this
pin is left unconnected or not driven. EN pin activity does
not generate any digital reset.
Power Up Sequence (PUS)
In order to power up the circuit, the input voltage AVIN
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up which is the “Wake Up
Time” (including “Bias Time”).
This delay is internal and cannot be bypassed. EN pin
transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
The thermal shut down threshold is set at 150°C (typical)
and a 30°C hysteresis is implemented in order to avoid
erratic on / off behavior. After a typical 150°C thermal shut
down, NCV6357 will resume to normal operation when the
die temperature cools to 120°C.
AVIN
UVLO
POR
EN
Thermal Warnings
In addition to the TSD, the die temperature monitoring
DELAY[2..0]
VOUT
32 ms
∼ 80 ms
circuitry includes
a thermal warning and thermal
pre−warning sensor and interrupts. These sensors can
inform the processor that NCV6357 is close to its thermal
shutdown and preventive measures to cool down die
temperature can be taken by software.
The Warning threshold is set by hardware to 135°C
typical. The Pre−Warning threshold is set by default to
105°C but it can be changed by setting the TPWTH[1..0] bits
in the LIMCONF register.
Wake up
Time
Init DVS ramp
Time Time
Figure 40. Initial Power Up Sequence
In addition a user programmable delay will also take place
between the Wake Up Time and the Init time: The
DELAY[2..0] bits of the TIME register will set this user
programmable delay with a 2 ms resolution. With default
delay of 0 ms, the NCV6357 IPUS takes roughly 100 ms, and
the DC to DC converter output voltage will be ready within
150 ms.
Active Output Discharge
To make sure that no residual voltage remains in the power
supply rail when disabled, an active discharge path can
ground the NCV6357 output voltage. For maximum
flexibility, this feature can be easily disabled or enabled with
the DISCHG bit in the PGOOD register. By default the
The power up output voltage is defined by the VSEL state.
2
NOTE: During the Wake Up time, the I C interface is
2
not active. Any I C request to the IC during this
time period will result in a NACK reply.
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14
NCV6357
DC to DC Converter Shut Down
Normal, Quick and Fast Power Up Sequence
The previous description applies only when the EN
transitions during the internal core circuitry power up (Wake
up and calibration time). Otherwise 3 different cases are
possible:
When shutting down the device, no shut down sequence
is required. The output voltage is disabled and, depending on
the DISCHG bit state of the PGOOD register, the output may
be discharged.
DC to DC converter shutdown is initiated by either
grounding the EN pin (Hardware Shutdown) or, depending
on the VSEL internal signal level, by clearing the ENVSEL0
or ENVSEL1 bits (Software shutdown) in the PROGVSEL0
or PROGVSEL1 registers.
• Enabling the part by setting the EN pin from Off Mode
will result in “Normal power up sequence” (NPUS,
with DELAY;[2..0])
• Enabling the part by setting the EN pin from Sleep
Mode will result in “Quick power up sequence”
(QPUS, with DELAY;[2..0])
In hardware shutdown (EN = 0), the internal core is still
2
active and I C accessible.
• Enabling the DC to DC converter, whereas EN is
already high, either by setting the ENVSEL0 or
ENVSEL1 bits or by VSEL pin transition will results in
“Fast power up sequence” (FPUS, without
DELAY[2..0])
The internal core of the NCV6357 shuts down when AVIN
falls below UVLO.
Dynamic Voltage Scaling (DVS)
The NCV6357 supports dynamic voltage scaling (DVS)
2
allowing the output voltage to be reprogrammed via I C
commands and provides the different voltages required by
the processor. The change between set points is managed in
a smooth fashion without disturbing the operation of the
processor.
When programming a higher voltage, the output raises
with controlled dV/dt defined by DVS[1..0] bits in the TIME
register. When programming a lower voltage the output
voltage will decrease accordingly. The DVS step is fixed and
the speed is programmable.
AVIN
UVLO
POR
EN
O
F
F
DELAY[2..0]
M
O
D
E
32 ms
T
FTR Bias
Init DVS ramp
The DVS sequence is automatically initiated by changing
the output voltage settings. There are two ways to change
these settings:
Time
Time
Time
Figure 41. Normal Power Up Sequence
AVIN
• Directly change the active setting register value
(VoutVSEL0[7..0] of the PROGVSEL0 register or
VoutVSEL1[7..0] of the PROGVSEL1 register) via an
UVLO
POR
S
L
E
E
P
EN
2
I C command
• Change the VSEL internal signal level by toggling the
DELAY[2..0]
M
O
D
E
VSEL pin
32 ms
2
The second method eliminates the I C latency and is
T
FTR Bias
Init DVS ramp
Time Time
therefore faster.
Time
The DVS transition mode can be changed with the
DVSMODE bit in the COMMAND register:
Figure 42. Quick Power Up Sequence
AVIN
• In forced PPWM mode when accurate output voltage
control is needed. Rise and fall time are controlled with
the DVS[1..0] bits
UVLO
POR
S
L
E
E
P
VSEL
V2
Internal
Output
Reference
Voltage
VOUT
M
O
D
E
32 ms
DV
Dt
DVS ramp
Time
T
Init
Time
V1
Figure 43. Fast Power Up Sequence
Figure 44. DVS in Forced PPWM Mode Diagram
Output
Voltage
V2
In addition the delay set in DELAY[2..0] bits in TIME
register will apply only for the EN pins turn ON sequence
(NPUS and QPUS).
Internal
Reference
DV
Dt
The power up output voltage is defined by VSEL state.
V1
Figure 45. DVS in Auto Mode Diagram
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15
NCV6357
Digital IO Settings
Power Good Pin
To indicate the output voltage level is established, a power
good signal is available on PG pin. The power good signal
is low when the DC to DC converter is off. Once the output
voltage reaches 93% of the expected output level, the power
good logic signal becomes high and the open drain output
becomes high impedance.
VSEL pin
By changing VSEL pin levels, the user has a latency free
way to change NCV6357 configuration: operating mode
(Auto or PWM forced), the output voltage as well as enable.
Table 2. VSEL PIN PARAMETERS
During operation, when the output drops below 90% of
the programmed level, the power good logic signal goes low,
indicating a power failure. When the voltage rises again to
above 93%, the power good signal goes high again.
During a DVS sequence, the Power Good signal is set low
during the transition and goes back to high once the
transition is completed.
The Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in the PGOOD
register.
Parameter VSEL
Pin Can Set
REGISTER
VSEL = LOW
REGISTER
VSEL = HIGH
ENABLE
ENVSEL0
COMMAND[3]
ENVSEL1
COMMAND[2]
VOUT
VoutVSEL0[7..0]
VoutVSEL1[7..0]
OPERATING
MODE (Auto /
PPWM Forced)
PWMVSEL0
COMMAND[7]
PWMVSEL1
COMMAND[6]
The Power Good operation during DVS can be activated
with PGDVS bit of the PGOOD register.
VSEL pin action can be masked by writing 0 to the
VSELGT bit in the COMMAND register. In that case I C bit
2
corresponding to VSEL high will be taken into account.
DCDC_EN
EN pin
The EN pin can be gated by writing the ENVSEL0 or
ENVSEL1 bits of the COMMAND register, depending on
which register is activated by the VSEL internal signal.
93 %
90 %
32 ms
DCDC
3.5−
14 ms
3.5−
14 ms
1.0 ms
Interrupt (Optional)
PG
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when
a system status change is detected (dual edge monitoring).
Figure 46. Power Good signal when PGDCDC = 1
Internal
DVS ramp
Table 3. INTERUPT SOURCES
Interrupt Name
TSD
Description
Thermal Shut Down
Thermal Warning
V1
DVS
up
DVS
TWARN
TPREW
UVLO
down
Thermal Pre−Warning
Under Voltage Lock Out
PG
IDCDC
DC to DC converter Current
Over / below limit
Figure 47. Power Good during DVS Transition
PGDVS = 1
ISHORT
PG
DC to DC converter
Short−Circuit Protection
Power Good
Power Good Delay
In order to generate a Reset signal, a delay can be
programmed between when the output voltage gets 93% of
its final value and when the Power Good pin is released to
a high level.
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I C read only registers), indicating the
2
interrupt source. INT_ACK register is automatically reset
2
by an I C read. The INT_SEN register (read only register)
Vout
contains real time indicators of interrupt sources.
When the host reads the INT_ACK registers the interrupt
register INT_ACK is cleared.
PG
No
TOR[2:0]
Delay
SEN_TWARN
ACK_TWARN
Delay Programmed in
TOR [2:0]
2
read
read
read
read
I C access on INT_ACK
Figure 48. Power Good Operation
Figure 49. TWARN Interrupt Operation Example
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16
NCV6357
Configurations
Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.
Below is the default configurations pre−defined:
Table 4. NCV6357 CONFIGURATION
5.0 A
5.0 A
5.0 A
5.0 A
5.0 A
NCV6357A
NCV6357B
NCV6357C
NCV6357D
NCV6357F
Configuration
2
Default I C address
ADD1 – 14h:
0010100R/W
ADD2 – 18h:
0011000R/W
ADD1 – 14h:
0010100R/W
ADD2 – 18h:
0011000R/W
ADD4 – 60h:
1100100R/W
PID product identification
RID revision identification
FID feature identification
21h
Metal
00h
21h
Metal
01h
21h
Metal
00h
21h
Metal
08h
21h
Metal
04h
Default VOUT – VSEL = 1
Default VOUT – VSEL = 0
Default MODE – VSEL = 1
Default MODE – VSEL = 0
Default IPEAK
1.10 V
1.80 V
1.00 V
0.90 V
1.10 V
1.80 V
1.25 V
1.25 V
1.1 V
1.0 V
Auto mode
Forced PPWM
6.8 A
Forced PPWM
Forced PPWM
6.8 A
Auto mode
Forced PPWM
6.8 A
Auto mode
Forced PPWM
6.8 A
Forced PPWM
Forced PPWM
6.8 A
Discharge path
Activated
Activated
Not Activated
6.25 mV/2.666 ms
Activated
Activated
DVS
6.25 mV/2.666 ms
6.25 mV/0.666 ms
6.25 mV/0.666 ms
6.25 mV/0.666 ms
OPN
NCV6357MTWAT
XG
NCV6357MTWB
TXG
NCV6357MTWC
TXG
NCV6357MTWD
TXG
NCV6357MTWF
TXG
Marking
6357A
6357B
6357C
6357D
6357F
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17
NCV6357
I²C Compatible Interface
2
NCV6357 can support a subset of the I C protocol as detailed below.
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
READ OUT FROM PART
START
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA n
1 à READ
/ACK
ACK
ACK
ACK
STOP
WRITE INSIDE PART
IC ADDRESS
0
DATA 1
DATA n
If PART does not Acknolege, the /NACK will be followed by a STOP or Sr (repeated start).
0 à WRITE
Figure 50. General Protocol Description
The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a Write operation).
The following data will be:
• During a Write operation, the register address (@REG) is written in followed by the data. The writing process is
auto−incremental, so the first data will be written in @REG, the contents of @REG are incremented and the next data
byte is placed in the location pointed to by @REG + 1 …, etc
• During a Read operation, the NCV6357 will output the data from the last register that has been accessed by the last
write operation. Like the writing process, the reading process is auto−incremental.
Read Sequence
The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then
start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to:
FROM MCU to NCPxxxx
SETS INTERNAL
REGISTER POINTER
START
ACK
ACK
STOP
IC ADDRESS
0
REGISTER ADDRESS
0 à WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA n
REGISTER ADDRESS
VALUE
REGISTER ADDRESS + (n –1)
VALUE
n REGISTERS READ
1 à READ
Figure 51. Read Sequence
The first WRITE sequence will set the internal pointer to the register that is selected. Then the read transaction will start at
the address the write transaction has initiated.
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18
NCV6357
Write Sequence
Write operation will be achieved by only one transaction. After chip address, the REG address has to be set, then following
data will be the data we want to write in REG, REG + 1, REG + 2, …, REG + n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG + (n – 1) VALUE
0 à WRITE
Figure 52. Write Sequence
Write then Read Sequence
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG + (n –1) VALUE
n REGISTERS WRITE
0 à WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA k
REGISTER REG + (n –1)
VALUE
REGISTER ADDRESS + (n –1) +
(k – 1) VALUE
k REGISTERS READ
1 à READ
Figure 53. Write Followed by Read Transaction
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19
NCV6357
I2C Address
2
The NCV6357 has 8 available I C addresses selectable by factory settings (ADD0 to ADD7). Different address settings can
be generated upon request to ON Semiconductor. See Table 5 (NCV6357 Configuration) for the default I C address.
2
Table 5. I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0x20
R 0x21
0
0
1
0
0
0
0
R/W
Add
0x10
0
−
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
W 0x28
R 0x29
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Add
0x14
1
−
W 0x30
R 0x31
R/W
Add
0x18
1
−
W 0x38
R 0x39
R/W
Add
0x1C
0
−
W 0xC0
R 0xC1
R/W
Add
0x60
0
−
W 0xC8
R 0xC9
R/W
Add
0x64
1
−
W 0xD0
R 0xD1
R/W
Add
0x68
1
−
W 0xD8
R 0xD9
R/W
Add
0x6C
−
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20
NCV6357
Register Map
The tables below describe the I C registers.
2
Registers / Bits Operations:
R
RC
Read only register
Read then Clear
RW
Read and Write register
Reserved
Address is reserved and register / bit is not physically designed
Table 6. I2C REGISTERS MAP CONFIGURATION (NCV6357A)
Register
Name
Add.
Type
RC
R
Def.
00h
01h
−
Function
00h
INT_ACK
Interrupt register
01h
INT_SEN
Sense register (real time status)
Reserved for future use
02h
−
−
03h
PID
R
20h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 11h
12h
−
PGOOD
TIME
−
Reserved for future use
RW
RW
RW
−
11h
19h
8Dh
−
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
13h
14h
COMMAND
−
15h
16h
LIMCONF
PROGVSEL1
PROGVSEL0
−
RW
RW
RW
−
E3h
28
Reset and limit configuration register (trim)
Output voltage settings for VSEL pin = High (trim)
Output voltage settings for VSEL pin = Low (trim)
Reserved for future use
17h
18h
60
19h to 26h
27h to FFh
−
−
−
−
Reserved. Test Registers
Table 7. I2C REGISTERS MAP CONFIGURATION (NCV6357B)
Register
Name
Add.
Type
RC
R
Def.
00h
01h
−
Function
00h
INT_ACK
Interrupt register
01h
INT_SEN
Sense register (real time status)
Reserved for future use
02h
−
−
03h
PID
R
20h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 11h
12h
−
PGOOD
TIME
−
Reserved for future use
RW
RW
RW
−
11h
09h
CD
−
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
13h
14h
COMMAND
−
15h
16h
LIMCONF
PROGVSEL1
PROGVSEL0
−
RW
RW
RW
−
E3h
20
Reset and limit configuration register (trim)
Output voltage settings for VSEL pin = High (trim)
Output voltage settings for VSEL pin = Low (trim)
Reserved for future use
17h
18h
18
19h to 26h
27h to FFh
−
−
−
−
Reserved. Test Registers
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21
NCV6357
Table 8. I2C REGISTERS MAP CONFIGURATION (NCV6357C)
Register
Name
Add.
Type
RC
R
Def.
00h
01h
−
Function
00h
INT_ACK
Interrupt register
01h
INT_SEN
Sense register (real time status)
Reserved for future use
02h
−
−
03h
PID
R
20h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 11h
12h
−
PGOOD
TIME
−
Reserved for future use
RW
RW
RW
−
01h
19h
8Dh
−
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
13h
14h
COMMAND
−
15h
16h
LIMCONF
PROGVSEL1
PROGVSEL0
−
RW
RW
RW
−
E2h
28
Reset and limit configuration register (trim)
Output voltage settings for VSEL pin = High (trim)
Output voltage settings for VSEL pin = Low (trim)
Reserved for future use
17h
18h
60
19h to 26h
27h to FFh
−
−
−
−
Reserved. Test Registers
Table 9. I2C REGISTERS MAP CONFIGURATION (NCV6357D)
Register
Name
Add.
Type
RC
R
Def.
00h
01h
−
Function
00h
INT_ACK
Interrupt register
01h
INT_SEN
Sense register (real time status)
Reserved for future use
02h
−
−
03h
PID
R
20h
Metal
08h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 11h
12h
−
PGOOD
TIME
−
Reserved for future use
RW
RW
RW
−
11h
09h
8Fh
−
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
13h
14h
COMMAND
−
15h
16h
LIMCONF
PROGVSEL1
PROGVSEL0
−
RW
RW
RW
−
E3h
34
Reset and limit configuration register (trim)
Output voltage settings for VSEL pin = High (trim)
Output voltage settings for VSEL pin = Low (trim)
Reserved for future use
17h
18h
34
19h to 26h
27h to FFh
−
−
−
−
Reserved. Test Registers
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22
NCV6357
Table 10. I2C REGISTERS MAP CONFIGURATION (NCV6357F)
Register
Name
Add.
Type
RC
R
Def.
00h
01h
−
Function
00h
INT_ACK
Interrupt register
01h
INT_SEN
Sense register (real time status)
Reserved for future use
02h
−
−
03h
PID
R
20h
Metal
04h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 11h
12h
−
PGOOD
TIME
−
Reserved for future use
RW
RW
RW
−
11h
09h
8Fh
−
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
13h
14h
COMMAND
−
15h
16h
LIMCONF
PROGVSEL1
PROGVSEL0
−
RW
RW
RW
−
E3h
28
Reset and limit configuration register (trim)
Output voltage settings for VSEL pin = High (trim)
Output voltage settings for VSEL pin = Low (trim)
Reserved for future use
17h
18h
20
19h to 26h
27h to FFh
−
−
−
−
Reserved. Test Registers
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23
NCV6357
Registers Description
Table 11. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 00h
Default: 00000000b (00h)
Type: RC
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_TWARN
ACK_TPREW
Spare = 0
ACK_ISHORT
Bit Description
ACK_UVLO
ACK_IDCDC
ACK_PG
Bit
ACK_PG
ACK_IDCDC
ACK_UVLO
ACK_ISHORT
ACK_TPREW
ACK_TWARN
ACK_TSD
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
DCDC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DCDC Short circuit protection detected
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
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24
NCV6357
Table 12. INTERRUPT SENSE REGISTER
Name: INTSEN
Type: R
Address: 01h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_TWARN
SEN_TPREW
Spare = 0
SEN_ISHORT
SEN_UVLO
SEN_IDCDC
SEN_PG
Bit
Power Good Sense
Bit Description
SEN_PG
0: DCDC Output Voltage below target
1: DCDC Output Voltage within nominal range
SEN_IDCDC
SEN_UVLO
SEN_ISHORT
SEN_TPREW
SEN_TWARN
SEN_TSD
DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
DCDC Short−Circuit Protection Sense
0: Short−Circuit detected not detected
1: Short−Circuit not detected
Thermal Pre−Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
Table 13. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 03h
Default: 00011011b (21h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 14. REVISION ID REGISTER
Name: RID
Type: R
Address: 04h
Default: Metal
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
Bit
RID[7..0]
Bit Description
Revision Identification
00000000: First Silicon
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25
NCV6357
Table 15. FEATURE ID REGISTER
Name: FID
Type: R
Address: 05h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare
Spare
Spare
Spare
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
00000000: NCV6357A 5.0 A, 1.80 V − 1.10 V configuration
00000001: NCV6357B 5.0 A, 0.90 V – 1.00 V configuration
Table 16. POWER GOOD REGISTER
Name: PGOOD
Address: 12h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Bit
Spare = 0
Spare = 0
DISCHG
TOR[1..0]
PGDVS
PGDCDC
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
Power Good Active On DVS
0 = Disabled
1 = Enabled
TOR[1..0]
Time out Reset settings for Power Good
00 = 0 ms
01 = 8 ms
10 = 32 ms
11 = 64 ms
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
Table 17. TIMING REGISTER
Name: TIME
Address: 13h
Type: RW
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
DVS[1..0]
D2
D1
D0
DELAY[2..0]
Spare = 0
DBN_Time[1..0]
Bit
Bit Description
DBN_Time[1..0]
EN and VSEL debounce time
00 = No debounce
01 = 1−2 ms
10 = 2−3 ms
11 = 3−4 ms
DVS[1..0]
DVS Speed
00 = 6.25 mV step / 0.333 ms
01 = 6.25 mV step / 0.666 ms
10 = 6.25 mV step / 1.333 ms
11 = 6.25 mV step / 2.666 ms
DELAY[2..0]
Delay applied upon enabling (ms)
000b = 0 ms – 111b = 14 ms (Steps of 2 ms)
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26
NCV6357
Table 18. COMMAND REGISTER
Name: COMMAND
Address: 14h
Default: See Register map
Type: RW
Trigger: N/A
D7
PPWMVSEL0
Bit
D6
D5
D4
D3
D2
D1
D0
PPWMVSEL1
DVSMODE
Sleep_Mode
ENVSEL0
ENVSEL1
Spare
VSELGT
Bit Description
VSELGT
VSEL Pin Gating
0 = Disabled
1 = Enabled
ENVSEL1
ENVSEL0
EN Pin Gating for VSEL internal signal = High
0: Disabled
1: Enabled
EN Pin Gating for VSEL internal signal = Low
0: Disabled
1: Enabled
Sleep_Mode
DVSMODE
PPWMVSEL1
PPWMVSEL0
Sleep mode
0 = Low Iq mode when EN and VSEL low
1 = Force product in sleep mode (when EN and VSEL are low)
DVS transition mode selection
0 = Auto
1 = Forced PPWM
Operating mode for MODE internal signal = High
0 = Auto
1 = Forced PPWM
Operating mode for MODE internal signal = Low
0 = Auto
1 = Forced PPWM
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27
NCV6357
Table 19. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Address: 16h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
Bit
TPWTH[1..0]
Spare = 0
FORCERST
RSTSTATUS
REARM
Bit Description
REARM
Rearming of device after TSD / ISHORT
0: No re−arming after TSD / ISHORT
2
1: Re−arming active after TSD / ISHORT with no reset of I C registers: new power−up sequence is initiated
2
with previously programmed I C registers values
RSTSTATUS
FORCERST
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0 = Default value. Self cleared to 0
1: Force reset of internal registers to default
Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK
Inductor peak current settings
00 = 5.2 A (for 3.5 A output current)
01 = 5.8 A (for 4.0 A output current)
10 = 6.2 A (for 4.5 A output current)
11 = 6.8 A (for 5.0 A output current)
Table 20. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER
Name: PROGVSEL1
Type: RW
Address: 17h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
VoutVSEL1[7..0]
Bit Description
D3
D2
D1
D0
Bit
VoutVSEL1[7..0]
Sets the DC to DC converter output voltage when VSEL pin = 1 (and VSEL pin function is enabled in
register COMMAND.D0) or when VSEL pin function is disabled in register COMMAND.D0
0000000b = 0.6 V – 11011000 ~ 1111111b = 3.3 V (steps of 12.5 mV)
Table 21. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER
Name: PROGVSEL0
Type: RW
Address: 18h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
VoutVSEL0[7..0]
Bit Description
D3
D2
D1
D0
Bit
VoutVSEL0[7..0]
Sets the DC to DC converter output voltage when VSEL pin = 0 (and VSEL pin function is enabled in
register COMMAND.D0)
0000000b = 0.6 V – 11011000 ~ 1111111b = 3.3 V (steps of 12.5 mV)
www.onsemi.com
28
NCV6357
APPLICATION INFORMATION
NCV6357
Supply Input
AVIN
PVIN
4.7 mF
Supply Input
Core
AGND
10 mF
Thermal
Protection
DCDC
5 A
Enable Control EN
Input
SW
Operating
Mode
Control
330 nH
Modular
Driver
Voltage VSEL
Selection
2 × 22 mF
PGND
FB
Output
Monitoring
PG
Power Good
DCDC
Processor
Core
GND
SDA
2
2.4 MHz
Sense
Controller
I C
Processor I@C
Control Interface
GND
SCL
Figure 54. Typical Application Schematic
Output Filter Considerations
The output filter introduces a double pole in the system at
a frequency of:
Components Selection
Inductor Selection
The inductance of the inductor is chosen such that the
peak−to−peak ripple current I is approximately 20% to
1
fLC
+
L_PP
Ǹ
(eq. 1)
2 p L C
50% of the maximum output current I
. This
OUT_MAX
The NCV6357 internal compensation network is
optimized for a typical output filter comprising a 330 nH
inductor and 47 mF capacitor as describes in the basic
application schematic in Figure 54.
provides the best trade−off between transient response and
output ripple. The inductance corresponding to a given
current ripple is:
(VIN * VOUT) VOUT
L +
Voltage Sensing Considerations
VIN fSW IL_PP
(eq. 2)
In order to regulate the power supply rail, the NCV6357
must sense its output voltage. The IC can support two
sensing methods:
The selected inductor must have a saturation current
rating higher than the maximum peak current which is
calculated by:
• Normal sensing: The FB pin should be connected to the
IL_PP
output capacitor positive terminal (voltage to regulate)
IL_MAX + IOUT_MAX
)
2
(eq. 3)
• Remote sensing: The power supply rail sense should be
made close to the system powered by the NCV6357.
The voltage to the system is more accurate, since the
PCB line impedance voltage drop is within the
regulation loop. In this case, we recommend connecting
the FB pin to the system decoupling capacitor positive
terminal
The inductor must also have a high enough current rating
to avoid self−heating. A low DCR is therefore preferred.
Refer to Table 22 for recommended inductors.
www.onsemi.com
29
NCV6357
Table 22. INDUCTOR SELECTION
Size (L y l y T)
Saturation
Current Max (A)
DCR Max
at 255C (mW)
(mm)
Supplier
Cyntec
Cyntec
Cyntec
TOKO
TOKO
TOKO
TDK
Part #
Value (mH)
0.33
PIFE20161B−R33MS−11
PIFE25201B−R33MS−11
PIFE32251B−R33MS−11
DFE252012F−H−R33M
DFE201612E−H−R33M
FDSD0412−H−R33M
VLS252012HBX−R33M
SPM5030T−R35M
2.0 × 1.6 × 1.2
2.5 × 2.0 × 1.2
3.2 × 2.5 × 1.2
2.5 × 2.0 × 1.2
2.0 × 1.6 × 1.2
4.2 × 4.2 × 1.2
2.5 × 2.0 × 1.2
7.1 × 6.5 × 3.0
2.0 × 1.6 × 1.2
4.0
5.2
6.5
5.1
4.8
7.5
5.3
14.9
4.8
33
17
14
13
21
19
25
4
0.33
0.33
0.33
0.33
0.33
0.33
TDK
0.35
Chilisin
HEI201612A−R24M−AUDG
0.24
13.5
IOUT_MAX (D * D2)
VIN_PP fSW
Output Capacitor Selection
VOUT
VIN
CIN_MIN
+
where D +
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance a high output capacitor
value must be used. For a given peak−to−peak ripple current
In addition, the input capacitor must be able to absorb the
input current, which has a RMS value of
Ǹ
IIN_RMS + IOUT_MAX
D * D2
I
in the inductor of the output filter, the output voltage
L_PP
ripple across the output capacitor is the sum of three
components as shown below.
The input capacitor also must be sufficient to protect the
device from over voltage spikes, and a 4.7 mF capacitor or
greater is required. The input capacitor should be located as
close as possible to the IC. All PGND pins must be
connected together to the ground terminal of the input cap
which then must be connected to the ground plane. All PVIN
pins must be connected together to the Vbat terminal of the
input cap which then connects to the Vbat plane.
VOUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
With:
IL_PP
VOUT_PP(C)
+
8 C fSW
VOUT_PP(ESR) + IL_PP ESR
LESL
L
VOUT_PP(ESL)
+
VIN
Power Capability
The NCV6357’s power capability is driven by the
Where the peak−to−peak ripple current is given by
difference in temperature between the junction (T ) and
J
(VIN * VOUT) VOUT
ambient (T ), the junction−to−ambient thermal resistance
IL_PP
+
A
VIN fSW L
(R ), and the on−chip power dissipation (P ).
qJA
IC
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
The on−chip power dissipation P can be determined as
IC
.
P
= PT − PL
OUT_PP(C)
IC
with the total power losses
P
T
being
The minimum output capacitance can be calculated based on
1
ǒ Ǔ
PT + Vout IOUT
* 1
h
a given output ripple requirement V
operation mode.
in PPWM
OUT_PP
where h is the efficiency and P the simplified inductor
L
IL_PP
PL = I LOAD 2 x DCR
power losses
.
CMIN
+
8 VOUT_PP fSW
Now the junction temperature T can easily be calculated
J
TJ = RqJA x PIC + TA
as
.
Input Capacitor Selection
Please note that the
T
J
should stay within the
One of the input capacitor selection requirements is the
input voltage ripple. To minimize the input voltage ripple
and get better decoupling at the input power supply rail, a
ceramic capacitor is recommended due to low ESR and ESL.
The minimum input capacitance with respect to the input
recommended operating conditions.
The R is a function of the PCB layout (number of layers
and copper and PCB size). For example, the NCV6357
qJA
mounted on the EVB has a R
about 30°C/W.
qJA
ripple voltage V
is
IN_PP
www.onsemi.com
30
NCV6357
Layout Considerations
• PGND directly connected to Cin input capacitor, and
then connected to the GND plane: Local mini planes
used on the top layer (green) and the layer just below
the top layer (yellow) with laser vias
Electrical Rules
Good electrical layout is key to proper operation, high
efficiency, and noise reduction. Electrical layout guidelines
are:
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement
• SW connected to the Lout inductor with local mini
planes used on the top layer (green) and the layer just
below the top layer (yellow) with laser vias
(See Figure 55 / 56 for example)
• The device should be well decoupled by input capacitor
and the input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission
• SW track should be wide and short to reduce losses and
noise radiation
• It is recommended to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane
Thermal Rules
Good PCB layout improves the thermal performance and
thus allows for high power dissipation even with a small IC
package. Thermal layout guidelines are:
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation
• Use multiple vias around the IC to connect the inner
ground layers to reduce thermal impedance
Figure 55. Placement Recommendation
• Use a large and thick copper area especially in the top
layer for good thermal conduction and radiation
• Use two layers or more for the high current paths
(PVIN, PGND, SW) in order to split current into
different paths and limit PCB copper self−heating
Component Placement
• Input capacitor placed as close as possible to the IC
• PVIN directly connected to Cin input capacitor, and
then connected to the Vin plane. Local mini planes used
on the top layer (green) and the layer just below the top
layer (yellow) with laser vias
• AVIN connected to the Vin plane just after the capacitor
• AGND directly connected to the GND plane
Figure 56. Demo Board Example
www.onsemi.com
31
NCV6357
Table 23. ORDERING INFORMATION
†
Device
Marking
Output Voltage
Package
Shipping
NCV6357MTWATXG
6357A
5.0 A
1.80 V / 1.10 V
DFN 3.0 x 4.0 mm
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NCV6357MTWBTXG
NCV6357MTWCTXG
NCV6357MTWDTXG
NCV6357MTWFTXG*
6357B
6357C
6357D
6357F
5.0 A
0.90 V / 1.00 V
DFN 3.0 x 4.0 mm
(Pb−Free)
5.0 A
1.80 V / 1.10 V
DFN 3.0 x 4.0 mm
(Pb−Free)
5.0 A
1.25 V / 1.25 V
DFN 3.0 x 4.0 mm
(Pb−Free)
5.0 A
DFN 3.0 x 4.0 mm
1.00 V / 1.10 V
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Not released yet.
www.onsemi.com
32
MECHANICAL CASE OUTLINE
0.10
0.05
C
C
G
G
M
M
0.07
0.05
C A B
C
G
G
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