NCV70517MW002R2G [ONSEMI]
微步进电机驱动器;
| 型号： | NCV70517MW002R2G |
| 厂家： | 
ONSEMI |
| 描述： | 微步进电机驱动器 电动机控制 电机 驱动 驱动器 |
| 文件： | 总25页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV70517
Micro-stepping Motor Driver
Description
The NCV70517 is a micro−stepping stepper motor driver for bipolar
stepper motors. The chip is connected through I/O pins and an SPI
interface with an external microcontroller. The NCV70517 contains
a current−translation table and takes the next micro−step depending on
the clock signal on the “NXT” input pin and the status of the “DIR”
(= direction) register or input pin. The chip provides an error message
if an electrical error, an under−voltage or an elevated junction
temperature is detected. It is using a proprietary PWM algorithm
for reliable current control.
NCV70517 is fully compatible with the automotive voltage
requirements and is ideally suited for general−purpose stepper motor
applications in the automotive, industrial, medical, and marine
environment.
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32
1
QFNW32
CASE 484AB
Due to the technology, the device is especially suited for use
in applications with fluctuating battery supplies.
MARKING DIAGRAM
Features
1
• Dual H−bridge for 2−phase Stepper Motors
• Programmable Peak−current up to 800 mA
• Low Temperature Boost Current up to 1100 mA
• On−chip Current Translator
N70517−2
FAWLYYWWG
G
• SPI Interface
N70517−2
= Specific Device Code
• 5 Step Modes from Full−step up to 16 Micro−steps
• Fully Integrated Current−sensing and Current−regulation
• Back−EMF Measurement
F
A
WL
YY
WW
G
= Fab Location
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• On Chip Stall Detection
• PWM Current Control with Automatic Selection of Fast and Slow
Decay
• Fixed PWM Frequency
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 23 of this data sheet.
• Active Fly−back Diodes
• Full Output Protection and Diagnosis
• Thermal Warning and Shutdown
• Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs, 5 V
Tolerant Open Drain Outputs
• Reset Function
• Overcurrent Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
December, 2018 − Rev. 0
NCV70517/D
NCV70517
TYPICAL APPLICATION SCHEMATIC
The application schematic below shows typical
connections for applications with low axis counts and/or
with software SPI implementation. For applications with
many stepper motor drivers, some “minimal wiring”
examples are shown at the last sections of this datasheet.
D1
100 nF
C4
100 nF
C3
100 nF
C2
VBAT
VDD
C1
100 uF
R1 R2
VDD
VBB
VBB
DIR
NXT
DO
R3
R4
MOTXP
R8
R5
DI
NCV70517
C5
C6
CLK
MOTXN
uC
R6
CSB
M
R7
MOTYP
MOTYN
ERRB
R9
C7
C8
GND
Figure 1. Typical Application Schematic
Table 1. EXTERNAL COMPONENTS
Component
Function
Typ. Value
22 ... 100
100
Max Tolerance
20%
Unit
mF
nF
nF
nF
kW
kW
W
C1
C2, C3
C4
V
buffer capacitor (Note 1)
BB
BB
V
decoupling capacitor (Note 2)
20%
Optional V decoupling capacitor (Note 3)
100
20%
DD
C5, C6, C7, C8
R1, R2
R3 – R7
R8, R9
D1
Optional EMC filtering capacitor (Note 4)
Pull up resistor
1 ... 3.3 max
1..5
20%
10%
Optional resistors
1
10%
Optional resistors (Note 5)
Optional reverse protection diode
100
10%
e.g. MURD530
1. Low ESR < 4 W, mounted as close as possible to the NCV70517. Total decoupling capacitance value has to be chosen properly to reduce
the supply voltage ripple and to avoid EM emission.
2. C2 and C3 must be close to pins VBB and coupled GND directly.
3. Radiated emissions around 100 MHz can be improved by avoiding this capacitor.
4. Optional capacitors for improvement of EMC and system ESD performance. The slope times on motor pins can be longer than specified
in the AC table.
5. Value depends on characteristics of mC inputs for DO and ERRB signals.
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NCV70517
VDD
VBB
Internal voltage
regulator 3.3 V
Timebase
STALL
CLK
CSB
DI
EMC
MOTXP
MOTXN
P
W
M
T
TSD
R
SPI
A
I−sense
N
S
L
A
T
O
R
Open/
Short
DO
Logic &
Registers
NXT
DIR
EMC
MOTYP
MOTYN
P
W
M
OTP
POR
ERRB
I−sense
NCV70517
UV
detect
Band−
gap
GND
Figure 2. Block Diagram
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NCV70517
PACKAGE AND PIN DESCRIPTION
32 31 30 29 28 27 26 25
MOTXP
1
2
3
4
24 MOTYP
23
MOTXP
VBB
MOTYP
22 VBB
21
VBB
DIR
NC
VBB
QFN32 5x5
NCV70517
20
5
6
7
8
NC
19
NC
18
17
NC
NC
CSB
NXT
9
10 11
12 13 14 15 16
Figure 3. Pin Connections – QFNW32 5x5
Table 2. PIN DESCRIPTION
Pin No.
QFNW32 5x5
Pin Name
MOTXP
VBB
Description
Positive end of phase X coil
Battery voltage supply
Direction input
I/O Type
Driver Output
Supply
1, 2
3, 4, 21, 22
5
DIR
Digital Input
6, 7, 14, 15, 18, 19, 20
NC
Not Connected
8
CSB
SPI chip select input
SPI data input
Digital Input
Digital Input
Digital Output
Digital Output
Supply
9
DI
10
DO
SPI data output (Open Drain)
Error Output (Open Drain)
Internal supply
11
12
ERRB
VDD
13
GND
Ground
Supply
16
CLK
SPI clock input
Digital Input
Digital Input
Driver Output
Supply
17
NXT
Next micro−step input
Positive end of phase Y coil
Ground
23, 24
25, 26, 31, 32
27, 28
29, 30
MOTYP
GNDP
MOTYN
MOTXN
Negative end of phase Y coil
Negative end of phase X coil
Driver Output
Driver Output
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NCV70517
Table 3. ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Min
−0.3
−0.3
−50
−55
−2
Max
+40
+6.0
+175
+160
+2
Unit
V
Supply voltage (Note 6)
V
BB
Digital input/outputs voltage
V
IO
V
Junction temperature range (Note 7)
Storage Temperature (Note 8)
T
j
°C
°C
kV
kV
T
strg
HBM Electrostatic discharge voltage (Note 9)
System Electrostatic discharge voltage (Note 10)
V
esd_hbm
V
−8
+8
syst_esd
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. V Max is +43 V for limited time < 0.5 s.
BB
7. The circuit functionality is not guaranteed.
8. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.
9. HBM according to AEC−Q100: EIA−JESD22−A114−B (100 pF via 1.5 kW).
10.System ESD, 150 pF, 330 W, contact discharge on the connector pin, unpowered.
Operating ranges define the limits for functional
operation and parametric characteristics of the device. A
mission profile (Note 11) is a substantial part of the
operation conditions; hence the Customer must contact
ON Semiconductor in order to mutually agree in writing on
the allowed missions profile(s) in the application.
Table 4. RECOMMENDED OPERATING RANGES
Characteristic
Symbol
Min
+6
Typ
Max
+29
Unit
V
Battery Supply voltage
V
BB
Digital input/outputs voltage
V
0
+5.5
+145
+160
V
IO
Parametric operating junction temperature range (Note 12)
Functional operating junction temperature range (Note 13)
T
−40
−40
°C
°C
jp
T
jf
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,
the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the
device is operated by the customer, etc. No more than 100 cumulated hours in life time above T .
tw
12.The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.
13.The maximum functional operating temperature range can be limited by thermal shutdown T
.
tsd
Package Thermal Characteristic
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the Rth from the
junction to the exposed pad (Rthjp).
Using an exposed die pad on the bottom surface of the
package is mainly contributing to this performance. In order
to take full advantage of the exposed pad, it is most
important that the PCB has features to conduct heat away
from the package. In the table below, one can find the values
for the Rthja and Rthjp:
The NCV70517 is available in a thermally optimized
QFNW32 5x5 package. For the optimizations, the package
has an exposed thermal pad which has to be soldered to the
PCB ground plane. The ground plane needs thermal vias to
conduct the heat to the bottom layer.
For precise thermal cooling calculations the major
thermal resistances of the devices are given. The thermal
media to which the power of the devices has to be given are:
• Static environmental air (via the case)
• PCB board copper area (via the device pins and
exposed pad)
Table 5. THERMAL RESISTANCE
Package
Rth, Junction−to−Exposed Pad, Rthjp
QFNW32 5x5
6 K/W
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NCV70517
EQUIVALENT SCHEMATICS
The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
DIGITAL
OUT
DIGITAL
IN
DI, CLK,
NXT, DIR
ERRB
Ipd
VDD
Ipu
MOT
OUT
DIGITAL
IN
CSB
MOTXP,
MOTXN,
MOTYN,
MOTYP
VDD
VBB
DIGITAL
OUT
DO
Figure 4. Input and Output Equivalent Diagrams
ELECTRICAL CHARACTERISTICS
DC PARAMETERS
The DC parameters are guaranteed over junction
temperature from −40 to 145°C and VBB in the operating
range from 6 to 29 V, unless otherwise specified.
Convention: currents flowing into the circuit are defined as
positive.
Table 6. DC PATAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
MOTORDRIVER
I
MOTXP
MOTXN
MOTYP
MOTYN
Max current through motor coil in
normal operation
V
= 14 V
800
mA
MSmax,Peak
BB
I
Max current during booster function
Absolute error on coil current
V
V
= 14 V, T = −45°C
1100
mA
%
MSboost,Peak
BB
j
I
= 14 V, T = 145°C
−10
−7
10
7
MSabs
BB
j
I
= 800 mA
MSmax,Peak
and 100 mA
I
Matching of X & Y coil currents
V
= 14 V
%
W
MSrel
BB
MSmax,Peak
I
= 800 mA
and 100 mA
R
On resistance of High side + Low
side Driver at the highest current
range
T = 145°C
2.4
DS(on)
j
R
Motor pin pull−down resistance
HiZ mode
70
kW
mpd
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NCV70517
Table 6. DC PATAMETERS (continued)
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
LOGIC INPUTS
V
CSB
Logic low input level, max
Logic high input level, min
0.8
V
V
inL
V
inH
2.4
I
Input pull up current for logic low
level (Note 14)
25
mA
inL_pu
I
Input pull up current for logic low
level in sleep mode (Note 14)
3
1
mA
mA
inL_pu_slp
I
Input leakage current for logic high
level
inH_pu
V
DI, CLK
Logic low input level, max
Logic high input level, min
0.8
V
V
inL
V
inH
2.4
75
R
DI, CLK pin pull−down resistance
(Note 14)
150
150
300
0.8
kW
inpd
V
inL
NXT, DIR Logic low input level, max
Logic high input level, min
V
V
V
inH
2.4
75
R
NXT, DIR pin pull−down resistance
(Note 14)
300
kW
inpd
OPEN DRAIN LOGIC OUTPUT
V
ERRB
Output voltage
6 mA sink current
0.4
5.5
12
V
V
OLmax
OHmax
OLmax
V
Maximum drain voltage
I
Maximum allowed drain current
(Note 22)
mA
PUSH−PULL LOGIC OUTPUT WHEN CSB = 0 (Figure 4)
V
DO
Output voltage low
6 mA sink current
0.4
V
V
OLmax
V
Output voltage high without pull−up
Maximum pin voltage
4 mA source current
V
DD
− 1.3
OHmin
OHmax
OLmax
V
5.5
12
V
I
Maximum allowed pin current
(Note 22)
mA
THERMAL WARNING & SHUTDOWN
T
Thermal warning (Notes 15 and 16)
135
155
12
145
165
28
155
175
44
°C
°C
°C
tw
T
tsd
Thermal shutdown (Note 17)
T
low
Low temperature level (Note 15)
SUPPLY AND VOLTAGE REGULATOR
UV
UV
V
BB
H−Bridge off voltage low threshold
Under voltage hysteresis
5.7
6.0
250
4
6.3
600
15
V
100
mV
mA
_HYST
I
Total current consumption (Note 18)
Unloaded outputs
bat
V
= 29 V
BB
I
Sleep mode current consumption at
V
= 5.5 V & 18 V
12
20
3.6
3.0
80
mA
V
bat_s
BB
temperature ≤ 85°C (Note 19)
T ≤ 85°C
j
V
V
DD
Regulated internal supply (Note 20)
5.5 V < V < 29 V
Load = 0 mA, 15 mA
3.0
3.3
DD
BB
V
Digital supply reset level @ power
down (Note 21)
V
ddReset
I
Current limitation
Pin shorted to ground
mA
ddLim
V
BB
= 14 V
14.All Pull−up and pull down currents stay activated during sleep to avoid floating input pins. Placing the pin in wrong state during sleep results
in higher sleep currents in the application.
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NCV70517
15.Thermal warning and low temperature level are derived from thermal shutdown (T = T – 20°C, T
= T – 137°C).
tsd
tw
tsd
low
16.No more than 100 cumulated hours in life time above T .
tw
17.Parameter guaranteed by trimming relevant OTPs in production test at 160°C and VBB = 14 V.
18.Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs.
19.All outputs unloaded, no floating inputs. Not tested in production, guaranteed by device characterization.
20.Pin VDD must not be used for any external supply.
21.The SPI registers content will not be altered above this voltage.
22.Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.
1
0,8
0,6
0,4
Typ
BestCase
0,2
WorstCase
0
−50
0
50
100
150
temp [5C]
Figure 5. ON Resistance of High Side + Low Side Driver at the Highest Current Range
24
22
20
18
VBB = 14 V
16
VBB = 18 V
14
12
10
8
−40
−20
0
20
40
60
80
100
120
140
temp [5C]
Figure 6. Typical Sleep Mode Current Consumption
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NCV70517
AC PARAMETERS
The AC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6
to 29 V, unless otherwise specified.
Table 7. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
10
Max
Unit
INTERNAL OSCILLATOR
f
Frequency of internal oscillator
V
BB
= 14 V
9
11
MHz
osc
MOTORDRIVER
f
MOTxx
PWM frequency
(Note 23)
28.4
kHz
%
pwm
f
PWM jitter modulation depth
SPI bit PWMJen = 1
(Note 23)
20
jit_depth
t
Open coil detection with
PWM = 100% (Note 23)
SPI bit OpenDet [1:0] = 00
SPI bit OpenDet [1:0] = 01
SPI bit OpenDet [1:0] = 10
SPI bit OpenDet [1:0] = 11
SPI bit EMC [1:0] = 00
SPI bit EMC [1:0] = 01
SPI bit EMC [1:0] = 10
SPI bit EMC [1:0] = 11
SPI bit EMC [1:0] = 00
SPI bit EMC [1:0] = 01
SPI bit EMC [1:0] = 10
SPI bit EMC [1:0] = 11
SPI bit UVtime [1:0] = 00
SPI bit UVtime [1:0] = 01
SPI bit UVtime [1:0] = 10
SPI bit UVtime [1:0] = 11
5
25
ms
OCdet
50
200
150
300
1000
2000
150
300
1000
2000
0
t
Turn−on transient time, between
ns
brise
10% and 90%, I
BB
= 300 mA,
MD
V
= 13.5 V, 1 nF at motor pins
t
Turn−off transient time, between
10% and 90%, I = 200 mA,
ns
bfall
MD
V
BB
= 13.5 V, 1 nF at motor pins
UV
MOTxx
Under−voltage debounce time
(Note: H−bridge off)
ms
time
5
10
30
DIGITAL OUTPUTS
t
DO,
ERRB
Output fall−time (90% to 10%)
Capacitive load 200 pF
and pull−up 1.5 kW
50
ns
H2L
from V
to V
InH
InL
HARD RESET FUNCTION
t
DIR
Hard reset trigger time (Note 23)
Hard reset DIR pulse width
NXT set−up time
See hard reset function
(Note 23)
20
2.5
2.5
ms
ms
ms
ms
ms
ms
hr_trig
t
hr_dir
hr_set
t
NXT
ERRB
CSB
(Note 23)
t
Hard reset error indication
CSB wake−up low pulse width
(Note 23)
50
hr_err
t
(Note 23)
2
150
csb_width
t
CSB no wake−up low pulse
width
(Note 23)
220
csb_no_wu
t
wu
Wake−up time
See Sleep Mode
250
ms
NXT/DIR INPUTS
t
NXT
NXT minimum, high pulse width
NXT minimum, low pulse width
NXT max repetition rate
2
2
ms
ms
NXT_HI
t
NXT_LO
f
f
/2
kHz
ms
NXT
PWM
t
-
NXT pin trigger after SPI NXT
command
1
CSB_LO_WIDT
H
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NCV70517
Table 7. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
NXT/DIR INPUTS
t
NXT, DIR NXT set time, following change
of DIR
25
25
ms
ms
DIR_SET
t
NXT hold time, before change
of DIR
DIR_HOLD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
23.Derived from the internal oscillator.
Table 8. SPI INTERFACE
Symbol
Parameter
Min
0.5
Typ
Max
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
t
CSB setup time (Note 24)
CSB hold time
CSS
CSH
t
0.5
t
CSB high time
1
CS
t
CLK low time
0.5
WL
t
CLK high time
0.5
WH
t
DI set up time, valid data before rising edge of CLK
DI hold time, hold data after rising edge of CLK
CSB low to DO valid
0.25
0.275
SU
t
H
t
0.23
0.32
CSDO
t
Output (DO) disable time (Note 25)
Output (DO) valid (Note 25)
0.08
DIS
t
0.32
→
V1
V0
0
1
t
Output (DO) valid (Note 26)
0.32 + t(RC)
→
24.After leaving sleep mode an additional wait time of 250 ms is needed before pulling CSB low.
25.SDO low–side switch activation time.
26.Time depends on the SDO load and pull–up resistor.
tCS
V
IH
CSB
V
IL
tCSH
tCSS
tWH
tWL
V
IH
CLK
V
IL
tSU tH
V
IH
DI
DI13
DI15
DI14
DI1
DI0
V
IL
tDIS
tV
tCSDO
V
IH
DO
HI−Z
HI−Z
DO15
DO14
DO13
DO1
DO0
V
IL
Figure 7. SPI Timing
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NCV70517
DETAILED OPERATING DESCRIPTION
H−Bridge Drivers with PWM Control
In order to reduce the radiated/conducted emission,
voltage slope control is implemented in the output switches.
A protection against shorts on motor lines is implemented.
When excessive voltage is sensed across a MOSFET for a
time longer than the required transition time, then the
MOSFET is switched−off.
Two H−bridges are integrated to drive a bipolar stepper
motor. Each H−bridge consists of two low−side N−type
MOSFET switches and two high−side P−type MOSFET
switches. One PWM current control loop with on−chip
current sensing is implemented for each H−bridge.
Depending on the desired current range and the micro−step
Motor Enable−Disable
position at hand, the R
of the low−side transistors will
DS(on)
The H−bridges and PWM control can be disabled
(high−impedance state) by means of a bit <MOTEN> in the
SPI control registers. <MOTEN>=0 will only disable the
drivers and will not impact the functions of NXT, DIR, SPI
bus, etc. The H−bridges will resume normal PWM operation
by writing <MOTEN>=1 in the SPI register. PWM current
control is then enabled again and will regulate current in
both coils corresponding with the position given by the
current translator.
be adapted to maintain current−sense accuracy.
A comparator compares continuously the actual winding
current with the requested current and feeds back the
information to generate a PWM signal, which turns on/off
the H−bridge switches. The switching points of the PWM
duty−cycle are synchronized to the on−chip PWM clock.
The PWM frequency will not vary with changes in the
supply voltage. Also variations in motor−speed or
load−conditions of the motor have no effect. There are no
external components required to adjust the PWM frequency.
In order to avoid large currents through the H−bridge
switches, it is guaranteed that the top− and bottom−switches
of the same half−bridge are never conductive
simultaneously (interlock delay).
Automatic Forward and Slow−Fast Decay
The PWM generation is in steady−state using
a combination of forward and slow−decay. For transition to
lower current levels, fast−decay is automatically activated to
allow high−speed response. The selection of fast or slow
decay is completely transparent for the user and no
additional parameters are required for operation.
Icoil
Set value
Actual value
t
0
T
PWM
Forward & Slow Decay
Forward & Slow Decay
Fast Decay & Forward
Figure 8. Forward and Slow/Fast Decay PWM
Automatic Duty Cycle Adaptation
completely automatic and requires no additional parameters
for operation. The state of the duty cycle adaptation mode is
represented in the internal T/B bits for both motor windings
X and Y. Figure 9 gives a representation of the duty cycle
adaptation.
If during regulation the set point current is not reached
before 75% of t , the duty cycle of the PWM is adapted
pwm
automatically to > 50% (top regulation) to maintain the
requested average current in the coils. This process is
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NCV70517
|Icoil |
Duty Cycle
< 50%
Duty Cycle < 50%
Set value
Duty Cycle > 50%
Actual value
0
T
PWM
Bit T/B
Bottom reg. Bit T/B = 0
Bottom reg. Bit T/B = 0
Top reg. Bit T/B = 1
Figure 9. Automatic Duty Cycle Adaptation
Active Break
When the micro−step resolution is reduced, then the
corresponding least−significant bits of the translator
position are set to “0”. This means that the position in the
current table moves to the right and in the case that
micro−step position of desired new resolution does not
overlap the micro−step position of current resolution, the
closest value up or down in required column is set depending
on the direction of rotation.
When the micro−step resolution is increased, then the
corresponding least−significant bits of the translator
position are added as “0”: the micro−step position moves to
the left on the same row.
In general any change of <SM[2:0]> SPI bits have no
effect on current micro−step position without consequent
occurrence of NXT pulse or <NXTP> SPI command (see
NXT input timing below). When NXT pulse or <NXTP>
SPI command arrives, the motor moves into next micro−step
position according to the current <SM[2:0]> SPI bits value.
Besides the micro−step modes, also full step mode is
implemented. Full step mode activates always only one coil
at a time.
Whenever active break is activated (<ACTBR> bit is set),
both bottom drivers of active H−bridge (based on actual
MSP position) are switched on.
By this mean the position is frozen and current starts
recirculating through the bottom drivers, causing faster
stopping of the motor.
STEP TRANSLATOR
Step Mode
The step translator provides the control of the motor
by means of step mode SPI register SM[2:0], SPI bits DIRP,
NXTP and input pins DIR (direction of rotation) and NXT
(next pulse). It is translating consecutive steps
into corresponding currents in both motor coils for a given
step mode.
One out of five possible stepping modes can be selected
through SPI−bits SM[2:0]. After power−on or hard reset, the
coil−current translator is set to the default to 1/16
micro−stepping at position ‘8*’. When remaining in the
default step mode, subsequent translator positions are all in
the same column and increased or decreased with 1. Table 9
lists the output current versus the translator position.
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12
NCV70517
Table 9. TRANSLATOR TABLE
MSP[5:0]
Step mode SM[2:0]
% of Imax
MSP[5:0]
Step mode SM[2:0]
% of Imax
000
1/16
0
001
1/8
0
010
1/4
0
011
1/2
0
100
FS
0
000
1/16
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
001
1/8
16
−
010
1/4
8
011
1/2
4
100
FS
2
MSP[5:0]
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111
01 1000
01 1001
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
Coil Y Coil X MSP[5:0]
Coil Y Coil X
0
100
99,5
98,1
95,7
92,4
88,2
83,1
77,3
70,7
63,4
55,6
47,1
38,3
29
10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111
10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111
11 0000
11 0001
11 0010
11 0011
11 0100
11 0101
11 0110
11 0111
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
0
−100
1
−
−
−
−
1
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
9,8
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−9,8
−99,5
2
1
19,5
29
17
−
−
−19,5 −98,1
−29 −95,7
3
−
−
4
2
38,3
47,1
55,6
63,4
70,7
77,3
83,1
88,2
92,4
95,7
98,1
99,5
100
99,5
18
−
9
−38,3 −92,4
−47,1 −88,2
−55,6 −83,1
−63,4 −77,3
−70,7 −70,7
−77,3 −63,4
−83,1 −55,6
−88,2 −47,1
−92,4 −38,3
5
−
−
−
−
2
−
6
3
19
−
−
7
−
−
8(*)
9
4
20
−
10
−
−
−
−
−
3
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
5
21
−
−
−
−
6
22
−
11
−
−
−
−
−
4
−95,7
−29
7
19,5
9,8
23
−
−
−98,1 −19,5
−
−
−99,5
−100
−99,5
−98,1
−95,7
−92,4
−88,2
−83,1
−77,3
−70,7
−63,4
−55,6
−47,1
−38,3
−29
−9,8
0
8
0
24
−
12
−
−
−
−
−
5
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−9,8
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
9,8
9
98,1 −19,5
95,7 −29
25
−
−
19,5
29
−
−
10
−
92,4 −38,3
88,2 −47,1
83,1 −55,6
77,3 −63,4
70,7 −70,7
63,4 −77,3
55,6 −83,1
47,1 −88,2
38,3 −92,4
26
−
13
−
38,3
47,1
55,6
63,4
70,7
77,3
83,1
88,2
92,4
95,7
98,1
99,5
−
−
−
6
11
−
27
−
−
−
12
−
28
−
14
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
13
−
29
−
−
−
14
−
30
−
15
−
−
−
−
29
19,5 −98,1
9,8 −99,5
−95,7
15
−
31
−
−
−19,5
−9,8
−
*Default position after reset of the translator position.
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13
NCV70517
Translator Position
The translator position can be read and set by the SPI
0.8VCC
register <MSP[5:0]>. This is a 6−bit number equivalent to
CSB
NXT
th
the 1/16 micro−step from Table 9: Translator Table. The
tCSB_LO_WIDTH
translator position is updated immediately following a next
micro−step trigger (see below).
0.2VCC
NXT
Figure 11. NXT Input Non Overlapping Zone with
the <NXTP> SPI Command
Update
Update
Translator Position
Translator Position
For control by means of I/O’s, the NXT pin operation with
respect to DIR pin should be in a non−overlapped way. See
also the timing diagram below (refer to the Table 7 − AC
Parameters for the timing values). The <SM[2:0]> SPI bits
setting, when changed, is accepted upon the consequent
either NXT pin rising edge or <NXTP> SPI command write
only. On the other hand, the SPI bits <DIRP>, <SM[2:0]>
and <NXTP> can change state at the same time in the same
SPI command: the next micro−step will be applied with the
new settings. Writing to the SPI register <MSP[5:0]> is
accepted and applied to translator table immediately, does
not taking actual step mode into account.
Figure 10. Translator Position Timing Diagram
Direction
The direction of rotation is selected by means of input pin
DIR and its “polarity bit” <DIRP> (SPI register). The
polarity bit <DIRP> allows changing the direction of
rotation by means of only SPI commands instead of the
dedicated input pin.
Direction = DIR−pin EXOR <DIRP>
Positive direction of rotation means counter−clockwise
rotation of electrical vector Ix + Iy. Also when the motor is
disabled (<MOTEN>=0), both the DIR pin and <DIRP>
will have an effect on the positioner. The logic state of the
DIR pin is visible as a flag in SPI status register.
tNXT_HI
tNXT_LO
Next Micro−Step Trigger
0,5 V
CC
NXT
DIR
Positive edges on the NXT input − or activation of the
“NXT pushbutton” <NXTP> in the SPI input register − will
move the motor current one step up/down in the Table 9 −
Translator table. The <NXTP> bit in SPI is used to move
positioner one (micro−)step by means of only SPI
commands. If the bit is set to “1”, it is reset automatically to
“0” after having advanced the positioner with one
micro−step.
tDIR_SET tDIR_HOLD
VALID
Figure 12. NXT input Timing Diagram
Trigger “Next micro−step” = (positive edge on NXT−pin)
OR (<NXTP>=1)
Motor Current
On cold temperatures below T
Parameters) the current can be boosted to higher values by
SPI bit <IBOOST>. After reaching temperature of thermal
(see Table 6 − DC
low
• Also when the motor is disabled (<MOTEN>=0),
NXT/DIR functions will move the positioner according
to the logic (only if <NXTfilter>=0).
warning T , current is automatically decreased to
tw
• In order to be sure that both the NXT pin and the
<NXTP> SPI command are individually attended, the
following non overlapping zone has to be respected.
In this case it is guaranteed that both triggers will have
effect (2 steps are taken).
unboosted level. Status of the boost function can be read in
SPI <IBOOST> bit. The motor current settings correspond
to the following current levels:
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14
NCV70517
Stall and Motion Detection
Table 10. IMOT VALUES (4BIT)
Motion detection is based on the Back Electromotive
Force (BEMF or back emf) generated into the running
motor. When the motor is blocked, e.g. when it hits the
end−position, the velocity and as a result also the generated
back emf, is disturbed. The NCV70517 measures the back
emf during the current zero crossing phase and makes it
available in the SPI status register SR5. The back emf
voltage is measured several times in each PWM cycle during
zero crossing phase. Samples taken during PWM ON phase
of the switches in the second coil are discarded not to add
noise to measurement (see Figure 13). Results are then
converted into a 5−bits word <Bemf[4:0]> with the
following formula:
Register
Value
Peak Motor
Current IMOT (mA)
Peak Boost Motor
Current IMOT (mA)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
59
81
98
71
84
116
138
164
194
231
275
327
389
462
550
655
778
925
1100
100
119
141
168
200
238
283
336
400
476
566
673
800
25
2.41
5
4
BEMF_code(dec) + V_MOT_XorY_diff(V) Gain ( )
When the result is ready, it is indicated by <BemfRes> bit
in status register.
When using normal mode of back emf measurement
(<EnhBemfEn> = 0), last sample before end of current zero
crossing phase becomes available in <Bemf[4:0]> register
(see the red circle on Figure 13).
When the enhanced back emf measurement mode is set by
<EnhBemfEn> bit, all non discarded results are
continuously available in <Bemf[4:0]> register (see red and
all black circles on Figure 13). This allows microcontroller
(when reading content of the register fast enough) to follow
back emf signal and its shape during zero crossing phase and
use more complex algorithms to optimize the work of driven
stepper motor.
Whenever <IMOT[3:0]> is changed, the new coil currents
will be updated immediately at the next PWM period.
In case the motor is disabled (<MOTEN>=0), the logic is
functional and will have effect on NXT/DIR operation (not
on the H−bridges). When the chip is in sleep mode, the logic
is not functional and as a result, the NXT pin and DIR pin
will have no effect.
Note: The hard−reset function is embedded by means of a
special sequence on the DIR pin and NXT pin, see also
Hard−Reset Function chapter.
I coil X
Ideal Coil Current
0
Under−voltage Detection
The NCV70517 has one undervoltage threshold level UV
(see Table 6 − DC Parameters).
Real Coil Current
Current Decay
Zero crossing position
(0;32 )
Undervoltage warning <UVW> bit is activated as when
the UV comparator threshold is hit (cleared by read as when
the undervoltage condition disappears). This allows the
MCU taking actions at system level if required.
When supply voltage VBB drops below UV threshold and
stays there longer than set undevoltage debounce time, the
undervoltage detection <UV> flag is set and ERRB pin is
pulled down. Undervoltage debounce time can be selected
by means of <UV_time[1:0]> register.
t
NXT
NXT
Pins MXP/MXN in HiZ state
V MXP/MXN
MXN
MXP MXP MXP
VBB + 0.6 V
MXN
VBEMF
Voltage Transient
Only if the <UV>=0 the motor can be enabled again
by writing <MOTEN>=1 in the control register.
Behavior of the H-bridge after UV detection can be
selected by <UV_act> bit. When <UV_act> = 0, H-bridge
goes to Hi-Z state. When <UV_act> = 1, H-bridge motor
brake (shorted to GDN).
t
t
V MYP/MYN MYP MYP MYP MYP MYP MYP
BEMF
sampling
Note: When Next pulse is applied (by means of NXT pin or
<NXTP> bit via SPI) during undervoltage condition, the
step loss bit <SL> is set.
Figure 13. Back Emf Sampling
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15
NCV70517
For slow speed or when a motion ends at a full step
current. Sign is determined by comparator, which compares
the polarity of voltage measured over the coil with expected
polarity of voltage.
position (there is an absence of next NXT trigger), the end
of the zero crossing is taking too long or is non−existing. In
this case, the back emf voltage is taken the latest at “stall
time−out” time and this value is used also for comparison
with <StThr[3:0]> stall threshold to detect stall situation.
The “stall time−out” is set in SPI by means of <StTo[7:0]>
H−bridge
HiZ state
V
XP
V
XN
register and is expressed in counts of 4/f
(See AC
pwm
V
BEMF
Parameters), roughly in steps of 0.2 ms. If <StTo[7:0]> = 0,
time−out is not active.
NXT
NXT
At the end of the current zero crossing phase the internal
circuitry compares measured back emf voltages
with <StThr[3:0]> register, which determines threshold for
stall detection. The last sample of back emf taken before end
of zero crossing phase is used for stall detection in normal
mode as well as in enhanced back emf mode. When
<StThr[3:0]> = 0 then stall detection is disabled. When
value of <StThr[3:0]> is different from 0 and measured back
emf signal is lower than <StThr[3:0]> threshold for 2
succeeding coil current zero−crossings (including both X
and Y coil), then the <STALL> bit in SPI status register 1
is set, the current translator table goes 135 degrees
in opposite direction and the ERRB pin is pulled down,
IMOT is maintained. Direction has to change its state at least
once and then <STALL> bit can be cleared by reading the
status register 1. With stall bit cleared, the chip reacts on
“Next Micro−step Triggers” and ERRB pin becomes
inactive again.
XP
XN
2 mA
BEMF polarity
XOR
Bemfs
Expected polarity
Figure 14. Back Emf Sign Value
The last measured back emf value <Bemf[4:0]>, sign flag
<Bemfs> and coil where the last back emf sample was taken
<Bemfcoil> can be read out via SPI.
Table 11. STALL THRESHOLDS SETTINGS (4BIT)
StThr Index
StThr Level (V)
BemfGain = 0
Disable
0.48
StThr Level (V)
BemfGain = 1
Disable
0.24
Notes:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1. Used stall detection is covered by patent US
8,058,894B2
2. As the stall threshold register <StThr[3:0]> is 4
bits wide, the 4 MSBs of 5−bit <Bemf[4:0]>
register are taken for comparison
0.96
0.48
1.44
0.72
1.92
0.96
Stall detection and Bemf measurement are performed
only when Speed register value <Sp[7:0]> is less than or
equal to Speed threshold register value <SpThr[7:0]>.
Stall detection is disabled if time between two consecutive
NXT pulses is lower than 74.5 ms (PWMJen = 0) or 80 ms
(PWMJen = 1).
Range and resolution of Speed register and Speed
threshold register are 0 to 5100 us and 20 us/digit for half
stepping mode. Accuracy of speed (time) measurement is
given by the accuracy of the internal oscillator.
2.4
1.2
2.88
1.44
3.36
1.68
3.84
1.92
4.32
2.16
4.8
2.4
5.28
2.64
5.76
2.88
6.24
3.12
If measured back emf voltage has not expected polarity,
the back emf sign flag <Bemfs> is set. Motor pin, where
lower voltage is expected, is tied to GND by pull down
6.72
3.36
7.2
3.6
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16
NCV70517
WARNING, ERROR DETECTION AND
DIAGNOSTICS FEEDBACK
to protect the integrated circuit. Each driver stage has
an individual detection bit for the N side and the P side.
When short circuit is detected, <MOTEN> is set to 0. The
positioner, the NXT and DIR stay operational. The flag
<ELDEF> (result of OR−ing the latched flags:
<SHRTXPT> OR <SHRTXPB> OR <SHRTXNT> OR
<SHRTYXNB> OR <SHRTYPT> OR <SHRTYPB> OR
<SHRTYNT> OR <SHRTYNB> OR <OPENX> OR
<OPENY>) is reset when the microcontroller reads out the
short circuit or open coil status flags in status registers.
To enable the motor again after reading out of the status
flags, <MOTEN>=1 has to be written.
Open & Short Circuit Diagnostic
The NCV70517 stepper driver features an enhanced
diagnostic detection and feedback, to be read by the external
microcontroller unit (MCU). Among the main items of
interest for the application and typical failures, are open coil
and the short circuit condition, which may be to ground
(chassis), or to supply (battery line).
When in normal mode, the device will continuously check
upon errors with respect to the expected behavior.
Notes:
The open load condition is determined by the fact that the
PWM duty cycle keeps 100% value for a time longer than set
by <OpenDet[1:0]> register. This is valid of course only for
the X/Y coil where the current is supposed to circulate,
meaning that in full step positions (MSP[5:0] = {0; 16; 32;
48} (dec)) the open load can be detected only for one of the
coil at a time (respectively {X; Y; X; Y}). The same
reasoning applies for the short circuits detection.
1. Successive reading of the <SHRTij> flags and
re−enabling the motor in case of a short circuit
condition may lead to damage of the drivers.
2. Example: SHRTXPT means: Short at X coil,
Positive output pin, Top transistor.
3. In case of the short from any stepper motor pin
to the top side during switching event from bottom
to top on motor pin, the flag “short to bottom side”
is set instead of the expected “short to top side”
flag.
Due to the timeout value set by <OpenDet[1:0]>, the open
coil detection is dependent on the motor speed. In more
detail, there is a maximum speed at which it can be done.
Table 12 specifies these maxima for the different step
modes. For practical reasons, all values are given in full
steps per second.
Step Loss Detection
When Next pulse is applied (by means of NXT pin or
<NXTP> bit via SPI) or <MSP> register is written during
error condition, the step loss bit <SL> is set.
Table 12. MAXIMUM VELOCITIES FOR OPEN COIL
DETECTION
<SL> = (<UV> OR <TSD> OR <ELDEF>) AND ((NXT
OR <NXTP>) OR <MSP> write)
Step Mode
Speed [FS/s] for given <OpenDet[1:0]>
00
200
300
350
375
387.5
01
40
10
20
11
5
Step loss bit <SL> is cleared after read out.
Full Step
1/2
Thermal Warning and Shutdown
60
30
7.5
8.8
9.4
9.7
When junction temperature is above T , the thermal
tw
1/4
70
35
warning bit <TW> is set (SPI register) and the ERRB pin is
pulled down (*). If junction temperature increases
above thermal shutdown level, then also the <TSD> flag is
set, the ERRB pin is pulled down, the motor is disabled
1/8
75
37.5
38.8
1/16
77.5
When Open coil condition is detected, the appropriate bit
(<OPENX> or <OPENY>) together with <ELDEF> bit in
the SPI status register are set. Reaction of the H−bridge to
Open coil condition depends on the settings of <OpenHiZ>
and <OpenDis> bits.
When both <OpenHiZ> and <OpenDis> bits are 0,
<MOTEN> bit stays in 1 and only H−bridge where open coil
is detected is disabled. When <OpenHiZ> bit is set, both
H−bridges are disabled (<MOTEN>=0) in case of Open coil
detection. When <OpenDis> bit is set, drivers remain active
for both coils independently of <OpenHiZ> bit.
(<MOTEN> = 0) and the hardware reset is disabled. If T <
j
T
level and <TSD> bit has been read−out, the status
tw
of <TSD> is cleared and the ERRB pin is released.
Only if the <TSD>=<TW>=0, the motor can be enabled
again by writing <MOTEN>=1 in the control register 1.
During the over temperature condition the hardware reset
will not work until T < T and the <TSD> readout is done.
j
tw
In this way it is guaranteed that after a <TSD>=1 event,
the die−temperature decreases back to the level of <TW>.
After reaching temperature of thermal warning T , motor
tw
current is automatically decreased to unboosted level.
Note (*): During the <TW> situation the motor is not
disabled while the ERRB is pulled down. To be informed
about other error situations it is recommended to poll the
status registers on a regular base (time base driven
by application software in the millisecond domain).
The short circuit detection monitors the load current in
each activated output stage. The current is measured in terms
of voltage drop over the MOSFETS’ R
. If the load
DS(ON)
current exceeds the over−current detection threshold, the
appropriate over−current flag <SHRTij> together with
<ELDEF> bit are set and the drivers are switched off
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17
NCV70517
Error Output
Notes:
This is an open drain output to flag a problem to the
external microcontroller. The signal on this output is active
low and the logic combination of:
• The hard−reset function is disabled in sleep mode.
• The CSB low pulse width has to be within t
,
csb_with
(see Table 7 − AC Parameters) to guarantee a correct
wake−up.
NOT(ERRB) = (<SPI> OR <ELDEF> OR <TSD> OR
<TW> OR <STALL> OR (BemfIntEn AND BemfRes) OR
<UV> OR (*)reset state) AND not (**)sleep mode
Power−on Reset, Hard−Reset Function
After a power−on or a hard−reset, a flag <HR> in the SPI
status register is set and the ERRB is pulled low. The ERRB
stays low during this reset state. The typical power−on reset
Note (*) reset state: After a power−on or a hard−reset, the
ERRB is pulled low during t
Parameters).
(Table 7 − AC
hr_err
time is given by t
(Table 7 − AC Parameters). After the
hr_err
Note (**) sleep mode: In sleep mode the ERRB is always
inactive (high).
reset state the device enters sleep mode and the ERRB pin
goes high to indicate the motor controller is ready for
operation.
Sleep Mode
By means of a specific pattern on the DIR pin and NXT
pin, the complete digital part of driver can be reset without
a power−cycle. This hard−reset function is activated when
the input pin DIR changes logic state “0 → 1 → 0 → 1” in
five consecutive patterns during NXT pin being at high
level. See figure below and Table 7 − AC Parameters.
The operation of all analog circuits is suspended during
the reset state of the digital. Similar as for a normal
power−on, the flag <HR> is set in the SPI register after a
The motor driver can be put in a low−power consumption
mode (sleep mode). The sleep mode is entered automatically
after a power−on or hard reset and can also be activated by
means of SPI bit <SLP>. In sleep−mode, all analog circuits
are suspended in low−power, logic output pin ERRB is
disabled (ERRB has no function) and none of the input pins
is functional with the exception of pin CSB. Only CSB pin
can wake−up the chip to normal mode (i.e. clear bit <SLP>)
by means of a low pulse with a specified width within
hard−reset and the ERRB pin is pulled low during t
(Table 7 − AC Parameters).
hr_err
t
time. Time t (see Table 7 − AC Parameters) is
csb_with
wu
needed to restore all analog and digital circuits
after wake−up.
thr_trig
DIR
thr_set
thr_dir
NXT
thr_err
ERRB
Figure 15. Hard Reset Timing Diagram
SPI INTERFACE
General
and sampling of the information on the two serial data lines:
DO and DI. The DO signal is the output from the Slave
(NCV70517), and the DI signal is the output from the
Master.
A slave or chip select line (CSB) allows individual
selection of a slave SPI device in a time multiplexed
multiple−slave system.
The CSB line is active low. If an NCV70517 is not
selected, DO is in high impedance state and it does not
interfere with SPI bus activities. Since the NCV70517
always clocks data out on the falling edge and samples data
The serial peripheral interface (SPI) is used to allow
an external microcontroller (MCU) to communicate
with the device. NCV70517 acts always as a slave and it
cannot initiate any transmission. The operation of the device
is configured and controlled by means of SPI registers,
which are observable for read and/or write from the master.
The NCV70517 SPI transfer size is 16 bits.
During an SPI transfer, the data is simultaneously
transmitted (shifted out serially) and received (shifted in
serially). A serial clock line (CLK) synchronizes shifting
www.onsemi.com
18
NCV70517
in on rising edge of clock, the MCU SPI port must be
configured to match this operation.
The implemented SPI allows connection to multiple
slaves by means of star connection (CSB per slave) or by
means of daisy chain.
An SPI star connection requires a bus = (3 + N) total lines,
where N is the number of Slaves used, the SPI frame length
is 16 bits per communication.
MOSI
NCV70517 dev#1
(SPI Slave )
CSB1
MCU
(SPI Master )
NCV70517 dev#1
(SPI Slave)
MISO
SDO1
SDI2
CSB2
MCU
NCV70517 dev#2
NCV70517 dev#2
(SPI Slave)
(SPI Master )
(SPI Slave )
SDO2
CSBN
SDIN
NCV70517 dev#N
NCV70517 dev#N
(SPI Slave )
SDON
(SPI Slave)
Figure 16. SPI Star vs. Daisy Chain Connection
SPI Transfer Format
SPI Daisy chain mode
SPI daisy chain connection bus width is always four lines
independently on the number of slaves. However, the SPI
transfer frame length will be a multiple of the base frame
length so N x 16 bits per communication: the data will be
interpreted and read in by the devices at the moment the CSB
rises.
A diagram showing the data transfer between devices in
daisy chain connection is given further: CMDx represents
the 16−bit command frame on the data input line transmitted
by the Master, shifting via the chips’ shift registers through
the daisy chain. The chips interpret the command once the
chip select line rises.
Two types of SPI commands (to DI pin of NCV70517)
from the micro controller can be distinguished: “Write to a
control register” and “Read from register (control or
status)”.
The frame protocol for the write operation:
Write; CMD = ‘1’
High
Low
C
M
D
A
3
A
2
A
1
A
0
D D D D D D D D D D
DI
P
9
8 7 6 5 4 3 2 1 0
Low
Previous SPI WRITE command
resp. “SPIERR + 0x000hex”
after POR or SPI Command
S
P
I
E
R
R
C
M
D
A
3
A
2
A
1
A
0
D D D D D D D D D D
DO
9
8
7
6
5
4
3
2
1
0
PARITY/FRAMING Error
HIGH−Z
S
P
I
E
R
R
E
L
D
E
F
Previous SPI READ command
& NCV70516 status bits resp.
“SPIERR + 0x000hex” after
POR or SPI Command
C
M
D
T
S
D
A
4
A
3
A
2
A
1
A
0
U
V
T
W
P
1
1
1
0
PARITY/FRAMING Error
CLK
Low
P
=
not(CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor
D6 xor D5 xor D4 xor D3 xor D2 xor D1 xor D0)
Figure 18. SPI Write Frame
Referring to the previous picture, the write frame coming
from the master (into the DI) is composed from the
following fields:
• Bit[15] (MSB): CMD bit = 1 for write operation,
Figure 17. SPI Daisy Chain Data Shift Between
Slaves. The symbol ‘x’ represents the previous
content of the SPI shift register buffer.
• Bits[14:11]: 4 bits WRITE ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
• Bits[9:0]: 10 bit DATA to write
The NCV70517 default power up communication mode
is “star”. In order to enable daisy chain mode, a multiple of
16 bits clock cycles must be sent to the devices, while the
SDI line is left to zero.
Device in the same time replies to the master (on the DO):
• If the previous command was a write and no SPI error
had occurred, a copy of the command, address and data
written fields,
• If the previous command was a read, the response
frame summarizes the address used and an overall
Note: to come back to star mode the NOP register (address
0x0000) must be written with all ones, with the proper data
parity bit and parity framing bit: see SPI protocol for details
about parity and write operation.
www.onsemi.com
19
NCV70517
diagnostic check (copy of the main detected errors, see
Figure 18 and Figure 19 for details),
• In case of previous SPI error or after power−on−reset,
only the MSB bit will be 1, followed by zeros.
Referring to the previous picture, the read frame coming
from the master (into the DI) is composed from the
following fields:
• Bit[15] (MSB): CMD bit = 0 for read operation,
• Bits[14:10]: 5 bits READ ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
• Bits [8:0]: 9 bits zeroes field.
If parity bit in the frame is wrong, device will not perform
command and <SPI> flag will be set.
The frame protocol for the read operation:
Read; CMD = ‘0’
High
Device in the same frame provides to the master (on the DO)
data from the required address (in frame response), thus
achieving the lowest communication latency.
TW, TSD, ELDEF, UV:
immediate value of STATUS BITS
dedicated SPI READ Command of STATUS
Register has to be performed to clear
the value of read −by−clear STATUS bits
Low
;
C
M
D
A
4
A
3
A
2
A
1
A
0
DI
P
SPI Framing and Parity Error
Low
Low
S
P
I
E
R
R
SPI communication framing error is detected by the
NCV70517 in the following situations:
E
L
D
E
F
Data from address A [4:0]
shall be returned
T
S
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
U
V
T
W
0
DO
HIGH−Z
• Not an integer multiple of 16 CLK pulses are received
during the active−low CSB signal;
• LSB bits (8..0) of a read command are not all zero;
• SPI parity errors, either on write or read operation.
CLK
Low
P
=
not(CMD xor A4 xor A3 xor A2 xor A1 xor A0)
Once an SPI error occurs, the <SPI> flag can be reset only
by reading the status register in which it is contained (using
in the read frame the right communication parity bit). This
request will reset the SPI error bit and release the ERRB pin
(high).
Figure 19. SPI Read Frame
SPI Control Registers (CR)
All SPI control registers have Read/Write access.
Table 13. SPI CONTROL REGISTERS (CR)
5−bit
Default
Address
after Res.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00 0000
0000
00h
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
00 0000
0000
01h (CR1)
02h (CR2)
03h (CR3)
04h (CR4)
0Bh (CR5)
0Ch (CR6)
NXTfilter
NXTP
PWMJen
UVtime1
−
MOTEN
DIRP
IBOOST
OpenDis
ACTBR
IMOT3
SLP
IMOT2
SM2
IMOT1
SM1
IMOT0
SM0
00 1000
1000
−
UVact
−
OpenDet1 OpenDet0
OpenHiZ
00 0000
0000
UVtime0
−
BemfIntEn EnhBemfEn BemfGain
StThr3
MSP3
StTo3
SpThr3
StThr2
MSP2
StTo2
SpThr2
StThr1
MSP1
StTo1
SpThr1
StThr0
MSP0
StTo0
SpThr0
00 0000
1000
−
MSP5
StTo5
MSP4
StTo4
01 0001
0000
EMC1
−
EMC0
−
StTo7
SpThr7
StTo6
SpThr6
00 0000
0000
SpThr5
SpThr4
Table 14. BIT DEFINITION
Symbol
NOP
MAP position
Description
NOP register (read/write operation ignored)
Bits [9:0] – ADDR_0x00
Bit 9 – ADDR_0x01 (CR1)
Bit 8 – ADDR_0x01 (CR1)
Bit 7 – ADDR_0x01 (CR1)
Bit 6 – ADDR_0x01 (CR1)
NXTfilter
NXTP
Filters out pulses coming from the NXT pin when the motor (H−bridge) is disabled
Push button pin, generating next step in position table
Enables the H−bridges (motor activated)
MOTEN
DIRP
Polarity of DIR pin, which controls direction status; DIRP = 1 inverts the logic
polarity of the DIR pin)
IBOOST
ACTBR
Bit 5 – ADDR_0x01 (CR1)
Bit 4 – ADDR_0x01 (CR1)
Current boost function activation and status
Active break
www.onsemi.com
20
NCV70517
Table 14. BIT DEFINITION (continued)
IMOT[3:0]
PWMJen
Bits [3:0] – ADDR_0x01 (CR1)
Bit 8 – ADDR_0x02 (CR2)
Bits [7:6] – ADDR_0x02 (CR2)
Bit 5 – ADDR_0x02 (CR2)
Current amplitude
Enable PWM jittering function to spread spectrum of PWM modulation
OpenDet[1:0]
OpenDis
Open Coil detection time setting bits (see Table 7 − AC Parameters)
When bit is set, Open Coil detection status is flagged, but drivers control remain
active for both coils, <OpenDis> bit setting has higher priority than <OpenHiZ> bit
OpenHiZ
Bit 4 – ADDR_0x02 (CR2)
When bit is set, during Open Coil detection both drivers are deactivated
(MOTEN=0)
SLP
SM[2:0]
UVact
Bit 3 – ADDR_0x02 (CR2)
Bits [2:0] – ADDR_0x02 (CR2)
Bit 9 – ADDR_0x03 (CR3)
Places device in sleep mode with low current consumption (when 1)
Step mode selection
“0”: H bridge left open upon under voltage detection;
“1”: H bridge motor brake (shorted to GND), when undervoltage is detected
UVtime[1:0]
BemfIntEn
EnhBemfEn
BemfGain
StThr[3:0]
MSP[5:0]
Bits [8:7] – ADDR_0x03 (CR3)
Bit 6 – ADDR_0x03 (CR3)
Bit 5 – ADDR_0x03 (CR3)
Bit 4 – ADDR_0x03 (CR3)
Bits [3:0] – ADDR_0x03 (CR3)
Bit [5:0] – ADDR_0x04 (CR4)
Bits [9:8] – ADDR_0x0B (CR5)
Under−voltage filter (debounce) time (see Table 7 − AC Parameters)
BEMF result interrupt enable
Enhanced BEMF measurement functionality is activated when bit is set
Gain of BEMF measurement channel = “0”: gain 0.5, “1”: gain 0.25
Threshold level for stall detection, when “0”, stall detection is disabled
Setting or status of translator micro−step position
EMC[1:0]
Voltage slope defining bits for motor driver switching (see Table 7 − AC Parame-
ters)
StTo[7:0]
Bits [7:0] – ADDR_0x0B (CR5)
Bits [7:0] – ADDR_0x0C (CR6)
tall time−out. Max difference between two successive full step next pulse periods
(time−out), after this time the BEMF sample is taken to verify stall
SpThr[7:0]
Speed threshold register, BEMF measurement and stall detection is activated
when Speed register value is less than or equal to <SpThr> value
SPI Status Registers (SR)
All SPI status registers have Read Only Access, with the odd parity on Bit8. Parity bit makes the numbers of 1 in the byte
odd.
Table 15. SPI STATUS REGISTERS (SR)
Default
after
Res.
5−bit
Address
Bit 9
05h (SR1) 0x0
06h (SR2) 0x0
07h (SR3) 0x0
08h (SR4) 0x0
09h (SR5) 0x0
Bit 8
PAR
PAR
PAR
Bit 7
SL,L
0x0
Bit 6
HR,L
SPI,L
Bit 5
ELDEF,R* TAMB,R
TSD,L
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UVW,L
TW,R
UV,L
Stall,L
OPENX,L SHRTXPB,L SHRTXNB,L SHRTXPT,L SHRTXNT,L
0x0
NXTpin, R DIRpin, R OPENY,L SHRTYPB,L SHRTYNB,L SHRTYPT,L SHRTYNT,L
PAR DEVID4 DEVID3
DEVID2
DEVID1
DEVID0
REVID2
REVID1
REVID0
PAR
Bemf
−Res,L
Bemf
−Coil,R
Bemfs,R Bemf4, R Bemf3, R
Bemf2, R
Bemf1, R
Bemf0, R
0Ah (SR6) 0x0
PAR
Sp7,R
Sp6,R
Sp5,R
Sp4,R
Sp3,R
Sp2,R
Sp1,R
Sp0,R
Flags have “,L” for latched information or “,R” for real time information. All latched flags are “cleared upon read”.
X = value after reset is defined during reset phase (diagnostics)
R* = real time read out of values of other latches. Reading out this R* value does not reset the bit, and does not reset the values of the
latches this bit reads out.
www.onsemi.com
21
NCV70517
Table 16. BIT DEFINITION
Symbol
MAP Position
Description
PAR
SL
Bit 8 – ADDR_0x05 (SR1)
Bit 7 – ADDR_0x05 (SR1)
Bit 6 − ADDR_0x06 (SR2)
Parity bit for SR1
Step loss register
HR
Hard reset flag: 1 indicates a hard reset has occurred
ELDEF
Bit 5 – ADDR_0x05 (SR1)
Eletrical defect: Short circuit was detected (at least one of the SHORTij
individual bits is set) or Open Coil X or Y was detected
TAMB
UVW
TW
Bit 4 – ADDR_0x05 (SR1)
Bit 3 – ADDR_0x06 (SR2)
Bit 2 – ADDR_0x05 (SR1)
Bit 1 – ADDR_0x05 (SR1)
Bit 0 – ADDR_0x05 (SR1)
Bit 8 – ADDR_0x06 (SR2)
Bit 6 – ADDR_0x05 (SR1)
Temperature below T level − Iboost function can be activated
low
Under−voltage warning – UV threshold hit
Thermal warning
UV
Under voltage detection – action taken according to UVact bit
Stall detected by the internal algorithm
Parity bit for SR2
Stall
PAR
SPI
SPI error: no multiple of 16 rising clock edges between falling and rising
edge of CSB line
TSD
Bit 5 – ADDR_0x05 (SR1)
Bit 4 – ADDR_0x06 (SR2)
Bit 3 – ADDR_0x06 (SR2)
Bit 2 – ADDR_0x06 (SR2)
Bit 1 – ADDR_0x06 (SR2)
Bit 0 – ADDR_0x06 (SR2)
Bit 8 – ADDR_0x07 (SR3)
Bit 6 – ADDR_0x07 (SR3)
Bit 5 – ADDR_0x07 (SR3)
Bit 4 – ADDR_0x07 (SR3)
Bit 3 – ADDR_0x07 (SR3)
Bit 2 – ADDR_0x07 (SR3)
Bit 1 – ADDR_0x07 (SR3)
Bit 0 – ADDR_0x07 (SR3)
Bit 8 – ADDR_0x08 (SR4)
Bits [7:3] – ADDR_0x08 (SR4)
Bits [2:0] – ADDR_0x08 (SR4)
Bit 8 – ADDR_0x09 (SR5)
Bit 7 – ADDR_0x09 (SR5)
Bit 6 – ADDR_0x09 (SR5)
Bit 5 – ADDR_0x09 (SR5)
Bits [4:0] – ADDR_0x09 (SR5)
Bits [7:0] – ADDR_0x0A (SR6)
Thermal shutdown
OPENX
Open Coil X detected
SHRTXPB
SHRTXNB
SHRTXPT
SHRTXNT
PAR
Short circuit detected at XP pin towards ground (Bottom)
Short circuit detected at XN pin towards ground (Bottom)
Short circuit detected at XP pin towards supply (Top)
Short circuit detected at XN pin towards supply (Top)
Parity bit for SR3
NXTpin
Read out of NXT pin logic status
DIRpin
Read out of DIR pin logic status
OPENY
Open Coil Y detected
SHRTYPB
SHRTYNB
SHRTYPT
SHRTYNT
PAR
Short circuit detected at YP pin towards ground (Bottom)
Short circuit detected at YN pin towards ground (Bottom)
Short circuit detected at YP pin towards supply (Top)
Short circuit detected at YN pin towards supply (Top)
Parity bit for SR4
DEVID[4:0]
REVID[2:0]
PAR
Device ID
Revision ID
Parity bit for SR5
BemfRes
BemfCoil
Bemfs
BEMF result ready at <Bemf> register
Last BEMF measurement was done on coil: 0 = X, 1 = Y
BEMF measured voltage has expected polarity (Yes = 0, No = 1)
BEMF value measured during zero crossing
Speed register
Bemf[4:0]
Sp[7:0]
DEVID [4:0] for NCV70517 device is (17)
dec.
REVID [2:0] for N70517−2 device is (3)
dec.
www.onsemi.com
22
NCV70517
APPLICATION EXAMPLES FOR MULTI−AXIS CONTROL
The wiring diagrams below show possible connection of
Further I/O reduction is accomplished in case the ERRB
is not connected. This would mean that the microcontroller
operates while polling the error flags of the slaves.
Ultimately, one can operate multiple slaves by means of only
4 SPI connections: even the NXT pin can be avoided if the
microcontroller operates the motors by means of the
“NXTP” bit.
multiple slaves to one microcontroller. In these examples,
all movements of the motors are synchronized by means of
a common NXT wire. The direction and Run/Hold
activation is controlled by means of an SPI bus.
Microcontroller
IC1 NCV70517
NXT
CSB
NXT
CSB1
DI/DO/CLK
ERRB
3
/DO
DI
/CLK
ERRB
3
3
IC2 NCV70517
NXT
CSB
/DO
CSB2
DI
/CLK
ERRB
“Multiplexed SPI”
IC3 NCV70517
NXT
CSB
/DO
CSB3
DI
/CLK
ERRB
Rpu
vcc
Figure 20. Examples of Wiring Diagrams for Multi−axis Control
ELECTRO MAGNETIC COMPATIBILITY
The NCV70517 has been developed using
Special care has to be taken into account with long wiring
to motors and inductors. A modern methodology to regulate
the current in inductors and motor windings is based on
controlling the motor voltage by PWM. This low frequency
switching of the battery voltage is present at the wiring
towards the motor or windings. To reduce possible radiated
transmission, it is advised to use twisted pair cable and/or
shielded cable.
state−of−the−art design techniques for EMC. The overall
system performance depends on multiple aspects of the
system (IC design & lay−out, PCB design and layout …..)
of which some are not solely under control of the IC
manufacturer. Therefore, meeting system EMC
requirements can only happen in collaboration with all
involved parties.
ORDERING INFORMATION
†
Device
Peak Current
End Market/Version
Package*
Shipping
NCV70517MW002R2G
800/1100 mA
(Note 27)
Automotive
High Temperature
Version
QFNW32 5x5 with step−cut
wettable flank (Pb−Free)
5000 / Tape & Reel
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
27.The device boost current. This applies for operation under the thermal warning level only.
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW32 5x5, 0.5P
CASE 484AB
ISSUE D
DATE 07 SEP 2018
32
1
SCALE 2:1
L3
L4
L3
L4
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
L
L
REFERENCE
ALTERNATE
CONSTRUCTION
DETAIL A
E
MILLIMETERS
EXPOSED
COPPER
DIM MIN
NOM
0.90
−−−
0.20 REF
−−−
0.25
5.00
3.10
5.00
3.10
0.50 BSC
−−−
0.40
−−−
0.08 REF
MAX
1.00
0.05
A
A1
A3
A4
b
D
D2
E
0.80
−−−
A4
A1
0.10
0.20
4.90
3.00
4.90
3.00
−−−
0.30
5.10
3.20
5.10
3.20
TOP VIEW
PLATING
A1
A4
ALTERNATE
CONSTRUCTION
DETAIL B
A
DETAIL B
(A3)
0.10
0.08
C
C
E2
e
C
C
L3
K
L
L3
L4
0.35
0.30
−−−
−−−
0.50
0.10
A3
A4
SEATING
PLANE
C
NOTE 4
SIDE VIEW
DETAIL A
PLATED
GENERIC
MARKING DIAGRAM*
SURFACES
D2
9
SECTION C−C
17
8
1
32X
L
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
E2
1
32
25
K
32X
b
e
XXXXX = Specific Device Code
M
0.10
C A B
e/2
BOTTOM VIEW
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
M
NOTE 3
0.05
C
WL
YY
WW
G
RECOMMENDED
SOLDERING FOOTPRINT*
(Note: Microdot may be in either location)
5.30
32X
0.63
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
3.35
1
3.35
5.30
PACKAGE
OUTLINE
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14940G
QFNW32 5x5, 0.5P
PAGE 1 OF 1
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