NCV7343D20R2G [ONSEMI]
CAN FD Transceiver, Low Power, with INH, WAKE and Error Detection;
| 型号： | NCV7343D20R2G |
| 厂家： | 
ONSEMI |
| 描述： | CAN FD Transceiver, Low Power, with INH, WAKE and Error Detection |
| 文件： | 总23页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAN FD Transceiver,
Low Power, with INH,
WAKE and Error Detection
NCV7343
Description
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The NCV7343 CAN FD transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7343 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers
and previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7343 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbit/s to cope with CAN
flexible data rate requirements (CAN FD). These features make
the NCV7343 an excellent choice for all types of HS−CAN networks,
in nodes that require a low−power mode with wake−up capability via
the CAN bus.
14
1
1
SOIC−14
D2 SUFFIX
DFNW14 4.5x3, 0.65P
MW SUFFIX
CASE 751A−03
CASE 507AC
MARKING DIAGRAM
1
14
8
14
1
8
NCV
7343
ALYW
G
NCV7343
AWLYWWG
Features
• Compliant with International Standard ISO11898−2:2016
• CAN FD Timing Specified up to 5 Mbit/s
• Extended Bus Load Range
7
7
SOIC−14
DFNW14
• Standby and Sleep Mode with very Low Current Consumption
• CAN Wake−up with Wake−up Pattern (WUP), Short CAN Activity
Filter Time, Long Wake−up Timeout and Normal Bus Biasing.
• Local Wake−up
A
(W)L
= Assembly Site
= Wafer Lot
YW(W) = Date Code
G or G = Pb−Free Identification
• V Pin Allowing Direct Interfacing with 3 V to 5 V MCUs
IO
• Low Electromagnetic Emission (EME) and High Electromagnetic
Susceptibility (EMS)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
• High Impedance Bus Lines in Unpowered State
• Transmit Data (TxD) Dominant Timeout Function (Long)
• Bus Error Detection
• Under all Supply Conditions the Chip behaves Predictably
• ESD Robustness of Bus Pins > 8 kV
• Thermal Protection
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
• Bus Pins Protected against Transients in an Automotive Environment
• AEC−Q100 Grade 0 Qualified and PPAP Capable
• These are Pb−Free Devices
Quality
• Wettable Flank Package for Enhanced Optical Inspection
Typical Applications
• Automotive
• Industrial Networks
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
February, 2021 − Rev. 0
NCV7343/D
NCV7343
TYPICAL APPLICATION
VBAT
ECU
IN
IN
RPP
VIO 3V3 / 5V
VCC 5V
OUT
INH
OUT
INH
CVIO
CVCC
CVB
VIO
VCC
INH VB
VDD
WAKE
STBN
EN
WAKE
RWAKE2
Host Interface
ERRN
MCU
NCV7343
CMC
CANH
CANL
CAN
GND
TxD
RxD
CAN Controller
VSS
2x RT
CST
GND
Figure 1. Typical Application Diagram
RECOMMENDED EXTERNAL COMPONENTS FOR THE APPLICATIONS DIAGRAM
Symbol
Parameter
Decoupling Capacitor on V Supply Pin, Ceramic
Value
100
1
Unit
Note
C
C
C
R
R
nF
mF
nF
kW
kW
mH
W
VB
B
Decoupling Capacitor on V Supply Pin, Ceramic
VCC
CC
Decoupling Capacitor on V Supply Pin, Ceramic
100
33
VIO
IO
WAKE Pin Pull−up Resistor
WAKE1
WAKE2
WAKE Pin Serial Protection Resistor
Common Mode Choke
3.3
100
60
CMC
(Note 1)
R
C
Terminating Resistors
< 1%, ≥ 0.25 W
< 20%, 50 V
LT
Common−mode Stabilization Capacitor, Ceramic
4.7
nF
ST
1. Murata DLW32SH101XF2, Murata DLW32SH101XK2, TDK ACT45B−101−2P, TDK ACT1210−101−2P
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2
NCV7343
BLOCK DIAGRAM
VIO
VCC
INH
VB
5
3
7
10
VIO
Local
Wakeup
Control
8
9
ERRN
STBN
EN
WAKE
14
6
Thermal
Shutdown
VCC
NCV7343
13
12
CANH
CANL
Mode control
+
Driver
VIO
Wake control
+
Error detection
control
1
4
Tx
Timeout
TxD
RxD
Wake−up
Filter
COMP
COMP
VIO
Rx
Timeout
V
CC/2
OSC
UV
2
11
GND
NC
Figure 2. NCV7343 Block Diagram
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3
NCV7343
PIN CONNECTIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
STBN
TxD
GND
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
TxD
GND
VCC
STBN
CANH
CANL
NC
CANH
CANL
NC
RxD
VIO
RxD
VIO
VB
VB
EN
WAKE
ERRN
EN
WAKE
ERRN
EP
8
INH
8
INH
(Top View)
(Top View)
Figure 4. Pin Connections − DFNW14
Figure 3. Pin Connections − SOIC−14
PIN FUNCTION DESCRIPTION
Pin
1
Name
TxD
Description
Transmit data input; low input " dominant driver; internal pull−up current
Ground
2
GND
3
V
CC
Supply voltage
4
RxD
Receive data output; dominant transmitter " low output
Input / Output pins supply voltage
5
V
IO
6
EN
Enable mode control input; internal pull−down current
High voltage output for controlling external voltage regulators
Digital output indicating errors and power−up; active low
Local wake−up input
7
INH
8
ERRN
WAKE
9
10
11
12
13
14
15
V
N
Battery supply connection
B
C
Not connected
CANL
CANH
STBN
EP
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input; internal pull−down current
Exposed Pad. Recommended to connect to GND or left floating in application (DFNW14 package only)
MAXIMUM RATINGS
Symbol
Parameter
Conditions
(Note 2)
(Note 2)
Min
−0.3
−0.3
−42
Max
+40
+6.0
+42
Unit
V
V
V
V
Supply Voltage, Pin V
B
B
Supply Voltage, Pin V , V
IO
V
SUP
CAN
CC
DC Voltage at Pins CANH and CANL
0 < V < 5.5 V;
V
CC
No time limit
V
DIFF
DC Voltage between Any Two Pins
(Including CANH and CANL)
−42
+42
V
V
V
V
DC Voltage at Pin TxD, STBN, EN
DC Voltage at Pin RxD, ERRN
DC Voltage at Pin INH
−0.3
−0.3
−0.3
−5
+40
V
V
DIG_IN
DIG_OUT
INH
V
+ 0.3
IO
V
+ 0.3
0
V
B
I
DC Current on INH Pin
mA
V
INH
V
V
DC Voltage at Pin WAKE
−42
−8
+42
WAKE
Electrostatic Discharge Voltage at Pins CANH, CANL,
(Note 3)
(Note 4)
+8
kV
ESD_IEC
V
B
and WAKE; System HBM, According to IEC 61000−4−2.
V
Electrostatic Discharge Voltage at Pins CANH, CANL,
and WAKE; Component HBM, According to JEDEC
−8
+8
kV
ESD_HBM
V
B
JESD22−A114.
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NCV7343
MAXIMUM RATINGS (continued)
Symbol
Parameter
Conditions
(Note 4)
Min
Max
Unit
V
V
V
V
Electrostatic Discharge Voltage at All Other Pins;
Component HBM, According to JEDEC JESD22−A114.
−4
+4
kV
ESD_INT
ESD_CDM
ESD_MM
TRAN
Electrostatic Discharge Voltage at All Pins;
Component CDM, According to JEDEC JESD22−C101.
−750
−200
+750
+200
V
V
Electrostatic Discharge Voltage at All Pins;
Component MM, According to JEDEC JESD22−A115.
(Note 5)
Voltage Transients, Pins CANH, CANL.
Test Pulses According to ISO7637−2, Class C, (Note 6)
Test pulses 1
Test pulses 2a
Test pulses 3a
Test pulses 3b
−100
−
−
+75
−
V
V
V
V
V
−150
−
+100
40
Voltage Transients, Pin V , According to ISO7637−2
Test pulse 5
Load dump
−
B
Latch−up
Static Latch−up at All Pins, According to JEDEC JESD78
Maximum Junction Temperature
Storage Temperature
−
150
+160
+150
mA
°C
T
T
−40
−55
J
°C
STG
MSL
Moisture Sensitivity Level
SOIC−14
2
1
DFNW14
T
SLD
Peak Soldering Temperature (Note 7)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. Equivalent to discharging a 150 pF capacitor through a 330 W resistor, referenced to GND. WAKE pin stressed through an external series
resistor 3.3 kW and with 10 nF capacitor on the module input. VB pin decoupled with 100 nF during stressing. Results were verified by an
external test house.
4. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor.
5. Equivalent to discharging a 200 pF capacitor through a 10 W resistor and 0.75 mH coil.
6. Results were verified by an external test house.
7. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC−14 (Note 8)
Thermal Resistance Junction−to−Air, (Note 9)
Thermal Resistance Junction−to−Air, (Note 10)
R
R
100
63
K/W
q
JA_1
JA_2
q
Thermal Characteristics, DFNW14 (Note 8)
Thermal Resistance Junction−to−Air, (Note 9)
Thermal Resistance Junction−to−Air, (Note 10)
R
R
115
65
K/W
q
JA_1
JA_2
q
8. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
9. Test board according to EIA/JEDEC Standard JESD51−3 (1S0P PCB), signal layer with 10% trace coverage.
10.Test board according to EIA/JEDEC Standard JESD51−7 (2S2P PCB), signal layers with 10% trace coverage.
RECOMMENDED OPERATING RANGES
Symbol
Parameter
Conditions
Min
5.0
4.5
2.8
−36
0
Max
18
Unit
V
V
V
V
V
V
V
V
Supply Voltage, Pin V
Supply Voltage, Pin V
Supply Voltage, Pin V
B
B
5.5
5.5
36
V
CC
CC
IO
V
IO
DC Voltage at Pins CANH and CANL
DC Voltage at Pins TxD, STBN, and EN
DC Voltage at Pins RxD and ERRN
DC Voltage at Pin INH
V
CAN
5.5
V
DIG_IN
DIG_OUT
INH
0
V
IO
V
0
V
B
V
I
DC Current on Pin INH
−1
0
mA
INH
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NCV7343
RECOMMENDED OPERATING RANGES (continued)
Symbol Parameter
Conditions
Min
−42
−40
Max
Unit
V
V
WAKE
DC Voltage at Pin WAKE
Junction Temperature
V
B
T
J
150
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 5.5 V; V = 2.8 V to 5.5 V; V = 5.0 V to 18 V; for typical values T = 25°C, for
CC
IO
B
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive current flow into the respective pin)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
SUPPLY (Pin V
)
CC
V
Power Supply Voltage
Supply Current
4.5
−
−
47
3.2
1.0
−
5.5
61
V
CC
I
Normal mode, Dominant, V
= 0 V
mA
mA
mA
mA
CC
TxD
Normal mode, Recessive, V
Silent mode, Recessive
= V
−
6.2
3.2
103
TxD
IO
−
Normal mode, Dominant, V
= 0 V,
−
TxD
one of bus wires shorted (Note 11)
−3 V ≤ V , V ≤ +18 V
CANH
CANL
I
Supply Current
in Low−power Modes
(Standby or Sleep Mode)
Standby or Sleep mode, V = 5 V
B CC J
−
11
20
mA
CC_LP
CC
V > V , T ≤ 100°C (Note 11)
V
V
Undervoltage Detection
Threshold
3.5
3.8
4.3
V
uv_VCC
Undervoltage Threshold
Hysteresis
−
120
−
mV
uvh_VCC
V
IO
SUPPLY VOLTAGE (Pin V )
IO
V
I
Supply Voltage on Pin V
2.8
−
−
5.5
300
7.0
4.0
V
IO
IO
Normal−power Mode Supply
Current
Normal or Silent mode; V
Normal or Silent mode, V
= 0 V
110
1.5
1.0
mA
mA
mA
IO
TxD
= V
−
TxD
IO
I
Low−power Mode Supply Current
Standby or Sleep mode; V
= V
IO;
−
IO_LP
TxD
T ≤ 100°C (Note 11)
J
V
V
Undervoltage Detection
Threshold
2.0
2.2
2.8
V
uv_VIO
Undervoltage Threshold
Hysteresis
−
280
−
mV
uvh_VIO
V
B
SUPPLY VOLTAGE (Pin V )
B
V
B
Supply Voltage on Pin V
5.0
−
18
V
B
I
Normal−power Mode Supply
Normal and Silent mode
Standby mode
−
3.5
7.0
mA
B
Current
I
Low−power Mode Supply Current
−
−
3.5
13
7.0
20
mA
mA
B_LP
V
V
J
= V ;
WAKE
B
T ≤ 100°C (Note 11)
B
= 5 V to 14 V
Sleep mode
V
V
V
= V
= 0 V,
VCC
WAKE
VIO
B
= V ;
= 5 V to 14 V
B
T ≤ 100°C (Note 11)
J
I
Sum of Low−power Mode Supply
Current to Battery and V Pin
Sleep and Standby Mode
−
14
23
mA
B_LP_VB&VCC
V
V
= V
= 5 V,
CC
VCC
B
VIO
= 5 V to 14 V
T ≤ 100°C (Note 11)
J
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NCV7343
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 5.5 V; V = 2.8 V to 5.5 V; V = 5.0 V to 18 V; for typical values T = 25°C, for
CC
IO
B
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive current flow into the respective pin) (continued)
Symbol Parameter
SUPPLY VOLTAGE (Pin V )
Conditions
Min
Typ
Max
Unit
V
B
B
V
V
V
Undervoltage Detection
V
V
falling
rising
3.7
3.9
4.1
4.4
4.5
4.9
V
V
uvd_VB
B
Threshold
Undervoltage Recovery
Threshold
uvr_VB
uvh_VB
B
Undervoltage Threshold
Hysteresis
100
300
400
mV
TRANSMITTER DATA INPUT (PIN TxD)
V
V
High−level Input Voltage
Low−level Input Voltage
High−level Input Current
Pull−up Resistor
Output recessive
Output dominant
2.0
−
−
−
−
V
IH
IL
0.8
+5.0
50
V
I
IH
V
TxD
= V
IO
−5.0
10
0
mA
kW
mA
pF
R
25
0
PU
I
Leakage Current
V
TxD
= 5.5 V, V = 0 V
−1.0
−
+1.0
10
LEAK
IO
C
Input Capacitance
(Note 11)
5
i
RECEIVER DATA OUTPUT (Pin RxD)
I
I
High−level Output Current
Low−level Output Current
V
V
= V − 0.4 V
−8.0
−3.0
−1.0
mA
mA
OH
OL
RxD
IO
= 0.4 V
1.0
6.0
12
RxD
TRANSMITTER MODE SELECT (Pin STBN, EN)
V
V
High−level Input Voltage
Low−level Input Voltage
Pull−down Resistor
Low−level Input Current
Leakage Current
Standby mode
Normal mode
2.0
−
−
−
−
V
IH
IL
0.8
V
R
300
−1.0
−1.0
−
650
0
1000
+1.0
+1.0
10
kW
mA
mA
pF
PD
I
I
V
V
= 0 V
IL
LEAK
STBN
= 5.5 V, V = V = V = 0 V
0
STBN
B
CC
IO
C
Input Capacitance
(Note 11)
5
i
ERROR SIGNALING (Pin ERRN)
I
I
High Level Output Current
Low Level Output Current
V
V
= V − 0.4 V
−100
−50
−10
mA
OH
OL
ERRN
IO
= 0.4 V
0.1
0.5
1.0
mA
ERRN
LOCAL WAKE−UP INPUT (Pin WAKE)
V
V
High−level Input Voltage
Low−level Input Voltage
High−level Input Current
Standby or Sleep
Standby or Sleep
V
− 2
−
−
−
−
V
V
IH
IL
B
−
V − 4
B
I
IH
V
WAKE
V
WAKE
= V − 2 V;
−11
−3.0
mA
B
= High for t ≥ t
wake_filt
(Pull−up active)
I
IL
Low−level Input Current
V
V
= V − 4 V;
3.0
−
11
mA
WAKE
WAKE
B
= Low for t ≥ t
wake_filt
(Pull−down active)
INHIBIT OUTPUT (Pin INH)
V
OH
High−level Output Voltage
I
= −1 mA
V
−
V
−
V −
B
0.1
V
INH
B
B
0.6
0.27
I
Leakage Current
Sleep or Power−off mode, V
= 0 V
−5
0
+5
mA
LEAK
INH
CAN TRANSMITTER (Pins CANH and CANL)
V
Dominant Output Voltage at Pin
CANH
Normal mode; V
= Low;
LT
2.75
3.65
4.5
V
o(dom)(CANH)
TxD
t < t
; 45 W ≤ R ≤ 65 W
dom(TxD)
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NCV7343
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 5.5 V; V = 2.8 V to 5.5 V; V = 5.0 V to 18 V; for typical values T = 25°C, for
CC
IO
B
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive current flow into the respective pin) (continued)
Symbol Parameter
CAN TRANSMITTER (Pins CANH and CANL)
Conditions
Min
Typ
Max
Unit
V
Dominant Output Voltage at Pin
CANL
Normal mode; V
= Low;
LT
0.5
2.0
1.35
2.5
2.25
3.0
V
V
o(dom)(CANL)
TxD
t < t
; 45 W ≤ R ≤ 65 W
dom(TxD)
V
o(rec)
Recessive Output Voltage at Pins
CANH and CANL
Normal or Silent mode;
= High
V
TxD
TxD
or V
= Low and t > t
;
dom(TxD)
no load
V
Recessive Output Voltage at Pins
CANH and CANL
Standby or Sleep mode;
no load
−0.1
1.5
0
2.3
2.3
−
+0.1
3.0
V
V
o(off)
V
Differential Dominant Output
Voltage
Normal mode; V
= Low;
LT
o(dom)(diff)
TxD
t < t
; 50 W ≤ R ≤ 65 W
dom(TxD)
(V
CANH
− V
)
CANL
V
Normal mode; V
= Low;
LT
1.4
3.3
V
o(dom)(diff)_E
TxD
t < t
; 45 W ≤ R ≤ 70 W
dom(TxD)
V
Normal mode; V
= Low;
1.5
5.0
V
o(dom)(diff)_ARB
TxD
t < t
; R = 2 240 W
dom(TxD)
LT
V
Differential Recessive Output
Voltage
Normal or Silent mode;
= High
TxD
no load
−50
0
+50
mV
o(rec)(diff)
V
TxD
(V
− V
)
or V
= Low and t > t
;
CANH
CANL
dom(TxD)
V
Differential Recessive Output
Voltage
Standby or Sleep Mode;
no load
−0.2
0
+0.2
V
o(off)(diff)
(V
− V
)
CANH
CANL
V
Driver Output Voltage Symmetry
= V + V
TxD = square wave up to 1 MHz;
C = 4.7 nF
ST
0.9
−100
−2.0
−3.0
1.0
−70
+70
−
1.1
V
CC
o(sym)
V
o(sym)
CANH
CANL
I
I
I
Short Circuit Output Current
at Pin CANH in Dominant
Normal mode; V
= Low,
CANH
+2.0
+100
+3.0
mA
mA
mA
o(sc)(CANH)
o(sc)(CANL)
o(sc)(rec)
TxD
t < t
; −3 V ≤ V
≤ +18 V
≤ +36 V
dom(TxD)
Short Circuit Output Current
at Pin CANL in Dominant
Normal mode; V
= Low,
CANL
TxD
t < t
; −3 V ≤ V
dom(TxD)
Short Circuit Output Current
at Pins CANH and CANL
in Recessive
Normal or Silent mode;
−27 V < V , V
< +32 V
CANL
CANH
CAN RECEIVER (Pins CANH and CANL)
I
Input Leakage Current
−5.0
−5.0
−3.0
0
0
−
+5.0
+5.0
+0.5
0 W < R(V to GND) < 1 MW
mA
mA
V
LEAK(off)
CC
= V
V
= 5 V
CANH
CANL
V
V
= V = V = 0 V
B
CC
IO
= V
= 5 V
CANH
CANL
V
V
V
V
Differential Input Voltage Range
Recessive State
Normal or Silent mode;
i(rec)(diff)_NM
i(rec)(diff)_LP
i(dom)(diff)_NM
i(dom)(diff)_LP
−12 V ≤ V
, V
≤ +12 V;
CANH
CANL
no load
Standby or Sleep mode;
−3.0
0.9
−
−
−
+0.4
8.0
V
V
V
−12 V ≤ V
, V
CANL
≤ +12 V;
CANH
no load
Differential Input Voltage Range
Dominant State
Normal or Silent mode;
−12 V ≤ V
, V
≤ +12 V;
CANH
CANL
no load
Standby or Sleep mode;
1.05
8.0
−12 V ≤ V
, V
CANL
≤ +12 V;
CANH
no load
www.onsemi.com
8
NCV7343
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 5.5 V; V = 2.8 V to 5.5 V; V = 5.0 V to 18 V; for typical values T = 25°C, for
CC
IO
B
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive current flow into the respective pin) (continued)
Symbol Parameter
CAN RECEIVER (Pins CANH and CANL)
Conditions
Min
Typ
Max
Unit
V
Differential Receiver Threshold
Voltage
Normal or Silent mode;
0.5
−
0.9
V
i(th)(diff)_NM
−12 V ≤ V
, V
≤ +12 V;
CANH
CANL
no load
V
Normal or Silent mode; Extended,
0.4
0.4
−
−
1.0
V
V
i(th)(diff)_NM_E
−30 V ≤ V
, V
CANL
≤ +35 V;
CANH
no load
V
Standby or Sleep mode;
1.05
i(th)(diff)_LP
−12 V ≤ V
, V
CANL
≤ +12 V;
CANH
no load
R
R
Common−mode Input Resistance
−2 V ≤ V
, V ≤ +7 V
CANL
6.0
−
50
+1
kW
i(cm)
CANH
at Pins CANH and CANL
Matching between Pin CANH
and Pin CANL Common Mode
Input Resistance
V
CANH
= V = +5 V
CANL
−1
0
%
i(cm)(m)
R
C
C
Differential Input Resistance
R
= R
CANH
+ R
i(cm)(CANL)
CANL
12
−
−
100
20
kW
pF
pF
i(diff)
i
i(diff)
i(cm)(CANH)
−2 V ≤ V
, V
≤ +7 V
Input Capacitance at Pins CANH
and CANL
V
= High; (Note 11)
7.5
TxD
TxD
Differential Input Capacitance
V
= High; (Note 11)
−
3.75
10
i(diff)
THERMAL SHUTDOWN
T
Shutdown Junction Temperature
Junction temperature rising
160
2.0
180
3.5
200
6.0
°C
°C
JSD
T
Shutdown Junction Temperature
Hysteresis
JSD_HYST
TIMING CHARACTERISTICS (see Figure 18)
t
Propagation Delay TxD to Bus
Active
Normal mode (Note 12, Figure 16)
Normal mode (Note 12, Figure 16)
−
75
−
ns
d(TxD−BUSon)
t
t
t
t
t
Propagation Delay TxD to Bus
Inactive
−
−
85
25
−
−
ns
ns
ns
ns
ns
d(TxD−BUSoff)
d(BUSon−RxD)
d(BUSoff−RxD)
pd_dr
Propagation Delay Bus Active
to RxD
Normal or Silent mode (Note 12,
Figure 16)
Propagation Delay Bus Inactive
to RxD
Normal or Silent mode (Note 12,
Figure 16)
−
35
−
Propagation Delay TxD to RxD
Dominant to Recessive Transition
Normal mode (Note 12, Figure 17)
50
50
100
120
170
170
t
= 200 ns / 500 ns / 1000 ns
bit(TxD)
Propagation Delay TxD to RxD
Recessive to Dominant Transition
Normal mode (Note 12, Figure 17)
= 200 ns / 500 ns / 1000 ns
pd_rd
t
bit(TxD)
t
t
TxD Dominant Timeout
Normal mode; V
= Low
TxD
1.2
7.0
2.4
6.0
50
ms
dom(TxD)
Transmitter Activation Time after
Clearing TxD Dominant Timeout
Flag Condition
Normal mode
−
ms
en(TxD)
t
t
Bus Dominant Timeout
Normal or Silent mode; bus dominant
Normal or Silent mode
1.5
14
2.8
6.5
50
ms
dom(BUS)
Receiver Activation Time after
Clearing Bus Dominant Timeout
Flag Condition
−
ms
en(RxD)
t
Bit Time on RxD Pin
t
t
= 500 ns (Note 12, Figure 17)
= 200 ns (Note 12, Figure 17)
400
120
−
−
550
220
ns
ns
bit(RxD)
bit(TxD)
bit(TxD)
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9
NCV7343
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 5.5 V; V = 2.8 V to 5.5 V; V = 5.0 V to 18 V; for typical values T = 25°C, for
CC
IO
B
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive current flow into the respective pin) (continued)
Symbol Parameter
TIMING CHARACTERISTICS (see Figure 18)
Conditions
Min
Typ
Max
Unit
t
Bit Time on Bus Pins
t
t
t
t
= 500 ns (Note 12, Figure 17)
= 200 ns (Note 12, Figure 17)
= 500 ns (Note 12, Figure 17)
= 200 ns (Note 12, Figure 17)
435
155
−65
−45
−
−
−
−
−
−
530
210
+40
+15
100
ns
ns
ns
ns
ms
bit(Vi(diff))
bit(TxD)
bit(TxD)
bit(TxD)
bit(TxD)
(CANH − CANL)
Dt
Receiver Timing Symmetry
rec
Dt
t
− t
rec = bit(RxD) bit(Vi(diff))
t
t
t
t
t
t
t
Power−on Event Device Sartup
Time
V
> V
to Standby Mode Delay
d(startup)
B
uvr_VB
(Figure 5)
Operating Mode Change Delay
Mode change by STBN/EN pins
(Figure 7 and Figure 8)
7.0
10
16
16
22
−
50
38
ms
ms
ms
ms
ms
ms
d(mode)
Mode change after local wake−up
(Figure 12 and Figure 13)
d(mode_wake)
d(mode_wup)
h(mode)
Mode change after remote wake−up
(Figure 14)
10
63
Operating Mode Change Hold
Time
Figure 7 and Figure 8
3.0
3.0
40
50
Go−to−Sleep Mode Entering Hold
Time
STBN = Low, EN = High (Figure 9)
−
50
h(go−to−sleep)
d(wake_startup)
Power−on Event WAKE Pin
Enable Time
Standby mode to WAKE input enable
delay (Power−on event only)
(Figure 5)
70
200
t
t
WAKE Pin Input Filter Time
Standby or Sleep mode
(Figure 12 and Figure 13)
5.0
3.0
21
60
13
ms
ms
wake_filt
Wake−up Flag Set Delay Time
Local wake−up detected, Standby
or Sleep mode
(Figure 12 and Figure 13)
5.5
d(wake_flg)
t
Bus Wake−up Pattern Filter Time
Standby or Sleep mode (Figure 14)
Standby or Sleep mode (Figure 14)
0.15
−
1.8
ms
wup_filt
(Short)
t
t
Bus Wake−up Pattern Timeout
Wake−up Flag Set Delay Time
1.0
3.0
2.0
11
5.0
38
ms
wup_to
Remote wake−up detected, Standby
or Sleep mode (Figure 14)
ms
d(wup_flg)
t
Transmitter Deactivation Time
V
< V
or V < V
uvd_VIO
−
0.7
25
−
ms
ms
uv_det
uv_rec
CC
uvd_VCC
IO
after V or V Undervoltage
(Figure 6)
CC
IO
Condition Detection
t
Transmitter Activation Time
V
CC
> V
and V > V
uvr_VIO
14
75
uvr_VCC
IO
after V and V Undervoltage
(Figure 6)
CC
IO
Condition Removal
t
t
t
t
V
Undervoltage Detection
V
V
V
V
< V
to V UV flag set
100
100
160
160
0.6
0.6
400
400
1.3
1.3
ms
ms
ms
ms
uvd_VCC
uvd_VIO
uvr_VCC
uvr_VIO
CC
CC
uvd_VCC
CC
Timeout
V
IO
Undervoltage Detection
< V
to V UV flag set
IO
uvd_VIO IO
Timeout
V
CC
Undervoltage Recovery
> V
to V UV flag reset
0.35
0.35
CC
IO
uvr_VCC
CC
Timeout
V
IO
Undervoltage Recovery
> V
to V UV flag reset
uvr_VIO IO
Timeout
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Values based on design and characterization, not tested in production.
12.C = 100 pF, C not present, C = 15 pF
LT
ST
RxD
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10
NCV7343
FUNCTIONAL DESCRIPTION
POWER SUPPLY
NCV7343
implements
three
power
supply
In Normal mode, the transmitter is disabled t
after
uv_det
inputs – battery supply input V , CAN transceiver supply
V
CC
or V voltage falls below respective undervoltage
B
IO
input V and digital IOs supply input V .
detection thresholds. The transmitter is re−enabled t
CC
IO
uv_rec
after both V and V voltage rises above the undervoltage
CC
IO
VB Supply Pin
recovery thresholds (Figure 6).
undervoltage is detected if V supply voltage falls
V is the main supply pin of the NCV7343. The NCV7343
B
V
B
B
proceeds from Power−off mode to Standby mode as soon as
below undervoltage detection threshold, V
. V
uvd_VB
B
the V supply is available. This supply input is used
B
undervoltage recovery is detected if V supply voltage rises
B
to provide the minimum power required for the operation
in case of absence of the remaining supplies. Typically this
is the only active supply in a low−power Sleep mode
providing power supply to the low−power wake−up
detector.
above the undervoltage recovery threshold, V
uvr_VB.
V
CC
undervoltage flag is set if V supply voltage is
CC
lower than V
for longer than V
undervoltage
uv_VCC
CC
detection time t . V
uvd_VCC
undervoltage recovery is
CC
detected and the flag is reset if V supply voltage is higher
CC
than V
for longer than V undervoltage recovery
uv_VCC
CC
VCC Supply Pin
time t
.
uvr_VCC
V
CC
pin is the CAN transceiver main supply input
Similarly, V undervoltage flag is set if V supply
voltage is lower than V
IO
IO
in Normal and Silent mode.
for longer than V
uv_VIO
IO
undervoltage detection time t
. V undervoltage
VIO Supply Pin
uvd_VIO
IO
Digital pins interfacing with the microcontroller have
recovery is detected and the flag is reset if V supply
IO
a separate IO supply. The V pin should be connected
voltage is higher than V for longer than V
uv_VIO IO
IO
to microcontroller supply pin. By using V supply pin
undervoltage recovery time t
.
IO
uvr_VIO
shared with microcontroller the IO levels between
microcontroller and transceiver are properly adjusted. See
Figure 1.
Both
V
and
V
undervoltage flags and
CC
IO
the undervoltage detection timers are also reset after local
or remote wake−up detection event or STBN pin rising edge
detection in Sleep mode.
VB
Once the V
and/or V undervoltage flag is set
CC
IO
the device changes to Sleep mode. The Sleep mode can be
left and the operation mode control by STBN and EN pin is
Vuvr_VB
re−enabled as soon as both V
and V supplies are
CC
IO
td(startup)
recovered. The operating mode control state machine is not
reset when an undervoltage condition is detected. Thus if
STBN
Sleep mode was requested by the host prior to V and/or
CC
EN
V
undervoltage condition detection and the EN pin was set
IO
td(mode)
Low in Sleep mode, the device stays in Sleep once
the undervoltage is recovered, although STBN and EN pins
are both set Low, which is otherwise considered a Standby
mode request.
Power off
Standby
Normal
INH
< tuvd_VCC/VIO
Normal mode
< tuvd_VCC/VIO
VCC
VIO
VCC or VIO
td(wake_startup)
Vuv_VCC/VIO
tuv_det
> tuv_rec
disabled
WAKE
disabled
enabled
Transmitter active
active
Figure 5. Typical Power−up Sequence
TxD
Power Supplies Monitoring
CAN
V , V
and V supply inputs are monitored by
B
CC
IO
Figure 6. Transmitter Deactivation/Activation
in Case of Undervoltage Event
undervoltage detectors with individual thresholds
and filtering times both for undervoltage detection
and undervoltage recovery.
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11
NCV7343
INH Pin
The INH output pin is a high−voltage high−side switch
to V supply. It can be used to control the V or V
disabled, CAN bus pins are left floating and the INH pin is
deactivated. The RxD pin is left High at V level. As soon
B
CC
IO
IO
external supply voltage regulators. The output is switched
high in all operating modes except for the Sleep mode.
In Sleep mode the pin is left floating (high−impedance)
which can be used to deactivate the external regulators
in order to minimize the ECU current consumption.
The INH switch is also deactivated in Power−off mode.
as the V voltage rises above battery undervoltage recovery
B
threshold V
, the device proceeds to Standby mode.
uvr_VB
Standby Mode
Standby mode is a low−power mode. In Standby mode
both the transmitter and receiver are disabled and a very
low−power differential receiver monitors the bus lines
for CAN bus activity. The bus lines are biased to ground
and supply current is reduced to a minimum.
A wake−up event can be detected either on the CAN bus
or on the WAKE pin. A valid wake−up is signaled on pins
ERRN and RxD. Pin INH remains active (pulled high) so
that the external regulators controlled by the INH pin remain
switched on.
HIGH SPEED CAN TRANSCEIVER
NCV7343 implements high−speed physical layer
CAN FD transceiver compatible with ISO11898−2:2016,
implementing following optional features or alternatives:
• Extended bus load range
• Transmit dominant timeout, long
• Support of bit rates up to 5 Mbit/s
• Low−power modes with wake−up via wake−up pattern,
Short CAN activity filter time and long wake−up
timeout
• Normal Bus biasing
Standby mode is entered automatically upon Power−on
event (V > V
). It can be requested during normal
B
uvr_VB
operation by setting STBN and EN pins to Low. Standby
mode is also entered if wake−up event is detected in Sleep
mode or if V
and V recovers after undervoltage
CC
IO
condition has been detected.
OPERATIONS MODES
NCV7343 provides five operation modes. These modes
are either selectable through pins STBN and EN or entered
automatically upon detection of specific event, such as
power−on, undervoltage of wake−up (see Figure 11). Any
mode transition is completed within a time given by
Normal Mode
In the Normal mode, the transceiver is able
to communicate via the bus lines. The signals are
transmitted and received to the CAN controller via the pins
TxD and RxD. The slopes on the bus lines outputs are
optimized to give low EME.
operating mode change delay t
.
d(mode)
The bus lines (CANH and CANL) are internally biased to
V
CC
/2.
STBN
< th(mode)
Pin INH is active (pulled high) so that the external
regulators controlled by INH pin are switched on.
Normal mode can be requested by setting STBN and EN
pin to High.
EN
td(mode)
Standby
Normal
Silent Mode
In Silent mode, the CAN transmitter is disabled.
The CAN controller can still receive data from the bus via
RxD Pin as the receiver part remains active. Equally
to Normal mode, the bus lines (CANH and CANL) are
Figure 7. Operating Mode Transition Timing
STBN
EN
> th(mode)
internally biased to V /2. Pin INH is also active (pulled
CC
high).
Silent mode can be requested by setting STBN to High
and EN pin to Low.
td(mode)
Standby
Figure 8. Operating Mode Transition Timing
td(mode)
Silent
Normal
Go−to−Sleep Mode
Go−to−sleep mode is an intermediate state used to put
the transceiver into Sleep mode in a controlled way.
Go−to−sleep mode is entered when EN is set to High
and STBN pin is set to Low. If the logical state of pins EN
and STBN is kept unchanged for a minimum period of
Power−off
This virtual mode is entered as soon as the V voltage falls
B
t
and neither a wake−up nor a power−up event
h(go−to−sleep)
below the battery undervoltage detection threshold V
uvd_VB
occur during this time, the transceiver enters Sleep mode.
and a V undervoltage condition is detected. The internal
B
logic is reset. The transceiver and wake−up detection is
www.onsemi.com
12
NCV7343
While in Go−to−sleep mode, the transceiver behaves
the mode change via STBN is requested by the host or
identically to Standby mode.
a valid wake−up is detected.
Sleep Mode
Operating Modes Transition
Sleep mode is
a low−power mode in which
the consumption is further reduced compared to Standby
mode. Sleep mode can be entered via Go−to−sleep mode or
> th(go−to−sleep)
STBN
is forced in case an undervoltage on either V and/or V
occurs for longer than the undervoltage detection time.
CC
IO
EN
The transceiver behaves identically to Standby mode, but
the INH Pin is deactivated (left floating) and the external
regulators controlled by INH pin are switched off. In this
th(go−to−sleep)
Normal
td(mode)
Go−to−Sleep
Sleep
way, the V consumption is reduced to a minimum.
B
The device will leave sleep mode either after a wake−up
event (in case of a CAN bus wake−up or wake−up via
WAKE pin) or by changing STBN pin from Low to High (as
Figure 9. Correct Sleep Mode Entry Sequence
long as an undervoltage on V is not detected).
IO
STBN
EN
In case the Sleep mode was forced due to undervoltage
detection, the device enters Standby mode and the operation
mode control by STBN and EN pin is re−enabled as soon as
both V and V supplies are recovered.
CC
IO
< th(go−to−sleep)
Normal
td(mode)
In case the Sleep mode was requested by the host, any
potential and/or undervoltage detection
V
CC
V
IO
Standby
and subsequent undervoltage recovery does not lead to any
mode change and the device stays in Sleep mode until
Figure 10. Sleep Mode Entry Sequence Interrupted
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13
NCV7343
Power off
VB UV detected
VB < Vuvd_VB
CAN: off (no bias)
Wake−up: Disabled
INH = OFF
Any active
mode
1
RxD: High(VIO)
VB > Vuvr_VB
Standby mode
STBN = L, EN = L
STBN = L
EN = L
STBN = L
EN = L
CAN: off (weak GND)
Wake−up: Enabled4
INH = High
STBN = H
EN = H
STBN = H
EN = L
ERRN, RxD: wake−up
(STBN = L
5
EN = H)
no wake flag
Normal mode
STBN = H, EN = H
CAN: Normal (VCC/2)
INH = High
Silent mode
STBN = H, EN = L
STBN = H
EN = L
CAN: Receive only (V /2)
CC
INH = High
STBN = H
EN = H
ERRN: Local wake−up /
ERRN: Power−on /
Bus failure
Local failure
STBN = L
EN = L
Go−to−Sleep mode
STBN = L, EN = H
STBN = H
EN = H
STBN = H
EN = L
CAN: off (weak GND)
Wake−up: Enabled
INH = High
(STBN = L
(STBN = L
5
5
EN = H)
EN = H)
ERRN, RxD: wake−up
no wake flag
no wake flag
Sleep mode
STBN = L, EN = L or H
STBN L³H
EN = H
STBN L³H
EN = L
and VIO OK
and VIO OK
CAN: off (weak GND)
Wake−up: Enabled
INH = OFF
VCC UV detected
and/or
Wake−up detected
or
( VCC OK and VIO OK )3
Any active
mode
ERRN, RxD: wake−up2
VIO UV detected
Notes:
1 Highest priority
2 If VIO is active
3 In case Sleep mode was requested by host command VCC /VIO undervoltage recovery event does not lead to mode change
4 Upon Power−on event, Local wake−up detection is enabled after td(wake_startup)
5 For t > th(go−to−sleep)
VCC UV detected: VCC < Vuv_VCC for t > tuvd_VCC
VCC OK: VCC > Vuv_VCC for t > tuvr_VCC
;
;
VIO UV detected: VIO < Vuv_VIO for t > tuvd_VIO
VIO OK:
VIO > Vuv_VIO for t > tuvr_VIO
Figure 11. Operation Modes
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14
NCV7343
WAKE−UP
w twake_filt
A Wake−up flag is set if Local wake−up via WAKE pin
(positive or negative edge) is detected or Remote wake−up
via bus (wake−up pattern) is detected. If the Wake−up flag
is set in Sleep mode, the device changes to Standby mode.
Undervoltage detection flags are cleared and
the corresponding timers are restarted upon detection
of valid wake−up event.
WAKE
VIH(WAKE)
twake_filt td(mode_wake)
td(wake_flg)
> twake_filt
< twake_filt
WAKE pin pull−down
RxD, ERRN
pull−up
Wake−up
Standby
The Wake−up flag is cleared when entering Normal mode
or when V or V undervoltage is detected.
CC
IO
Wake−up flag is signaled on ERRN and RxD pin
in Standby, Go−to−sleep and Sleep mode provided the V
IO
supply voltage is available.
Sleep mode
Local Wake−up (WAKE pin)
INH
The high−voltage input WAKE is monitored
in Low−power Standby mode, Go−to−Sleep and Sleep
mode. If a negative or positive edge is recognized on WAKE
pin, a local wake−up is detected and a Wake−up flag is set.
In order to avoid false wake−ups, the negative or positive
edge must be followed by stable Low or High level,
Figure 13. Local Wake−up Behavior (Positive Edge)
Remote Wake−up (Wake−up pattern)
When a valid wake−up pattern (phase in order
dominant – recessive – dominant) is detected during
the Standby, Go−to−Sleep or Sleep mode a Wake−up flag is
set. Minimum length of each phase is t
Figure 14.
respectively, longer than t
for the wake−up to be
wake_filt
valid. The WAKE pin can be used, for example, for switch
or contact monitoring.
– see
wup_filt
Internal pull−up and pull−down current sources are
connected to WAKE pin in order to minimize the risk
of parasitic toggling. The current source polarity is
automatically selected based on the WAKE input signal
polarity – when the voltage on WAKE stays stable High
Pattern must be received within t
as valid wake−up otherwise internal logic is reset.
to be recognized
wup_to
w twup_filt w twup_filtw twup_filt
(Low) for longer than t
, the internal current source
wake_filt
is switched to pull−up (pull−down).
Negative edge detection is depicted in Figure 12. Positive
edge detection is depicted in Figure 13.
CANH
CANL
Besides, in order to be able to distinguish between local
and remote wake−up events, a Wake−up source indication
flag is set if local wake−up is detected. Wake−up source
indication flag is reset upon Normal mode leaving. Wake−up
source indication flag is signaled on ERRN pin in Normal
mode, before first four consecutive dominant symbols are
sent.
V
i(dom)(diff)_LP (1.05 V)
Vi(diff)
Vi(rec)(diff)_LP (400 mV)
twup_filt
td(mode_wup)
< twup_to
twup_flg
RxD, ERRN
INH
Wake−up
Standby
w twake_filt
WAKE
Sleep
VIL(WAKE)
twake_filt
td(mode_wake)
> twake_filt
WAKE pin pull−up
RxD, ERRN
< twake_filt
td(wake_flg)
pull−down
Wake−up
Standby
Figure 14. Remote Wake−up Behavior
(Wake−up Pattern)
Sleep mode
INH
Figure 12. Local Wake−up Behavior (Negative Edge)
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15
NCV7343
FAILURE DETECTION
Local Failures
A Local failure flag is set if any of the flowing flags are
set:
The transmitter can be re−enabled when either Normal
mode is entered or bus dominant symbol is received on
the bus, driving RxD Low, while TxD is High.
• TxD Dominant Timeout
• Bus Dominant Timeout
• Short−TxD to RxD
Overtemperature Detection
An overtemperature flag is set if the junction temperature
exceeds a shutdown temperature T . The thermal
protection circuit protects the IC from damage by switching
off the transmitter if the overtemperature is detected.
Because the transmitter dissipates most of the power,
the power dissipation and temperature of the IC is expected
to be reduced once the transmitter is disabled. All other IC
functions continue to operate.
JSD
• Overtemperature Detection
The local failure flag is signaled on ERRN pin in Silent
mode entered from Normal mode. The flag is cleared if all
of the mentioned flags are cleared.
TxD Dominant Timeout
The overtemperature flag is reset when the junction
temperature decreases below the thermal shutdown
threshold and either Normal mode is entered or bus
dominant symbol is received on the bus while TxD is High.
The transmitter can be re−enabled when the flag is
cleared.
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state if pin TxD
is forced permanently low. The timer is triggered by
a negative edge on pin TxD in Normal mode. If the duration
of the Low level on pin TxD exceeds the internal timer value
t
, the TxD dominant timeout flag is set.
dom(TxD)
The thermal protection circuit is particularly needed
in case of a bus line short circuit.
The transmitter is disabled, driving the bus into a recessive
state, as long as the TxD dominant flag is set.
The timer and the flag is reset when TxD is High and either
Normal mode is entered or bus dominant is received
in Normal mode. The transmitter is reactivated latest
CAN Bus Failure Flag
The transmitter of the NCV7343 device allows for bus
failure detection. During dominant bit transmission
in Normal mode, a short of the CANH or CANL line to
t
after TxD dominant flag has been cleared.
en(TxD)
The minimum value of TxD dominant timeout time
limits the minimum bit rate to 17 kbps.
supply or ground (V , V or GND) is internally detected.
B
CC
t
dom(TxD)
If the short circuit condition lasts for four consecutive TxD
dominant symbol requests, an internal bus failure flag is set.
Minimum dominant symbol length for correct bus failure
detection is 4 ms. The flag is visible on ERRN pin in Normal
mode. The transmission and reception circuitry continues
to function.
The bus failure flag is reset when Normal mode is entered
or if four consecutive TxD dominant symbols are sent while
no bus short circuit condition is present.
Bus Dominant Timeout
Bus dominant timeout timer is started when CAN bus
changes from recessive to dominant state. If the dominant
state on the bus is kept for longer time than t
,
dom(BUS)
the RxD pin is released to High level and a Bus dominant
timeout flag is set. No other action is taken upon Bus
dominant timeout condition detection. The timer
and the flag is reset when CAN bus changes back from
dominant to recessive state in Normal or Silent mode, or
when low−power mode is entered. The receiver is
INTERNAL FLAGS AND THEIR SIGNALING
The transceiver keeps several internal flags reflecting
conditions and events encountered during its operation.
Some flags influence the transceiver operation mode.
Beside the undervoltage flags all others can be read by
the host microcontroller on pin ERRN. Pin ERRN signals
internal flags depending on the operation mode of
the transceiver. An overview of the flags and their visibility
on pin ERRN is given in following table. Because the ERRN
pin uses negative logic, it will be pulled low if
the corresponding signaled flag is set and will be pulled high
if the signaled flag is reset.
reactivated latest t
cleared.
This feature prevents potential bus dominant clamping
condition from blocking the communication controller
transmit task.
after Bus dominant flag has been
en(RxD)
Short – TxD to RxD
If a short between TxD and RxD signal lines is detected
during data transmission. Short TxD to RxD flag is set
and the transmitter is disabled.
www.onsemi.com
16
NCV7343
INTERNAL FLAGS AND THEIR VISIBILITY
Internal Flag
or V Undervoltage
Set Conditions
Reset Conditions
or (V > V for t > t
uvr_VCC
Visibility on ERRN Pin
V
V
V
< V
for t > t
No
No
CC
IO
CC
IO
uv_VCC
uv_VIO
uvd_VCC
uvd_VIO
CC
uv_VCC
< V
for t > t
and V > V
for t > t
)
IO
uv_VIO
uvr_VIO
or power−on flag is set
or wake flag is set
or STBN is changed to High
V
B
Undervoltage
V
V
< V
> V
V > V
B uvr_VB
B
uvd_VB
Power−on
Normal mode is entered
In Silent mode entered
from other than Normal mode
B
uvr_VB
Wake−up
Local or remote wake−up is
detected
Normal mode is entered or
In Standby, Go−to−sleep or
V
and/or V flag is set
Sleep mode (if V is active)
CC
IO
IO
Wake−up Source indication
Local wake−up is detected
Normal mode is left
In Normal mode before first four
consecutive dominant symbols
are sent
TxD Dominant Timeout
TxD is Low for longer than
dom(TxD)
operation mode
TxD is High and either Normal
See Local Failure flag
t
while in Normal
mode is entered or bus dominant
is received (RxD Low) in Normal
mode
Bus Dominant Timeout
TxD Shorted to RxD
Overtemperature
Bus is dominant for longer than
dom(BUS)
Bus is recessive in Normal
or Silent mode, or Low−power
mode is entered
t
TxD is shorted to RxD during
data transmission
TxD is High and either Normal
mode is entered or bus dominant
is received (RxD Low)
Junction temperature T > T
Junction temperature T < T
J JSD
J
JSD
and either Normal mode is en-
tered or bus dominant is received
while TxD is High
Local Failure
Bus Failure
Any of the following flags is set
• TxD dominant timeout
• Bus dominant timeout
• TxD shorted to RxD
All of the following flags are reset In Silent mode entered from
• TxD dominant timeout
• Bus dominant timeout
• TxD shorted to RxD
• Overtemperature detection
Normal mode
• Overtemperature detection
Bus failure detected during four
consecutive TxD dominant
symbol requests
Normal mode is entered
In Normal mode after first four
consecutive dominant symbols
are sent
or four consecutive TxD
dominant symbols sent while no
bus failure condition present
STBN
EN
th(go−to−sleep)
4th dominant
symbol requested
Power−on
Wake−up
Events
Power off
ERRN
Standby
Silent
Normal
Silent
GTS
Wake−up
Wake−up
Sleep
High
High
Wake−up
Wake−up
Power−on
Local Wake−up Bus Failure Local Failure
Data Data
RxD
Data
Figure 15. ERRN and RxD Pin Signaling
www.onsemi.com
17
NCV7343
FAIL SAFE
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Undervoltage on supply pins prevents the chip from
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 19). Pin TxD is pulled high and pins STBN and EN
are pulled low internally should the input become
disconnected. Digital pins, TxD, STBN and EN will be
sending data on the bus when there is not enough V supply
floating, preventing reverse supply should the V supply be
CC
IO
voltage to build required bus differential voltage, or when
removed. RxD and ERRN have forward diode to V
supply.
IO
V
IO
supply voltage is low and thus the digital input or output
signals might be interpreted falsely. After supply is
recovered TxD pin must be first released to High to allow
sending dominant bits again.
MEASUREMENT SETUPS AND DEFINITIONS
recessive
dominant
recessive
TxD1
0.7 × VIO
0.3 × VIO
CANH
CANL
900 mV
Vi(diff)
=
* VCANL
VCANH
500 mV
0.7 × VIO
RxD
0.3 × VIO
td(BUSon−RXD)
td(TxD−BUSon)
1 TxD Edge length below 10 ns
td(TxD−BUSoff)
td(BUSoff−RXD)
Figure 16. Transceiver Timing Diagram − Propagation Delays
0.7 × VIO
TxD1
0.3 × VIO
0.3 × VIO
5 × tbit(TxD)
tbit(TxD)
tpd_rd
Vi(diff)
VCANH
=
* V
900 mV
CANL
500 mV
tbit(Vi(diff))
0.7 × VIO
RxD
0.3 × VIO
1 TxD Edge length below 10 ns
tpd_dr
tbit(RxD)
Figure 17. Transceiver Timing Diagram − Loop Delay and Recessive Bit Time
www.onsemi.com
18
NCV7343
+5 V
+14 V
22 μF
+3.3 V
22 μF
100 nF
100 nF
100 nF
VIO VCC INH VB
22 μF
5
3
7
10
STBN
EN
WAKE
14
6
9
CANH
13
RLT/2
ERRN
TxD
8
CLT
NCV7343
1
CST
100 pF
RLT/2
RxD
4
12
CANL
2x 30 Ω
2
15 pF
GND
Figure 18. Test Circuit for Timing Characteristics
+5 V
+14 V
22 μF
+3.3 V
22 μF
100 nF
100 nF
100 nF
VIO VCC INH VB
22 μF
5
7
3
10
STBN
EN
WAKE
14
6
9
CANH
13
1 nF
1 nF
ERRN
TxD
8
NCV7343
Test Pulse
Generator
1
RxD
4
12
CANL
2
15 pF
GND
Figure 19. Test Circuit for Automotive Transients
www.onsemi.com
19
NCV7343
ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE
ISO 11898−2:2016 Specification
NCV7343 Datasheet
Symbol
Parameter
Notation
DOMINANT OUTPUT CHARACTERISTICS
Single Ended Voltage on CAN_H
V
V
o(dom)(CANH)
CAN_H
Single Ended Voltage on CAN_L
V
CAN_L
V
o(dom)(CANL)
Differential Voltage on Normal Bus Load
Differential Voltage on Effective Resistance During Arbitration
Differential Voltage on Extended Bus Load Range
DRIVER SYMMETRY
V
Diff
V
Diff
V
Diff
V
o(dom)(diff)
o(dom)(diff)_ARB
V
V
o(dom)(diff)_E
Driver Symmetry
V
SYM
V
o(sym)
DRIVER OUTPUT CURRENT
Absolute Current on CAN_H
I
I
o(SC)(CANH)
CAN_H
Absolute Current on CAN_L
I
I
CAN_L
o(SC)(CANL)
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE
Single Ended Output Voltage on CAN_H
Single Ended Output Voltage on CAN_L
Differential Output Voltage
V
V
o(rec)
CAN_H
V
V
o(rec)
CAN_L
V
Diff
V
o(rec)(diff)
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE
Single Ended Output Voltage on CAN_H
Single Ended Output Voltage on CAN_L
Differential Output Voltage
V
V
o(off)
CAN_H
V
V
o(off)
CAN_L
V
Diff
V
o(off)(diff)
TRANSMIT DOMINANT TIMEOUT
Transmit Dominant Timeout
t
t
t
dom(TxD)
dom
Transmit Dominant Timeout, Short
NA
dom
STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE
Recessive State Differential Input Voltage Range
Dominant State Differential Input Voltage Range
STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING INACTIVE
Recessive State Differential Input Voltage Range
Dominant State Differential Input Voltage Range
RECEIVER INPUT RESISTANCE
V
V
V
Diff
i(rec)(diff)_NM
V
Diff
i(dom)(diff)_NM
V
V
V
Diff
i(rec)(diff)_LP
V
Diff
i(dom)(diff)_LP
Differential Internal Resistance
R
R
R
Diff
i(diff)
Single Ended Internal Resistance
R
CAN_H
i(cm)
R
CAN_L
RECEIVER INPUT RESISTANCE MATCHING
Matching of Internal Resistance
LOOP DELAY REQUIREMENT
Loop Delay
m
R
i(cm)(m)
R
t
t
t
Loop
pd_rd
pd_dr
DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 1 Mbit/s AND UP TO 2 Mbit/s
Transmitted Recessive Bit Width @ 2 Mbit/s
Received Recessive Bit Width @ 2 Mbit/s
Receiver Timing Symmetry @ 2 Mbit/s
t
t
bit(Vi(diff))
Bit(Bus)
t
t
bit(RxD)
Bit(RXD)
Dt
Rec
Dt
rec
www.onsemi.com
20
NCV7343
ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE (continued)
Parameter
Notation
Symbol
DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 2 Mbit/s AND UP TO 5 Mbit/s
Transmitted Recessive Bit Width @ 5 Mbit/s
Received Recessive Bit Width @ 5 Mbit/s
Receiver Timing Symmetry @ 5 Mbit/s
t
t
bit(Vi(diff))
Bit(Bus)
t
t
bit(RxD)
Bit(RXD)
Dt
Rec
Dt
rec
MAXIMUM RATINGS OF V
, V AND V
CAN_L Diff
CAN_H
Maximum Rating V
V
Diff
V
Diff
Diff
General Maximum Rating V
and V
V
V
CAN
V
CAN
CAN_H
CAN_L
CAN_H
CAN_L
V
Optional: Extended Maximum Rating V
and V
V
NA
CAN_H
CAN_L
CAN_H
CAN_L
V
MAXIMUM LEAKAGE CURRENTS ON CAN_H and CAN_L, UNPOWERED
Leakage Current on CAN_H, CAN_L
I
I
CAN_H
CAN_L
LEAK(off)
I
BUS BIASING CONTROL TIMINGS
CAN Activity Filter Time, Long
t
t
NA
Filter
CAN Activity Filter Time, Short
t
wup_filt
Filter
Wake−up Timeout, Short
t
NA
Wake
Wake
Wake−up Timeout, Long
t
t
wup_to
Timeout for Bus Inactivity (Required for Selective Wake−up Implementation Only)
Bus Bias Reaction Time (Required for Selective Wake−up Implementation Only)
t
NA
Silence
t
NA
Bias
Table 1. ORDERING INFORMATION
†
Part Number
NCV7343D20R2G
Description
Package
Shipping
CAN FD Transceiver, High
Speed, Low Power, with
SOIC−14
(Pb−free)
3000 / Tape & Reel
WAKE, INH and V Pin
IO
NCV7343MW0R2G
CAN FD Transceiver, High
Speed, Low Power, with
DFNW14
Wettable Flank
(Pb−free)
5000 / Tape & Reel
WAKE, INH and V Pin
IO
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
21
NCV7343
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
22
NCV7343
PACKAGE DIMENSIONS
DFNW14 4.5x3, 0.65P
CASE 507AC
ISSUE D
NOTES:
L3
L3
A B
D
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMESNION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURES TO AID IN FILLET FOR-
MATION ON THE LEADS DURING MOUNTING.
L
L
DETAIL A
PIN ONE
ALTERNATE
REFERENCE
CONSTRUCTION
E
EXPOSED
COPPER
MILLIMETERS
TOP VIEW
DIM MIN
NOM
0.85
−−−
0.20 REF
−−−
0.30
4.50
4.20
3.00
1.60
MAX
0.90
0.05
A
A1
A3
A4
b
D
D2
E
0.80
−−−
A
DETAIL B
0.10
C
C
PLATING
A1
A4
0.10
0.25
4.40
4.13
2.90
1.53
−−−
0.35
4.60
4.27
3.10
1.67
C
C
DETAIL B
A4
0.08
SEATING
PLANE
NOTE 4
A3
C
SIDE VIEW
E2
e
0.65 BSC
0.30 REF
0.40
DETAIL A
K
L
L3
0.35
0.00
0.45
0.10
D2
L3
0.05
PLATED
SURFACES
14X
L
1
7
SECTION C−C
RECOMMENDED
SOLDERING FOOTPRINT*
E2
14X
0.75
4.35
4.23
8
14
K
14
8
7
14X b
0.10
0.05
e
M
M
C A B
3.60 1.75
C NOTE 3
BOTTOM VIEW
PACKAGE
OUTLINE
1
0.65
PITCH
14X
0.33
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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