NCV7451MW0R2G_技术文档

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System Basis Chip with

CAN FD, LDO Regulator and

Wake-up Comparator

NCV7451

The system basis chip (SBC) NCV7451 integrates +5 V / 250 mA

LDO regulator with a high−speed CAN FD transceiver and local

wake−up comparator, directly controlled by dedicated pins.

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Features

• 5 V 2% / 250 mA LDO

♦ Current Limitation with Fold−back

♦ Output Voltage Monitoring

1

• One High−Speed CAN FD Transceiver

♦ Compliant to ISO11898−2:2016

♦ CAN FD Timing Specified up to 5 Mbps

♦ Current Limitation, Reverse Current Protected

♦ TxDC Timeout

DFNW14 4.5x3, 0.65P

CASE 507AC

MARKING DIAGRAM

• Local Wake−up Comparator

NCV

7451

ALYW

G

♦ Integrated Pull−up / Pull−down Current Source

• Very Low Current Quiescent Consumption

• Window Watchdog

• Direct Control

• Thermal Shutdown Protection

• AEC−Q100 Qualified and PPAP Capable

• Wettable Flank Package for Enhanced Optical Inspection

• This is a Pb−Free Device

NCV7451

A

L

Y

W

G

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Typical Applications

• Automotive

• Industrial Networks

PIN CONNECTIONS

1

2

3

4

5

6

7

14

13

12

11

10

9

TxDC

GND

CAN_EN

CANH

CANL

VR1

RxDC

RSTN

WD_EN

WDI

GND

VS

WAKE

WAKE_OUT

8

ORDERING INFORMATION

†

Device

Package

Shipping

NCV7451MW0R2G

DFNW14

(Pb−Free)

5000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

1

Publication Order Number:

February, 2021 − Rev. 0

NCV7451/D

NCV7451

Battery

Cbuf

100n

connection

VS

References,

oscillator

VR1

5 V / 250 mA

4u7

VDD

RESET

RSTN

WD_EN

WDI

Watchdog

VS

WAKE_OUT

WAKE

Local

wakeup

3k3

10n

MCU

VR1

CAN_EN

TxDC

CANH

CANL

Termination,

Protection

CAN

CAN bus

CAN

RxDC

NCV7451

GND

Figure 1. Simplified Application Diagram

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2

NCV7451

VS1

10

3

5

VR1

UV

OV

Internal

supply

RSTN

ref

References

LDO

Regulator

VR1

Thermal

Monitoring

Oscillator

6

7

Watchdog

WD_EN

WDI

VR1

9

WAKE

8

Filt.

WAKE_OUT

CAN_EN

ref

Local

Wakeup

14

VR1

13

12

1

4

Tx

Timeout

TxDC

RxDC

CANH

CANL

VR1

CAN

2

11

GND

Figure 2. Block Diagram

PIN FUNCTION DESCRIPTION

No.

Pin Type

(LV = Low Voltage; HV = High Voltage)

LV digital input; internal pull−up

Ground connection

Pin Name

TxDC

Description

1

2

CAN transmitter data input

GND

Ground supply (all GND pins have to be connected externally)

Output of the 5 V / 250 mA low−drop regulator

CAN receiver data output

3

VR1

LV supply output

4

RxDC

RSTN

WD_EN

WDI

LV digital output; push−pull

LV digital output; open drain; internal pull−up

LV digital input; internal pull−up current

LV digital input; internal pull−down

LV digital output

5

Reset signal to the MCU

6

Watchdog enable input

7

Watchdog trigger input

8

WAKE_OUT

WAKE

VS

WAKE pin output (inverted WAKE level)

WAKE pin

9

HV input; pull−up/−down current

HV supply input

10

11

12

13

14

Main supply input

GND

Ground connection

Ground supply (all GND pins have to be connected externally)

CANL line of the CAN bus

CANL

CANH

CAN_EN

EP

CAN bus interface

CANH line of the CAN bus

LV digital input; internal pull−down

Exposed pad

CAN transceiver enable input

Substrate (has to be connected to all GND pins externally)

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3

NCV7451

MAXIMUM RATINGS

Symbol

Rating

Min

Max

Unit

V

VS

DC Power Supply Voltage (Note 1)

LDO Supply pin output voltage

*0.3

+40

VR1

6 or VS+0.3

(whichever

is lower)

V

VdigIO

DC voltage on digital pins (CAN_EN, WD_EN, WDI, RSTN, RxDC, TxDC,

WAKE_OUT)

*0.3

VR1+0.3

V

WAKE

CANH, CANL

Vdiff

DC WAKE pin Input Voltage

*40

*8

+40

+8

V

DC voltage on pin CANH and CANL

Differential DC voltage between any two pins (incl. CANH and CANL)

V

V_ESD

ESD capability, Device HBM, according to

AEC−Q100−002 (EIA/JESD22−A114); (Note 2)

Pins VS, CANH,

CANL, WAKE

kV

HBM

Other pins

*4

−200

+4

V_ESD

ESD capability; MM, according to AEC−Q100−003 (EIA/JESD22−A115);

+200

V

MM

all pins

ESD capability; CDM, according to AEC−Q100−011 (EIA/JESD22−C101);

*750

−6

+750

+6

CDM

all pins

V_ESD

ESD capability; System HBM, according to IEC61000−4−2;

pins VS, CANH, CANL, WAKE; (Note 3)

kV

IEC

V_SCHAF

Voltage transients, Test pulses According to

ISO7637*2, Class D;

Test pulse 1

Test pulse 2a

Test pulse 3a

Test pulse 3b

*100

−

V

+75

−

pins VS, CANH, CANL, WAKE

*150

−

V

+100

+150

260

V

Tj

Junction Temperature Range

Storage Temperature Range

Peak Soldering Temperature (Note 4)

Moisture Sensitivity Level

*40

*55

−

°C

−

Tstg

Tsld

MSL

1

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

2. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor

3. Equivalent to discharging a 150 pF capacitor through a 330 W resistor; WAKE pin stressed through an external series resistor of 3.3 kW and

with 10 nF capacitor on the module input, VS pin decoupled with 100 nF.

4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

THERMAL CHARACTERISTICS

Symbol

Rating

Value

Unit

R

Thermal Characteristics,

°C/W

θJA

Thermal Resistance, Junction−to−Air (Note 5)

Thermal Reference, Junction−to−Air (Note 6)

77

52

R

Thermal Characteristics,

Thermal Resistance, Junction−to−Case

°C/W

ψJC

7

5. Value based on test board according to JESD51−3 standard, signal layer with 10% trace coverage.

6. Value based on test board according to JESD51−7 standard, signal layers with 20% trace coverage, inner planes with 90% coverage.

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4

NCV7451

RECOMMENDED OPERATING RANGES

Symbol

Rating

Min

5.0

6.0

4.9

0

Max

28

Unit

V

VS

Functional supply voltage

Supply voltage for valid parameter specification

VR1 regulator output voltage

18

V

VR1

I(VR1)

5.1

250

VR1

VS

V

VR1 regulator output current (including CAN transceiver consumption)

Digital inputs/outputs voltage

mA

V

VdigIO

0

WAKE

WAKE input voltage

0

V

CANH, CANL

CAN bus pins voltage

−40

40

V

T

J

Junction Temperature

150

125

°C

T

A

Ambient Temperature

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS

6 V v VS v 18 V; −40°C v Tj v 150°C; 4.75 V v VR1 v 5.25 V; R = 60 W, C = 100 pF, C not used, unless otherwise specified.

LT

ST

Symbol

VS SUPPLY

VS_PORH

VS_PORL

Is_off

Parameter

Conditions

Min

Typ

Max

Unit

VS POR threshold

VS rising

VS falling

3.4

2.0

−

4.1

3.5

35

V

VS POR threshold

VS consumption, low−power

VS = 14 V, VR1 on (not loaded), WAKE float-

ing, CAN bus recessive,

28

mA

CAN_EN = Low, WD_EN = Low, Tj v 85°C

Is_act

VS consumption, active

VS = 14 V, VR1 on (loaded by 100 mA, not

included in Is_act), WAKE floating, CAN bus

recessive,

−

3.7

5.0

mA

CAN_EN = High, WD_EN = High, TxDC = High

VR1 VOLTAGE REGULATOR

V_VR1

Regulator output voltage

0 mA v I(VR1) v 250 mA (including internal

CAN consumption), 6 V v VS v 28 V

Maximum VR1 overload current,

VR1 > RES_VR1

4.9

250

125

5.0

5.1

650

325

V

Ilim_VR1

Regulator current limitation

Regulator short current

Dropout Voltage

−

mA

V

Ishort_VR1

Vdrop_VR1

Maximum VR1 short current, VR1 < RES_VR1

1/2 x

Ilim_VR1

I(VR1) = 100 mA, VS = 5 V

I(VR1) = 100 mA, VS = 4.5 V

I(VR1) = 50 mA, VS = 4.5 V

1 mA v I(VR1) v 100 mA

I(VR1) v 100 mA

−

0.2

0.1

−

0.4

0.5

0.4

50

40

−

Loadreg_VR1

Linereg_VR1

Cload_VR1

Load Regulation

Line Regulation

VR1 load capacity

−50

−40

1.0

mV

mF

−

ESR < 200 mW, ceramic capacitor recommend-

ed

4.7

RES_VR1

RES_hyst_VR1

tfilt_RES_VR1

OV_VR1

VR1 Reset threshold

VR1 voltage decreasing

4.3

0.05

−

4.5

0.1

15

4.7

0.2

−

V

VR1 Reset threshold hysteresis

VR1 undervoltage filter time

VR1 overvoltage threshold

ms

V

VR1 voltage increasing / decreasing

5.5

−

6.0

−

OV_hyst_VR1

VR1 overvoltage threshold

hysteresis

0.06

V

tfilt_OV_VR1

toff_VR1

VR1 overvoltage filter time

VR1 off time after TSD

−

15

−

ms

1.0

s

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5

NCV7451

ELECTRICAL CHARACTERISTICS (continued)

6 V v VS v 18 V; −40°C v Tj v 150°C; 4.75 V v VR1 v 5.25 V; R = 60 W, C = 100 pF, C not used, unless otherwise specified.

LT

ST

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VR1 VOLTAGE REGULATOR

Is_add_VR1

VS consumption adder of VR1 (Note 7)

−

0.01 x

I(VR1)

−

A

CAN BUS LINES (Pins CANH and CANL)

I

Recessive output current at

pins CANH and CANL

CAN enabled;

−27 V < V

−5.0

2.0

−

0

5.0

3.0

0.1

0.2

mA

V

o(rec)

, V

< 32 V

CANH

CANL

I

LI

Input leakage current

0 W v R(VR1 to GND) < 1 MW;

V

CANH

= V

= 5 V

CANH

V

Recessive output voltage at

pin CANH

CAN enabled; TxDC = High; no load

CAN disabled; no load

2.5

0

o(rec)(CANH)

V

Recessive output voltage at

pin CANL

2.0

V

o(rec)(CANL)

V

Recessive output voltage at

pin CANH

−0.1

−0.2

V

o(off)(CANH)

V

Recessive output voltage at

pin CANL

CAN disabled; no load

0

V

o(off)(CANL)

V

Differential bus output volt-

age in off mode

CAN disabled; no load

0

V

o(off)(diff)

(V

CANH

− V

)

CANL

V

Dominant output voltage at

pin CANH

CAN enabled; 50 Ω v R v 65 Ω;

2.75

0.5

0.9

1.5

3.5

1.5

−

4.5

2.25

1.1

V

o(dom)(CANH)

LT

TxDC = Low; t < t

dom(TxDC)

V

Dominant output voltage at

pin CANL

CAN enabled; 50 Ω v R v 65 Ω;

o(dom)(CANL)

LT

TxDC = Low; t < t

dom(TxDC)

V

o(sym)

Driver output voltage

CAN enabled; C = 4.7 nF; TxDC driven by

VR1

V

ST

symmetry (V

+ V

)

square wave up to 1 MHz

CANH

CANL

V

Differential bus output

voltage (V − V

CAN enabled; 45 Ω v R v 65 Ω;

2.25

−

3.0

o(dom)(diff)

LT

)

CANL

TxDC = Low; dominant

CANH

V

Differential bus output

voltage during arbitration

(V − V

CAN enabled; R = 2240 Ω;

5.0

V

o(dom)(diff)_arb

LT

TxDC = Low; dominant; (Note 7)

)

CANL

CANH

V

Differential bus output

voltage (V − V

CAN enabled; no load;

TxDC

−50

0

50

mV

mA

o(rec)(diff)

)

V

= High; recessive

CANH

CANL

I

Short circuit output current at

pin CANH

CAN enabled; TxDC = Low;

= −3 V

o(sc)(CANH)

V

CANH

−100

−70

−40

2.0

−3 V v V

v 18 V

CANH

I

Short circuit output current at

pin CANL

CAN enabled; TxDC = Low;

mA

o(sc)(CANL)

V

CANL

= 36 V

40

−1.5

70

100

−3 V v V

v 18 V

CANL

V

Differential input voltage

range

recessive state

CAN enabled; no load;

3.0

−3.0

0.9

−

0.5

0.4

8.0

0.9

1.05

V

i(rec)(diff)_NM

−12 V v V

, V

CANL

v 12 V

CANH

V

CAN disabled; no load;

i(rec)(diff)_LP

−12 V v V

, V

CANL

CANH

V

Differential input voltage

range

dominant state

CAN enabled; no load;

i(dom)(diff)_NM

−12 V v V

, V

CANL

CANH

V

CAN disabled; no load;

1.05

0.5

i(dom)(diff)_ LP

−12 V v V

, V

CANL

CANH

V

Differential receiver threshold

voltage in normal mode

CAN enabled;

i(diff)(th)_NM

−12 V v V

, V

CANH

CANL

V

Differential receiver threshold

voltage in wake−up−detec-

tion mode

CAN disabled;

0.4

i(diff)(th)_LP

−12 V v V

, V

CANL

v 12 V

CANH

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6

NCV7451

ELECTRICAL CHARACTERISTICS (continued)

6 V v VS v 18 V; −40°C v Tj v 150°C; 4.75 V v VR1 v 5.25 V; R = 60 W, C = 100 pF, C not used, unless otherwise specified.

LT

ST

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CAN BUS LINES (Pins CANH and CANL)

R

Common−mode input resis-

−2 V v V

, V

v 7 V

15

25

0

37

kΩ

%

i(cm)(CANH)

CANH

CANL

tance at pin CANH

R

Common−mode input resis-

tance at pin CANL

, V

CANL

i(cm)(CANL)

CANH

R

Matching between pin CANH

and pin CANL common

mode input resistance

V

CANH

= V = 5 V

CANL

−1.0

1.0

i(cm)(m)

R

Differential input resistance

25

50

75

20

kΩ

i(diff)

C

Input capacitance at pin

CANH

TxDC = High; (Note 7)

−

7.5

pF

i(CANH)

C

Input capacitance at pin

CANL

−

7.5

20

10

pF

i(CANL)

C

Differential input capacitance

3.75

i(diff)

TIMING CHARACTERISTICS (see Figure 3, Figure 4 and Figure 5)

t

Propagation delay TxDC to

bus active

CAN enabled

−

65

90

−

ns

d(TxDC−BUSon)

d(TxDC−BUSoff)

d(BUSon−RxDC)

d(BUSoff−RxDC)

t

Propagation delay TxDC to

bus inactive

t

Propagation delay bus active

to RxDC

−

60

−

Propagation delay bus inac-

tive to RxDC

−

65

−

t

Propagation delay TxDC to

RxDC dominant to recessive

transition

50

100

170

pd_dr

pd_rd

t

Propagation delay TxDC to

RxDC recessive to dominant

transition

CAN enabled

50

120

170

ns

t

Dominant time for wake−up

CAN_EN = Low

0.15

0.5

−

1.8

6.0

ms

wake_filt

via bus

t

Delay to flag wake event (re-

cessive to dominant transi-

tions)

CAN_EN = Low; Valid bus wake−up event

dwakerd

dwakedr

t

Delay to flag wake event

(dominant to recessive tran-

sitions)

0.5

−

6.0

ms

t

Bus time for wake−up time-

CAN_EN = Low

1.0

−

10

ms

wake_to

out

t

TxDC dominant time for time-

out

CAN_EN = High; TxDC = Low

dom(TxDC)

t

Bit time on RxDC pin

t

= 500 ns

= 200 ns

400

120

−

550

220

ns

Bit(RxDC)

Bit(TxDC)

t

Bit time on bus pins

(CANH − CANL)

t

= 500 ns

= 200 ns

435

155

530

210

ns

Bit(Vi(diff))

Bit(TxDC)

−

t

Receiver timing symmetry

Dt

Rec

t

= 500 ns

= 200 ns

−65

−45

−

40

15

ns

Bit(TxDC)

Dt

Rec

= t

t

^Bit(RxDC)− ^{Bit(Vi(diff))}

Bit(TxDC)

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7

NCV7451

ELECTRICAL CHARACTERISTICS (continued)

6 V v VS v 18 V; −40°C v Tj v 150°C; 4.75 V v VR1 v 5.25 V; R = 60 W, C = 100 pF, C not used, unless otherwise specified.

LT

ST

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TIMING CHARACTERISTICS (see Figure 3, Figure 4 and Figure 5)

t

Mode change delay from

wake−up detection to normal

mode

CAN_EN = Low → High

−

25

47

ms

d(LP−NM)

WATCHDOG TIMING

twd_acc

Watchdog timing accuracy

Timeout watchdog period

−15

−

15

74

%

t_wd_TO

After WD_EN low → high transition or RSTN

pulse

56

65

ms

t_wd_CW

Window watchdog closed win-

dow

5.1

6.0

6.9

ms

t_wd_OW

t_WDI

Window watchdog open window

85

100

115

ms

Minimum WDI pulse width ac-

cepted as a watchdog service

6.0

−

ms

WAKE INPUT

Vth_WAKE

Vhys_WAKE

tfilt_WAKE

WAKE pin threshold

2.0

0.1

10

−

4.0

0.7

50

V

WAKE pin threshold hysteresis

WAKE wake−up filter time

Pull−up current on WAKE pin

ms

mA

Ipu_WAKE

Ipd_WAKE

V(WAKE) = 4 V

−11

3.0

−3.0

11

Pull−down current on WAKE pin V(WAKE) = 2 V

DIGITAL OUTPUTS, RxDC, WAKE_OUT

IoutL_pinx

IoutH_pinx

Low−level output driving current pinx is logical Low, forced V(pinx) = 0.4 V

1.0

6.0

12

mA

High−level output driving cur-

pinx is logical High,

forced V(pinx) = VR1 − 0.4 V

−8.0

−3.0

−1.0

rent

DIGITAL OUTPUT RSTN

IoutL_RSTN

Low−level output driving current RSTN is active (logical Low),

2.0

5.0

12

mA

V

forced V(RSTN) = 0.4 V

VoutL_RSTN

Low−level output voltage,

low VR1/VS

VR1 > 4.7 V, I(RSTN) = 0.6 mA

−

0.2

0.4

19

VR1 > 2 V, VS < VR1, I(RSTN) = 0.1 mA

VR1 = 0 V, VS > 2 V, I(RSTN) = 0.2 mA

−

0.2

Rpu_RSTN

t_RSTN

Internal pull−up resistor to VR1

5.0

6.8

10.0

8.0

kW

Reset pulse length after VR1

undervoltage or watchdog

failure

9.2

DIGITAL INPUTS TxDC, CAN_EN, WD_EN, WDI

VinL_pinx

Low−level input voltage (logical

−

0.8

V

“Low”)

VinH_pinx

High−level input voltage (logical

“High”)

2.0

−

Vin_hys_pinx

Rpu_pinx

Input voltage hysteresis

−

200

100

−

mV

Internal pull−up resistor to VR1;

pin TxDC

55

185

kΩ

Rpd_pinx

Ipu_WD_EN

tper_pu_WDEN

Internal pull−down resistor to

55

50

−

100

610

185

200

−

kΩ

mA

ms

ground; pins CAN_EN, WDI

Internal pull−up current to VR1, V(WD_EN) = 0 V, pull−up current source active

pin WD_EN

WD_EN pull−up current source WD_EN = CAN_EN = Low

activation period

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8

NCV7451

ELECTRICAL CHARACTERISTICS (continued)

6 V v VS v 18 V; −40°C v Tj v 150°C; 4.75 V v VR1 v 5.25 V; R = 60 W, C = 100 pF, C not used, unless otherwise specified.

LT

ST

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DIGITAL INPUTS TxDC, CAN_EN, WD_EN, WDI

ton_pu_WDEN

WD_EN pull−up current source WD_EN = CAN_EN = Low

activation on−time

−

5.0

−

ms

THERMAL PROTECTION

Tsd

Thermal shutdown level

Temperature increasing

Temperature decreasing

155

165

10

175

°C

Tsd_hys

Thermal shutdown level hys-

teresis

−

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Not tested in production, guaranteed by design.

6-18 V

100 nF

VS

VR1

CANH

4.7 uF

R_LT/2

C_LT

NCV7451

CAN_EN

TxDC

C

100 pF

R_LT/2

RxDC

CANL

R

_LT= 60 W

15 pF

GND

Figure 3. Test Circuit for CAN Timing Characteristics

recessive

dominant

recessive

TxDC¹

0.7 × VR1

0.3 × VR1

CANH

CANL

900 mV

V_i(diff)

=

V_CANH− V_CANL

500 mV

0.7 × VR1

RxDC

0.3 × VR1

t_{d(TxDC−BUSon)}

t_{d(BUSon−RxDC)}t_{d(TxDC−BUSoff)}

t_{d(BUSoff−RxDC)}

¹TxDC Edge length below 10 ns

Figure 4. CAN Transceiver Timing Diagram − Propagation Delays

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9

NCV7451

0.7 × VR1

TxDC¹

0.3 × VR1

5 × t_bit(TxDC)

t_bit(TxDC)

t_{pd_rd}

V_i(diff)

=

900 mV

V_CANH− V_CANL

500 mV

t_{bit(Vi(diff))}

0.7 × VR1

RxDC

0.3 × VR1

¹TxDC Edge length below 10 ns

t_{pd_dr}

t_bit(RxDC)

Figure 5. CAN Transceiver Timing Diagram − Loop Delay and Recessive Bit Time

Reset or previous

WD service

nominal t _wd_TO

Timeout WD

period

Safe trigger of timeout WD

WD expired

t_wd_TO

tolerance

nominal t_wd_OW

t_wd_trig

nominal t _wd_CW

Closed window

(WD trigger would be too early )

Window WD

period

Safe trigger of window WD

t_wd_CW

tolerance

t_wd_OW

tolerance

recommended

WD trigger

Figure 6. Watchdog Modes Timing

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10

NCV7451

FUNCTIONAL DESCRIPTION

Supply Concept

level drops below this level for longer than

tfilt_RES_VR1, a reset towards the MCU is

generated through the RSTN pin and the CAN

transceiver is disabled.

The device has one battery supply pin VS, supplying the

VR1 regulator and logic control. The supply line has to be

properly decoupled by filtering capacitors close to the

device pin.

♦ VR1 Overvoltage Reset Comparator – the VR1

regulator output is compared with an overvoltage

level OV_VR1. If the VR1 level crosses this

threshold for longer than tfilt_OV_VR1, a reset

towards the MCU is generated through the RSTN

pin and the CAN transceiver is disabled.

♦ Temperature (see Figure 14)

VR1 Low−drop Regulator

VR1 is a low−drop output regulator providing 5 V voltage

derived from the VS main supply. It is able to deliver up to

250 mA and is primarily intended to supply the on−chip

CAN transceiver, the application microcontroller unit

(MCU) and related 5 V loads (e.g. its own MCU−related

digital inputs/outputs). An external capacitor needs to be

connected on VR1 pin in order to ensure the regulator’s

stability and to filter the disturbances caused by the

connected loads.

V(VR1)

V_VR1

RES_hys_VR1

RES_VR1

VR1 voltage supplies all the digital low−voltage

input/output pins.

The protection and monitoring of the VR1 regulator

consist of the following features:

♦ VR1 Current Limitation – the two−level current

limitation controlled by VR1 reset comparator to

reduce the power dissipation in case of shorts to

ground by the current fold−back (see Figure 7)

♦ VR1 Reset Comparator – the VR1 regulator output

is compared with a reset level RES_VR1. If the VR1

Ishort _VR1

Ilim_VR1

I(VR1)

Figure 7. VR1 Current Fold−back

V(VS)

V(VR1)

OV_VR1

V_VR1

RES_VR1

Vdrop_VR1

VS_PORH

VS_PORL

<tfilt_OV_VR1

<tfilt_RES_VR1

tfilt_RES_VR1

t_RSTN

RSTN

t_RSTN

Off

Reset

Normal functionality

Reset

Normal Rst

Off

Mode

Figure 8. VS1 and VR1 Monitoring

CAN Transceiver

In order to prevent a faulty node from blocking the bus

traffic, the maximum length of the transmitted dominant

The SBC contains one high−speed CAN transceiver

compliant with ISO11898−2:2016. The transceiver consists

of the following sub−blocks: transmitter, receiver, and

wake−up detector.

If enabled (CAN_EN = High), the CAN transceiver is

ready to provide the full−speed interface between the bus

and a CAN controller connected on pins RxDC (received

data) and TxDC (data to transmit).

symbol is limited by a time−out counter to t

. In

dom(TxDC)

case the TxDC Low signal exceeds the timeout value, the

transmitter returns automatically to the recessive state. The

transmission is again de−blocked when TxDC pin returns to

high (recessive) state.

If the CAN block is disabled (CAN_EN = Low) or RSTN

pin active (Low) due to failed watchdog service or VR1

www.onsemi.com

11

NCV7451

undervoltage / overvoltage, the CAN transceiver is in its

• if the WAKE level stays Low for longer than

tfilt_WAKE, an internal pull−down current source is

connected to WAKE pin

wake−up detection state. Logical level on TxDC is ignored

and pin RxDC is kept high until a CAN bus wake−up is

detected. The CAN bus wake−up corresponds to a pattern

consisting of dominant – recessive – dominant symbols of

at least t

each. The RxDC starts following the CAN

wake_filt

bus afterwards. The pattern must be received within t

wake_to

Vth_WAKE

Vhys_WAKE

to be recognized as a valid wake−up event, otherwise

internal wake−up logic is reset.

WAKE

Voltage

EN_CAN

tfilt_WAKE

t_{wake_filt}

WAKE

_OUT

Current

souce

CANH

CANL

Pull-down

Pull-up

Pull-down

Figure 10. WAKE Pin Functionality

< t_{wake_to}

t_dwakerd

Watchdog

RxDC

The on−chip watchdog requires that the MCU software

“triggers” or “services” the watchdog in a specified time

frame. A correct watchdog service consists of high−to−low

transition on the WDI input. The watchdog timer re−starts

immediately after a successful trigger is received.

After any Reset event (power−up, watchdog failure, VR1

under−/overvoltage, thermal shutdown) or watchdog enable

(WD_EN = Low → High), the watchdog always starts in a

timeout mode. The MCU software must serve the watchdog

any time before the time−out expiration. After the watchdog

is triggered for the first time, it starts working in a window

mode operation: the watchdog time is split to two distinct

parts – a closed window, where the watchdog may not be

triggered, is followed by an open window where the MCU

must send a valid watchdog trigger (see Figure 12).

Figure 9. CAN Wake−up Pattern

WAKE Comparator

WAKE pin is a high−voltage input typically used to

monitor an external contact or switch. The inverted logical

level on pin WAKE can be polled via WAKE_OUT output

push−pull pin.

A stable logical level of the WAKE signal is ensured even

without an external connection:

• if the WAKE level is High for longer than tfilt_WAKE,

an internal pull−up current source is connected to

WAKE pin

Vs < Vs_PORL

Vs > Vs_PORH

Unpowered

Reset

No trigger

within t_wd_OW

No trigger

within

Trigger

t_wd_TO

WD_EN = high

Trigger

WD_EN = low

WD_EN = high

Closed

Open

Disabled

Timeout

Window

t_wd_CW

elapsed

Trigger

Figure 11. Watchdog Operating Modes

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12

NCV7451

WD Enable

Trigger in

Closed Window

WD_EN

WDI

Service

WDI

RSTN

Closed

Reset

win.

Closed Open Closed Open

window win. window win.

Timeout

WD status

Closed

Open

Closed

window window window window

Open

Timeout

WD status off

<t_wd_CW t_RSTN

t_wd_CW

<t_wd_TO

t_wd_CW <t_wd_OW

t_wd_trig

Figure 15. Watchdog Service during Closed Window

Figure 12. Correct Watchdog Services

The WD_EN pin has an integrated pull−up source to

enable the watchdog in case the pin is disconnected from the

application. To reduce the power consumption in the

low−power mode (watchdog and CAN disabled), the

WD_EN pull−up current source is switched on for

ton_pu_WDEN time with period of tper_pu_WDEN. The

pin state is sampled in the end of the current source

activation. Once High level is detected on the WD_EN pin,

the current source is activated permanently.

In case the watchdog is not triggered before the timeout or

open window elapses (Figure 13, Figure 14), or trigger is

sent within the closed window (Figure 15), RSTN signal is

generated and then watchdog restarted in the timeout mode

again.

WD Enable

WD_EN

WDI

Timeout elapsed

To ensure the High level is correctly detected if the pin

becomes floating, external WD_EN capacitance should stay

below 50 pF.

After the rising edge on WD_EN pin, the MCU should

wait tper_pu_WDEN before the first watchdog service.

RSTN

Closed

window

Open

win.

Reset

Timeout

off

Timeout

t_wd_TO

WD status

t_RSTN

t_wd_CW

WD_EN

sampled

WD_EN

sampled

WD_EN

sampled

WD_EN

Figure 13. Missed Watchdog in Timeout Mode

Ipu_WD_EN

Pull-up current

tper_pu_WDEN

ton_pu_WDEN

Enabled

(timeout )

Enabled

Disabled

WD status

WD_EN

WDI

Open Window elapsed

Figure 16. WD_EN Pull−up Current Source Activation

Thermal Protection

RSTN

A thermal protection circuit protects the IC from damage

by complete device de−activation if the junction

temperature exceeds a value of Tsd.

The device recovers automatically after the junction

temperature drops below Tsd level lowered by hysteresis

Tsd_hys and toff_VR1 (typ. 1 second) expires.

Closed Open

window window

Closed Open

window window

Reset

Timeout

WD status

t_wd_CW t_wd_OW t_RSTN

t_wd_CW

Figure 14. Missed Watchdog in Window Mode

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13

NCV7451

Operating Modes

The device operating modes are directly controlled by

CAN_EN input pin and failure events (see Figure 17).

POWER−UP

Cool−down

POWER OFF

VR1: starting

CAN: off

WAKE: on

Watchdog: off

RSTN: Low

VR1: off

CAN: off

WAKE: off

Watchdog: off

RSTN: Low

VR1: off

CAN: off

toff_VR1

WAKE: off

VS >

VS_PORH

Watchdog: off

RSTN: HiZ / Low (if VS>2 V)

elapsed

RES_VR1 < VR1 < OV_VR1

Tj < (Tsd – Tsd_hys)

VS <VS_PORL

Any

mode

Thermal Shutdown

RESET

VR1: on

CAN: wakeup detection

WAKE: on

VR1: off

CAN: off

WAKE: off

Watchdog: off

RSTN: Low

Watchdog: off

RSTN: Low

VR1 < RES_VR1

or

VR1 > OV_VR1

t_RSTN elapsed

Tj > Tsd

or

Correct

Watchdog failure

NORMAL

Any

mode

VR1: on

CAN: on

WAKE: on

Watchdog: per WD_EN

RSTN: High

CAN_EN = 0

CAN_EN = 1

Correct

WD service

Low−Power

VR1: on

CAN: wakeup detection

WAKE: on

Watchdog: per WD_EN

RSTN: High

OK20201015.01

Figure 17. Operating Modes Diagram

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14

NCV7451

ISO11898−2:2016 PARAMETER CROSS−REFERENCE TABLE

ISO 11898−2:2016 Specification

NCV7451 Datasheet

Symbol

Parameter

Notation

DOMINANT OUTPUT CHARACTERISTICS

Single ended voltage on CAN_H

V

o(dom)(CANH)

CAN_H

Single ended voltage on CAN_L

V

CAN_L

V

o(dom)(CANL)

Differential voltage on normal bus load

Differential voltage on effective resistance during arbitration

Differential voltage on extended bus load range (optional)

DRIVER SYMMETRY

V

Diff

V

Diff

V

Diff

V

o(dom)(diff)

V

o(dom)(diff)_arb

NA

Driver symmetry

V

SYM

V

o(sym)

DRIVER OUTPUT CURRENT

Absolute current on CAN_H

I

o(SC)(CANH)

CAN_H

Absolute current on CAN_L

I

o(SC)(CANL)

CAN_L

RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V

o(rec)(CANH)

CAN_H

V

o(rec)(CANL)

CAN_L

V

Diff

V

o(rec)(diff)

RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V

o(off)(CANH)

CAN_H

V

o(off)(CANL)

CAN_L

V

Diff

V

o(off)(dif)

TRANSMIT DOMINANT TIMEOUT

Transmit dominant timeout, long

t

dom(TxDC)

dom

Transmit dominant timeout, short

NA

dom

STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE

Recessive state differential input voltage range

Dominant state differential input voltage range

STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING INACTIVE

Recessive state differential input voltage range

Dominant state differential input voltage range

RECEIVER INPUT RESISTANCE

V

i(rec)(diff)_NM

Diff

V

Diff

i(dom)(diff)_NM

V

Diff

i(rec)(diff)_LP

V

Diff

i(dom)(diff)_LP

Differential internal resistance

R

Diff

i(diff)

R

i(cm)(CANH)

Single ended internal resistance

R

CAN_H

R

i(cm)(CANL)

CAN_L

RECEIVER INPUT RESISTANCE MATCHING

Matching a of internal resistance

IMPLEMENTATION LOOP DELAY REQUIREMENT

Loop delay

m

R

i(cm)(m)

R

t

Loop

pd_rd

t

pd_dr

DATA SIGNAL TIMING REQUIREMENTS for use with bit rates above 1 Mbit/s and up to 2 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s

Received recessive bit width @ 2 Mbit/s

Receiver timing symmetry @ 2 Mbit/s

t

Bit(Vi(diff))

Bit(Bus)

t

Bit(RxDC)

Bit(RXD)

Dt

Rec

Dt

Rec

www.onsemi.com

15

NCV7451

ISO11898−2:2016 PARAMETER CROSS−REFERENCE TABLE (continued)

ISO 11898−2:2016 Specification

NCV7451 Datasheet

Symbol

Parameter

Notation

DATA SIGNAL TIMING REQUIREMENTS for use with bit rates above 2 Mbit/s and up to 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit/s

Received recessive bit width @ 5 Mbit/s

t

Bit(Vi(diff))

Bit(Bus)

t

Bit(RxDC)

Bit(RXD)

Dt

Rec

Dt

Rec

MAXIMUM RATINGS OF V

, V AND V

CAN_L DIFF

CAN_H

Maximum rating V

V

Diff

Vdiff

Diff

General maximum rating V

and V

V

CANH

CANL

CAN_H

CAN_L

CAN_H

CAN_L

Optional: Extended maximum rating V

and V

V

NA

CAN_H

CAN_L

CAN_H

V

CAN_L

MAXIMUM LEAKAGE CURRENTS ON CAN_H AND CAN_L, UNPOWERED

Leakage current on CAN_H, CAN_L

I

,

I

LI

CAN_H

I

CAN_L

BUS BIASING CONTROL TIMINGS

CAN activity filter time, long

t

NA

Filter

CAN activity filter time, short

t

wake_filt

Filter

Optional: Wake−up timeout, short

t

NA

Wake

Optional: Wake−up timeout, long

t

wake_to

Timeout for bus inactivity (Required for selective wake−up implementation only)

Bus Bias reaction time (Required for selective wake−up implementation only)

t

NA

Silence

t

NA

Bias

www.onsemi.com

16

NCV7451

PACKAGE DIMENSIONS

DFNW14 4.5x3, 0.65P

CASE 507AC

ISSUE D

NOTES:

L3

A B

D

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMESNION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. THIS DEVICE CONTAINS WETTABLE FLANK

DESIGN FEATURES TO AID IN FILLET FOR-

MATION ON THE LEADS DURING MOUNTING.

L

DETAIL A

PIN ONE

ALTERNATE

REFERENCE

CONSTRUCTION

E

EXPOSED

COPPER

MILLIMETERS

TOP VIEW

DIM MIN

NOM

0.85

−−−

0.20 REF

−−−

0.30

4.50

4.20

3.00

1.60

MAX

0.90

0.05

A

A1

A3

A4

b

D

D2

E

E2

e

0.80

−−−

A

DETAIL B

0.10

C

PLATING

A1

A4

0.10

0.25

4.40

4.13

2.90

1.53

−−−

0.35

4.60

4.27

3.10

1.67

C

DETAIL B

A4

0.08

SEATING

PLANE

A3

NOTE 4

C

SIDE VIEW

0.65 BSC

0.30 REF

0.40

DETAIL A

K

L

L3

0.35

0.00

0.45

0.10

D2

L3

0.05

PLATED

SURFACES

14X

L

1

7

SECTION C−C

RECOMMENDED

SOLDERING FOOTPRINT*

E2

14X

0.75

4.35

4.23

8

14

K

_14Xb

0.10

0.05

e

14

8

7

M

C A B

NOTE 3

C

BOTTOM VIEW

3.60 1.75

PACKAGE

OUTLINE

1

0.65

PITCH

14X

0.33

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

17

NCV7451

ON Semiconductor and

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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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18


型号：	NCV7451MW0R2G
厂家：	ONSEMI
描述：	System Basis Chip with CAN FD, LDO Regulator and Wake-up Comparator
文件：	总19页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV7451MW0R2G [ONSEMI]

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