NCV7513FTG [ONSEMI]
FLEXMOS Hex Low−Side MOSFET Pre−Driver; FLEXMOS六角低端MOSFET预驱动器型号: | NCV7513FTG |
厂家: | ONSEMI |
描述: | FLEXMOS Hex Low−Side MOSFET Pre−Driver |
文件: | 总24页 (文件大小:245K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCV7513
FLEXMOSt Hex Low−Side
MOSFET Pre−Driver
The NCV7513 programmable six channel low−side MOSFET
pre−driver is one of a family of FLEXMOSTM automotive grade
products for driving logic−level MOSFETs. The product is
controllable by a combination of serial SPI and parallel inputs. It
features programmable fault management modes and allows
power−limiting PWM operation with programmable refresh time.
The device offers 3.3 V/5.0 V compatible inputs and the serial output
driver can be powered from either 3.3 V or 5.0 V. Power−on reset
provides controlled powerup and two enable inputs allow all outputs
to be simultaneously disabled.
Each channel independently monitors its external MOSFET’s
drain voltage for fault conditions. Shorted load fault detection
thresholds are fully programmable using an externally programmed
reference voltage and a combination of four discrete internal ratio
values. The ratio values are SPI selectable and allow different
detection thresholds for each group of three output channels.
Fault information for each channel is 2−bit encoded by fault type
and is available through SPI communication. Fault recovery
operation for each channel is programmable and may be selected for
latch−off or automatic retry.
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MARKING
DIAGRAM
32 LEAD LQFP
FT SUFFIX
CASE 873A
NCV7513
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
Device
Package
Shipping†
NCV7513FTG
LQFP
(Pb−Free)
250 Units/Tray
Features
• 16−Bit SPI with Frame Error Detection
• 3.3 V/5.0 V Compatible Parallel and Serial Control Inputs
• 3.3 V/5.0 V Compatible Serial Output Driver
• Two Enable Inputs
NCV7513FTR2G
LQFP
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Open−Drain Fault and Status Flags
• Programmable
− Shorted Load Fault Detection Thresholds
− Fault Recovery Mode
− Fault Retry Timer
− Flag Masking
• Load Diagnostics with Latched Unique Fault Type Data
− Shorted Load
− Open Load
− Short to GND
• These are Pb−Free Devices*
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Benefits
• Scalable to Load by Choice of External MOSFET
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 0
NCV7513/D
NCV7513
IN5 IN4 IN3 IN2 IN1 IN0
ENA2
VCC2
NCV7513
Hex MOSFET Pre−Driver
CHANNEL 0
DRN0
GAT0
DRN1
FAULT
DETECT
POWER ON RESET
&
VCC1
ENA1
VSS
VCC2
POR
BIAS
DRIVER
VSS
GATE SELECT
FLAG MASK
ENA ENA
DRN
REF
VCC2
VCC2
VCC2
CHANNEL 1
DISABLE MODE
REFRESH/REF
1
2
DISABLE
PARALLEL
SERIAL
GAT1
DRN2
CSB
SCLK
SI
6
ENA ENA
DRN
CHANNEL 2
VCC
1
2
REF
POR
CSB
SCLK
SI
DISABLE
PARALLEL
SERIAL
GAT2
DRN3
SPI
16 BIT
ENA ENA
DRN
CHANNEL 3
1
2
REF
VDD
SO
DISABLE
PARALLEL
SERIAL
GAT3
DRN4
DRIVER
SO
DRN
ENA ENA VCC2
CHANNEL 4
VSS
1
2
REF
12
DISABLE
PARALLEL
SERIAL
FAULT BITS
GAT4
DRN5
FLTB
GND
ENA ENA
DRN
VCC2
CHANNEL 5
1
2
FAULT LOGIC
&
REFRESH TIMER
REF
DISABLE
PARALLEL
SERIAL
2
GAT5
CLOCK
ENA1
VSS
ENA
1
DRN 0:5
MASK 0:5
POR
CH
0−2
DRAIN
FEEDBACK
MONITOR
FAULT
REFERENCE
GENERATOR
4
STAB
CH
FLTREF
+
OA
3−5
−
Figure 1. Block Diagram
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2
NCV7513
V
LOAD
M
+5V
RFILT
POWER−ON
RESET
CB1
VCC1
FLTREF
ENA1
ENA2
IN0
VCC2
DRN0
GAT0
DRN1
GAT1
DRN2
GAT2
DRN3
GAT3
DRN4
GAT4
DRN5
GAT5
+5V OR
+3.3V
RD0
RD1
RD2
RD3
RD4
NID9N05CL
NID9N05CL
NID9N05CL
RST
IN1
IN2
CB2
IN3
NID9N05CL
NID9N05CL
NID9N05CL
IN4
IN5
IRQ
I/O
FLTB
CSB
SCLK
SI
RD5
RFPU
VDD
SO
STAB
GND
RSPU
VSS
Figure 2. Application Diagram
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3
NCV7513
PIN FUNCTION DESCRIPTION
Symbol
Description
FLTREF
DRN0 – DRN5
GAT0 – GAT5
ENA1, ENA2
IN0 – IN5
CSB
Analog Fault Detect Threshold: 5.0 V Compliant
Analog Drain Feedback: Internally Clamped
Analog Gate Drive: 5.0 V Compliant
Digital Master Enable Inputs: 3.3 V/5.0 V (TTL) Compatible
Digital Parallel Input: 3.3 V/5.0 V (TTL) Compatible
Digital Chip Select Input: 3.3 V/5.0 V (TTL) Compatible
Digital Shift Clock Input: 3.3 V/5.0 V (TTL) Compatible
Digital Serial Data Input: 3.3 V/5.0 V (TTL) Compatible
Digital Serial Data Output: 3.3 V/5.0 V Compliant
Digital Open−Drain Output: 3.3 V/5.0 V Compliant
Digital Open−Drain Output: 3.3 V/5.0 V Compliant
Power Supply − Low Power Path
SCLK
SI
SO
STAB
FLTB
VCC1
GND
Power Return − Low Power Path – Device Substrate
Power Supply − Gate Drivers
VCC2
VDD
Power Supply − Serial Output Driver
VSS
Power Return – VCC2, VDD, Drain Clamps
24 23 22 21 20 19 18 17
GAT1
DRN1
GAT0
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
STAB
VDD
SO
DRN0
VCC2
VCC1
FLTREF
GND
NCV7513
SI
SCLK
CSB
FLTB
1
2
3
4
5
6
7
8
Figure 3. 32 Pin LQFP Pinout (Top View)
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4
NCV7513
MAXIMUM RATINGS (Voltages are with respect to device substrate.)
Rating
Value
−0.3 to 6.5
"0.3
Unit
V
DC Supply (V
, V
, V
)
CC1 CC2 DD
Difference Between V
and V
V
CC1
CC2
Difference Between GND (Substrate) and V
Output Voltage (Any Output)
"0.3
V
SS
−0.3 to 6.5
−0.3 to 40
10
V
Drain Feedback Clamp Voltage (Note 1)
Drain Feedback Clamp Current (Note 1)
Input Voltage (Any Input)
V
mA
V
−0.3 to 6.5
−40 to 150
260 peak
Junction Temperature, T
°C
°C
J
Peak Reflow Soldering Temperature: Lead−free
60 to 150 seconds at 217°C (Note 2)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ATTRIBUTES
Characteristic
Value
ESD Capability
Human Body Model
Machine Model
w " 2.0 kV
w " 200 V
Moisture Sensitivity (Note 2)
MSL2
Package Thermal Resistance (Note 3)
Junction–to–Ambient, R
86.0 °C/W
58.5 °C/W
q
JA
Junction–to–Pin, R
q
JL
1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power
dissipationis limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances.
2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and
ApplicationNote AND8003/D.
3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using
2
a minimum width signal trace pattern (384 mm trace area).
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5
NCV7513
ELECTRICAL CHARACTERISTICS (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise specified.) (Note 4)
CCX J
CCX
DD
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
V
CC1
Supply
Operating Current –
= 5.25 V, V
ENA = 0
–
–
2.80
3.10
5.0
5.0
mA
X
V
= 1.0 V
ENA = ENA = V
,
CC1
FLTREF
1
2
CC1
V
DRNX
= 0 V, GAT drivers off
X
ENA = ENA = V ,
CC1
–
2.80
5.0
1
2
GAT drivers on
X
Power−On Reset Threshold
Power−On Reset Hysteresis
V
−
Rising
3.65
4.20
4.60
–
V
V
CC1
0.150
0.385
Digital I/O
V
V
V
High
ENA , IN , SI, SCLK, CSB
2.0
–
–
–
0.8
500
–
V
V
IN
IN
IN
X
X
Low
ENA , IN , SI, SCLK, CSB
–
X
X
Hysteresis
ENA , IN , SI, SCLK, CSB
100
−25
–
330
−10
10
mV
mA
mA
X
X
Input Pullup Current
CSB V = 0 V
IN
Input Pulldown Current
ENA2, IN , SI, SCLK,
25
X
V
IN
= V
CC1
Input Pulldown Resistance
SO Low Voltage
ENA1
100
–
150
200
0.25
–
kW
V
V
DD
V
DD
= 3.3 V, I
= 3.3 V, I
= 5.0 mA
0.11
SINK
SO High Voltage
= 5.0 mA
V
DD
−
V
DD
−
V
SOURCE
0.25
0.11
22
–
SO Output Resistance
SO Tri−State Leakage Current
STAB Low Voltage
Output High or Low
CSB = 3.3 V
–
–
W
mA
V
−10
–
10
STAB Active, I
= 1.25 mA
0.1
–
0.25
10
STAB
STAB Leakage Current
FLTB Low Voltage
V
STAB
= V
–
mA
V
CC1
FLTB Active, I
= 1.25 mA
–
0.1
–
0.25
10
FLTB
FLTB Leakage Current
V
FLTB
= V
–
mA
CC1
Fault Detection – GAT ON
X
FLTREF Input Current
V
= 0 V
−1.0
0
–
–
–
mA
FLTREF
FLTREF Input Linear Range
(Note 5)
V
−
V
CC1
2.0
FLTREF Op−amp V
PSRR
(Note 5)
30
–
–
dB
V
CC1
DRN Clamp Voltage
V
CL
I
I
= 10 mA
= I
27
–
32
33.6
–
37
X
DRNX
DRNX
= 10 mA
CL(MAX)
DRN Shorted Load Threshold
Register 2: R = 0, R = 0 or
20
25
50
75
100
–
30
%
X
1
0
R = 0, R = 0
V
V
V
V
4
3
FLTREF
GAT Output High
X
Register 2: R = 0, R = 1 or
45
55
%
1
0
V
= 1.0 V
FLTREF
R = 0, R = 1
4
3
FLTREF
Register 2: R = 1, R = 0 or
70
80
%
1
0
R = 1, R = 0
4
3
FLTREF
Register 2: R = 1, R = 1 or
95
105
1.0
%
1
0
R = 1, R = 1
4
3
FLTREF
DRN Input Leakage Current
V
CC1
= V
= V = 5.0 V,
−1.0
mA
X
CC2
DD
ENA = IN = 0 V,
X
X
V
DRNX
= V
CL(MIN)
V
CC1
= V = V = 0 V,
CC2 DD
ENA = IN = 0 V,
X
X
V
DRNX
= V
CL(MIN)
4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
5. Guaranteed by design.
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6
NCV7513
ELECTRICAL CHARACTERISTICS (continued) (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise
CCX J
CCX
DD
specified.) (Note 6)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Fault Detection – GAT OFF
X
DRN Diagnostic Current
I
Short to GND Detection,
= 0.30 V
−27
30
−20
60
−10
80
mA
mA
X
SG
V
DRNX
CC1
I
Open Load Detection,
= 0.75 V
OL
V
DRNX
CC1
DRN Fault Threshold Voltage
V
Short to GND Detection
Open Load Detection
−
27
72
–
30
75
50
33
78
–
%V
X
SG
CC1
CC1
CC1
V
%V
%V
OL
DRN Off State Bias Voltage
V
CTR
X
Gate Driver Outputs
GAT Output Resistance
Output High or Low
1.0
−5.25
1.9
1.80
–
2.5
kW
X
GAT High Output Current
V
= 0 V
−1.9
5.25
mA
mA
ms
X
GATX
GATX
GAT Low Output Current
V
= V
–
X
CC2
Turn−On Propagation Delay
Turn−Off Propagation Delay
Output Rise Time
t
P(ON)
IN to GAT (Figure 4)
X
X
–
–
1.0
CSB to GAT (Figure 5)
X
t
ms
ms
IN to GAT (Figure 4)
P(OFF)
X
X
–
–
–
–
1.0
CSB to GAT (Figure 5)
X
t
R
20% to 80% of V
,
1.40
CC2
C
LOAD
= 400 pF
(Figure 4, Note 5)
80% to 20% of V
Output Fall Time
t
F
,
–
–
1.40
ms
CC2
C
LOAD
= 400 pF
(Figure 4, Note 5)
Fault Timers
Channel Fault Blanking Timer
t
V
= 5.0 V; IN rising to
30
90
45
60
ms
ms
BL(ON)
DRNX
X
FLTB falling (Figure 6)
t
V
DRNX
= 0 V; IN falling to
120
150
BL(OFF)
X
FLTB falling (Figure 6)
Channel Fault Filter Timer
t
t
Figure 7
7.0
7.5
30
–
12
10
17
12.5
50
ms
ms
ms
kHz
FF
Global Fault Refresh Timer
(Auto−retry Mode)
Register 2: Bit R = 0 or R = 0
FR
2
5
Register 2: Bit R = 1 or R = 1
40
2
5
Timer Clock
ENA1 = 1
= 5.0 V, V = 3.3 V, F
500
–
Serial Peripheral Interface (Figure 9) V
= 4.0 MHz, C
= 200 pF
ccx
DD
SCLK
LOAD
SO Supply Voltage
V
DD
3.3 V Interface
5.0 V Interface
−
3.0
4.5
–
3.3
5.0
250
–
3.6
5.5
–
V
V
SCLK Clock Period
Maximum Input Capacitance
SCLK High Time
ns
pF
ns
ns
ns
Sl, SCLK (Note 7)
SCLK = 2.0 V to 2.0 V
SCLK = 0.8 V to 0.8 V
Sl = 0.8 V/2.0 V to
–
12
–
125
125
25
–
SCLK Low Time
–
–
Sl Setup Time
–
–
SCLK = 2.0 V (Note 7)
Sl Hold Time
SCLK = 2.0 V to
25
–
–
ns
Sl = 0.8 V/2.0 V (Note 7)
6. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
7. Guaranteed by design.
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7
NCV7513
ELECTRICAL CHARACTERISTICS (continued) (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise
CCX J
CCX
DD
specified.) (Note 8)
Characteristic
Symbol
Conditions
Min
Typ
= 200 pF
Max
Unit
Serial Peripheral Interface (continued) (Figure 9) V
= 5.0 V, V = 3.3 V, F
= 4.0 MHz, C
ccx
DD
SCLK
LOAD
SO Rise Time
(20% V to 80% V
)
–
25
50
50
–
ns
ns
ns
ns
ns
ns
ms
SO
DD
C
LOAD
= 200 pF (Note 9)
SO Fall Time
(80% V to 20% V
)
–
60
75
–
–
SO
DD
C
LOAD
= 200 pF (Note 9)
CSB Setup Time
CSB Hold Time
CSB to SO Time
SO Delay Time
Transfer Delay Time
CSB = 0.8 V to SCLK = 2.0 V
(Note 9)
–
SCLK = 0.8 V to CSB = 2.0 V
(Note 9)
–
–
CSB = 0.8 V to SO Data Valid
(Note 9)
65
65
–
125
125
–
SCLK = 0.8 V to SO Data Valid
(Note 9)
–
CSB Rising Edge to Next
Falling Edge (Note 9)
1.0
8. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
9. Guaranteed by design.
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8
NCV7513
50%
INX
tP(OFF)
tR
tF
80%
20%
50%
GATX
tP(ON)
Figure 4. Gate Driver Timing Diagram – Parallel Input
50%
CSB
GX
tP(OFF)
50%
GATX
tP(ON)
Figure 5. Gate Driver Timing Diagram – Serial Input
DRNX
50%
INX
tBL(ON)
tBL(OFF)
50%
50%
FLTB
Figure 6. Blanking Timing Diagram
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9
NCV7513
OPEN LOAD
THRESHOLD
SHORTED
LOAD
THRESHOLD
DRNX
INX
tFF
tFF
50%
50%
FLTB
Figure 7. Filter Timing Diagram
GATX
tBL(ON)
tFR
tFF
tFR
tBL(ON)
tFR
DRNX
INX
SHORTED LOAD THRESHOLD (FLTREF)
Figure 8. Fault Refresh Timing Diagram
CSB
SETUP
TRANSFER
DELAY
CSB
SI
SETUP
CSB
HOLD
SCLK
1
16
SI
HOLD
BITS 14...1
SI
MSB IN
LSB IN
SO
DELAY
SO
RISE,FALL
CSB to
SO VALID
80% VDD
20% VDD
SEE
NOTE
BITS 14...1
SO
LSB OUT
MSB OUT
Note: Not defined but usually MSB of data just received.
Figure 9. SPI Timing Diagram
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NCV7513
DETAILED OPERATING DESCRIPTION
General
The active−low CSB chip select input has a pullup
current source. The SI and SCLK inputs have pulldown
current sources. The recommended idle state for SCLK is
low. The tri−state SO line driver can be supplied with either
The NCV7513 is a six channel general purpose low−side
pre−driver for controlling and protecting N−type logic
level MOSFETs. While specifically designed for driving
MOSFETs with resistive, inductive or lamp loads in
automotive applications, the device is also suitable for
industrial and commercial applications. Programmable
fault detection and protection modes allow the NCV7513
to accommodate a wide range of external MOSFETs and
loads, providing the user with flexible application
solutions. Separate power supply pins are provided
for low and high current paths to improve analog
accuracy and digital signal integrity. ON Semiconductor’s
SMARTDISCRETESTM clamp MOSFETs, such as the
NID9N05CL, are recommended when driving unclamped
inductive loads.
3.3 or 5.0 V and is powered via the device’s V and V
DD
SS
pins.
The NCV7513 employs frame error detection that
requires integer multiples of 16 SCLK cycles during each
CSB high−low−high cycle (valid communication frame.)
A frame error does not affect the flags. The CSB input
controls SPI data transfer and initializes the selected
device’s frame error and fault reporting logic.
The host initiates communication when a selected
device’s CSB pin goes low. Output (fault) data is
simultaneously sent MSB first from the SO pin while input
(command) data is received MSB first at the SI pin under
synchronous control of the master’s SCLK signal while
CSB is held low (Figure 10). Fault data changes on the
falling edge of SCLK and is guaranteed valid before the
next rising edge of SCLK. Command data received must be
valid before the rising edge of SCLK.
When CSB goes low, frame error detection is initialized,
latched fault data is transferred to the SPI, and the FLTB
flag is disabled and reset if previously set. Data for faults
detected while CSB is low are ignored but will be captured
if still present after CSB goes high.
If a valid frame has been received when CSB goes high,
the last multiple of 16 bits received is decoded into
command data, and FLTB is re−enabled. Latched
(previous) fault data is cleared and current fault data is
captured. The FLTB flag will be set if a fault is detected.
If a frame error is detected when CSB goes high, new
command data is ignored, and previous fault data remains
latched and available for retrieval during the next valid
frame. The FLTB flag will be set if a fault (not a frame
error) is detected.
Power Up/Down Control
The NCV7513’s powerup/down control prevents
spurious output operation by monitoring the V
supply. An internal Power−On Reset (POR) circuit causes
power
CC1
all GAT outputs to be held low until sufficient voltage is
X
available to allow proper control of the device. All internal
registers are initialized to their default states, fault data is
cleared, and the open−drain fault (FLTB) and status
(STAB) flags are disabled.
When V
exceeds the POR threshold, outputs and
CC1
flags are enabled and the device is ready to accept input
data. When V falls below the POR threshold during
power down, flags are reset and disabled and all GAT
outputs are driven and held low until V
about 0.7 V.
CC1
X
falls below
CC1
SPI Communication
The NCV7513 is a 16−bit SPI slave device. SPI
communication between the host and the NCV7513 may
either be parallel via individual CSB addressing or
daisy−chained through other devices using a compatible
SPI protocol.
CSB
MSB
LSB
4 − 13
B12 − B3
B12 − B3
1
2
3
14
15
16
SCLK
SI
X
B15
B14
B14
B13
B13
B2
B2
B1
B1
B0
B0
X
Z
SO
UKN
B15
Z
Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data
Figure 10. SPI Communication Frame Format
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11
NCV7513
Serial Data and Register Structure
MSB
LSB
The 16−bit data sent by the NCV7513 is always the
encoded 12−bit fault information, with the upper 4 bits
forced to zero. The 16−bit data received is decoded into a
4−bit address and a 6−bit data word (see Figure 11). The
upper four bits, beginning with the received MSB, are fully
decoded to address one of four programmable registers and
the lower six bits are decoded into data for the addressed
register. Bit B15 must always be set to zero. The valid
register addresses are shown in Table 1. Each register is
next described in detail.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
CH5
CH4
CH3
CH2
CH1
CH0
CHANNELFAULT OUTPUT DATA
COMMAND INPUT DATA
REGISTER SELECT
MSB
LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
A2 A1 A0
X
X
X
X
X
X
D5 D4 D3 D2 D1 D0
Figure 11. SPI Data Format
Table 1. Register Address Definitions
4−BIT ADDRESS
6−BIT INPUT DATA
B
15
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0
0
0
0
Gate Select
Disable Mode
0
0
0
0
0
0
0
1
0
1
1
X
1
0
1
X
Refresh & Reference
Flag Mask
Null
16−BIT OUTPUT DATA
B
B
B
B
B
11
D
11
B
0
15
14
13
12
0
0
0
0
12−bit Fault Data
D
0
Gate Select – Register 0
Each GAT output is turned on/off by programming its
to 1 causes the selected GAT output to latch−off when a
X
fault is detected. Setting a bit to 0 causes the selected GAT
X
X
respective G bit (see Table 2). Setting a bit to 1 causes the
output to auto−retry when a fault is detected. At powerup,
each bit is set to 0 (all outputs in auto−retry mode).
X
selected GAT output to drive its external MOSFET’s gate
X
to V
(ON). Setting a bit to 0 causes the selected GAT
X
CC2
output to drive its external MOSFET’s gate to V (OFF).
Table 3. Disable Mode Register
SS
Note that the actual state of the output depends on POR,
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
ENA and shorted load fault states as later defined by
Equation 1. At powerup, each bit is set to 0 (all outputs
OFF).
X
0
0
1
M
5
M
M
M
M
1
M
0
4
3
2
0 = AUTO−RETRY
1 = LATCH OFF
Table 2. Gate Select Register
Refresh and Reference – Register 2
A
2
A
1
A
0
D
5
D
4
D
D
D
D
0
3
2
1
Refresh time (auto−retry mode) and shorted load fault
detection references are programmable in two groups of
three channels. Refresh time and the fault reference for
0
0
0
G
G
G
G
G
G
0
5
4
3
2
1
0 = GAT OFF
X
channels 5−3 is programmed by R bits 5−3. Refresh time
1 = GAT ON
X
X
and the fault reference for channels 2−0 is programmed by
Disable Mode – Register 1
The disable mode for shorted load faults is controlled by
each channel’s respective M bit (see Table 3). Setting a bit
R bits 2−0 (see Table 4). At powerup, each bit is set to 0
X
(V
= 25% V , t = 10 ms).
FLTREF FR
FLT
X
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NCV7513
Table 4. Refresh and Reference Register
A2
0
A1
1
A0
0
D5
R5
D4
D3
R3
D2
R2
D1
D0
R0
R4
R1
CHANNELS 5−3
CHANNELS 2−0
25% VFLTREF
50% VFLTREF
75% VFLTREF
VFLTREF
X
X
X
X
X
X
0
0
0
0
1
X
X
X
X
0
0
0
0
1
1
0
1
0
1
1
1
1
tFR = 10 ms
tFR = 40 ms
tFR = 10 ms
tFR = 40 ms
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
1
Flag Mask – Register 3
The drain feedback from each channel’s DRN input is
Gate Driver Control and Enable
Each GAT output may be turned on by either its
X
X
combined with the channel’s K mask bit (Table 5). When
respective parallel IN input or the internal G (Gate
X X
X
K = 1, a channel’s mask is cleared and its feedback to the
X
Select) register bit via SPI communication. The device’s
FLTB and STAB flags is enabled. At powerup, each bit is
set to 0 (all masks set).
common ENA enable inputs can be used to implement
X
global control functions, such as system reset, overvoltage
or input override by a watchdog controller. Each parallel
input and the ENA2 input have individual internal
pulldown current sources. The ENA1 input has an internal
pulldown resistor. Unused parallel inputs should be
connected to GND and unused enable inputs should be
Table 5. Flag Mask Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
K
5
K
4
K
3
K
2
K
1
K
0
0 = MASK SET
1 = MASK CLEAR
connected to V . Parallel input is recommended when
CC1
low frequency (v2.0 kHz) PWM operation of the outputs
is desired.
The STAB flag is influenced when a mask bit changes
CLR→SET after one valid SPI frame. FLTB is influenced
after two valid SPI frames. This is correct behavior for
FLTB since, while a fault persists, the FLTB will be set
when CSB goes LO→HI at the end of an SPI frame. The
mask instruction is decoded after CSB goes LO→HI so
FLTB will only reflect the mask bit change after the next
SPI frame. Both FLTB and STAB require only one valid
SPI frame when a mask bit changes SET→CLR.
ENA2 disables all GAT outputs when brought low.
When ENA1 is brought low, all GAT outputs, the timer
clock, and the flags are disabled. The fault and gate
registers are cleared and the flags are reset. New serial G
data is ignored while ENA1 is low but other registers can
be programmed.
When both the ENA1 and ENA2 inputs are high, the
outputs will reflect the current parallel or serial input states.
This allows ENA1 to be used to perform a soft reset and
X
X
X
ENA2 to be used to disable the GAT outputs during
initialization of the NCV7513.
X
Null Register – Register 4
Fault information is always returned when any register
is addressed. The null register (Table 6) provides a way to
read back fault information without regard to the content
The IN input state and the G register bit data are
X
X
logically combined with the internal (active low)
power−on reset signal (POR), the ENA input states, and
X
of D .
X
the shorted load state (SHRT ) to control the
X
corresponding GAT output such that:
X
Table 6. Null Register
GAT + POR · ENA1 · ENA2 · SHRT · (IN ) G )
X
x
x
x
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
(eq. 1)
1
X
X
X
X
X
X
X
X
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NCV7513
The GAT state truth table is given in Table 7.
On−state faults will initiate MOSFET protection
behavior, set the FLTB flag and the respective channel’s D
bits in the device’s fault latches. Off−state faults will
X
X
Table 7. Gate Driver Truth Table
POR
0
ENA1
ENA2
SHRT
IN
G
GAT
L
X
X
X
X
simply set the FLTB flag and the channel’s D bits.
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
Fault types are uniquely encoded in a 2−bit per channel
format. Fault information for all channels simultaneously
is retrieved by SPI read (Figure 11). Table 8 shows the
fault−encoding scheme for channel 0. The remaining
channels are identically encoded.
1
0
X
X
L
1
0
1
0
L
1
1
X
L
1
1
1
0
L
Table 8. Fault Data Encoding
1
1
1
1
1
X
H
H
L
CHANNEL 0
STATUS
1
1
1
1
X
X
X
X
0
1
D
1
D
0
1
1
1
0
X
0
0
NO FAULT
OPEN LOAD
1
1→0
1
1
X
X
X
→0
→L
→L
0
1
1
1
0
1
1
1→0
0→1
G
X
SHORT TO GND
SHORTED LOAD
1
1
G
→G
X
X
Gate Drivers
The non−inverting GAT drivers are symmetrical
X
Blanking and Filter Timers
resistive switches (1.80 kW typ.) to the V
and V
CC2
SS
Blanking timers are used to allow drain feedback to
stabilize after a channel is commanded to change states.
Filter timers are used to suppress glitches while a channel
is in a stable state.
voltages. While the outputs are designed to provide
symmetrical gate drive to an external MOSFET, load
current switching symmetry is dependent on the
characteristics of the external MOSFET and its load.
Figure 12 shows the gate driver block diagram.
A turn−on blanking timer is started when a channel is
commanded on. Drain feedback is sampled after t
.
BL(ON)
A turn−off blanking timer is started when a channel is
commanded off. Drain feedback is sampled after t
A filter timer is started when a channel is in a stable state
and a fault detection threshold associated with that state has
FILTER
TIMER
DX0
ENCODING
LOGIC
FAULT
DETECTION
50
.
BL(OFF)
DX1
DRNX
GATX
BLANKING
TIMER
VSS
S
tFR
LATCH OFF /
R | R5
MX
been crossed. Drain feedback is sampled after t .
2
FF
AUTO RE−TRY
_
SHRT
X
VCC2
EN
R
Blanking timers for all channels are started when both
1800
INX
GX
DRIVER
VSS
ENA1 and ENA2 go high or when either ENA goes high
X
while the other is high. The blanking time for each channel
ENA1
ENA2
POR
depends on the commanded state when ENA goes high.
X
While each channel has independent blanking and filter
Figure 12. Gate Driver Channel
timers, the parameters for the t
, t
, and t
BL(ON) BL(OFF) FF
times are the same for all channels.
Fault Diagnostics and Behavior
Shorted Load Detection
Each channel has independent fault diagnostics and
employs blanking and filter timers to suppress false faults.
An external MOSFET is monitored for fault conditions by
connecting its drain to a channel’s DRN feedback input
through an external series resistor.
When either ENA1 or ENA2 is low, diagnostics are
disabled. When both ENA1 and ENA2 are high,
diagnostics are enabled.
An external reference voltage applied to the FLTREF
input serves as a common reference for all channels
(Figure 13). The FLTREF voltage must be within the range
X
of 0 to V −2.0 V and can be derived via a voltage divider
CC1
between V
and GND.
CC1
Shorted load detection thresholds can be programmed
via SPI in four 25% increments that are ratiometric to the
applied FLTREF voltage. Separate thresholds can be
selected for channels 0−2 and for channels 3−5 (Table 4).
Shorted load (or short to V ) faults can be detected
LOAD
when a driver is on. Open load or short to GND faults can
be detected when a driver is off.
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NCV7513
A shorted load fault is detected when a channel’s DRN
Fault Recovery Refresh Time
X
feedback is greater than its selected fault reference after
either the turn−on blanking or the filter has timed out.
Refresh time for shorted load faults is SPI programmable
to one of two values for channels 0−2 (register bit R2) and
for channels 3−5 (register bit R5) via the Refresh and
Reference register (Table 4).
A global refresh timer with taps at nominally 10 ms and
40 ms is used for auto−retry timing. The first faulted
channel triggers the timer and the full refresh period is
guaranteed for that channel. An additional faulted channel
may initially retry immediately after its turn−on blanking
time, but subsequent retries will have the full refresh time
period.
VCC1
CHANNELS 0−2
FLTREF
0 − 3V
3
2
1
0
VCC1
2 X 4
DECODER
RX1
+
OA
RX2
R
R
R
R
−
R1
R0
75%
50%
25%
KELVIN
REGISTER 2
BITS
R4
R3
2 X 4
If all channels in a group (e.g. channels 0−2) become
faulted, they will become synchronized to the selected
refresh period for that group. If all channels become faulted
and are set for the same refresh time, all will become
synchronized to the refresh period.
DECODER
3
2
1
0
CHANNELS 3−5
Figure 13. Shorted Load Reference Generator
Open Load and Short to GND Detection
Shorted Load Fault Recovery
Shorted load fault disable mode for each channel is
individually SPI programmable via the M bits in the
device’s Disable Mode register (Table 3).
A
window comparator with fixed references
proportional to V along with a pair of bias currents is
CC1
X
used to detect open load or short to GND faults when a
channel is off. Each channel’s DRN feedback is compared
X
When latch−off mode is selected the corresponding
to the references after either the turn−off blanking or the
filter has timed out. Figure 14 shows the DRN bias and
fault detection zones. The diagnostics are disabled and the
GAT output is turned off upon detection of a fault. Fault
X
X
recovery is initiated by toggling (ON→OFF→ON) the
channel’s respective IN parallel input, serial G bit, or
X
X
bias currents are turned off when ENA is low.
X
ENA2.
When auto−retry mode is selected (default mode) the
corresponding GAT output is turned off for the duration
No fault is detected if the feedback voltage at DRN is
X
greater than the V open load reference. If the feedback
OL
X
is less than the V short to GND reference, a short to GND
SG
of the programmed fault refresh time (t ) upon detection
of a fault. The output is automatically turned back on (if
still commanded on) when the refresh time ends. The
FR
fault is detected. If the feedback is less than V
and
OL
greater than V , an open load fault is detected.
SG
channel’s DRN feedback is resampled after the turn−on
X
IDRNX
blanking time. The output will automatically be turned off
if a fault is again detected. This behavior will continue for
as long as the channel is commanded on and the fault
persists.
Short to
GND
Open
Load
No
Fault
IOL
In either mode, a fault may exist at turn−on or may occur
some time afterward. To be detected, the fault must exist
longer than either t
at turn−on or longer than t
BL(ON)
FF
some time after turn−on. The length of time that a
MOSFET stays on during a shorted load fault is thus limited
0
−I
SG
to either t
or t .
FF
BL(ON)
In auto−retry mode, a persistent shorted load fault will
result in a low duty cycle (t /t ) for the
VDRNX
t
FD
BL(ON) FR
[
VSG
VCTR
VOL
affected channel and help prevent thermal failure of the
channel’s MOSFET.
Figure 14. DRNX Bias and Fault Detection Zones
CAUTION − CONTINUOUS INPUT TOGGLING VIA
IN , G or ENA2 WILL OVERRIDE EITHER DISABLE
Figure 15 shows the simplified detection circuitry. Bias
X
X
MODE. Care should be taken to service a shorted load fault
quickly when one has been detected.
currents I and I are applied to a bridge along with bias
SG OL
voltage V
(50% V
typ.).
CTR
CC1
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NCV7513
Status Flag (STAB)
VCC1
The open−drain active−low status flag output can be used
to provide a host controller with information about the state
ISG
of a channel’s DRN feedback. Feedback from all channels
x
VLOAD
RLOAD
is logically ORed to the flag (Figure 16). The STAB
outputs from several devices can be wire−ORed to a
common pullup resistor connected to the controller’s 3.3 or
VOL
−
D3
D1
CMP1
A
B
1600
DRNX
RDX
+
50
VX
DZ1
+
CMP2
−
5.0 V V supply.
DD
RSG
(VCL
)
D4
D2
When ENA1 is high, the drain feedback from a channel’s
VSG
+VOS
DRN input is compared to the V
reference without
OL
x
+
_
VCTR
IOL
regard to ENA2 or the commanded state of the channel’s
driver. The flag is reset and disabled when ENA1 is low or
when all mask bits are set. See Table 9 for additional
details.
Figure 15. Short to GND/Open−Load Detection
The flag is set (low) when the feedback voltage is less
than V , and the channel’s mask bit (Table 5) is cleared.
The flag is reset (hi−Z) when the feedback voltage is
OL
When a channel is off and V
and R
are
LOAD
LOAD
>> V
present, R is absent, and V
, bias current
CTR
SG
DRNX
greater than V , and the channel’s mask bit is cleared.
OL
I
is supplied from V
to ground through external
OL
LOAD
resistors R
and R , and through the internal 1650 W
DX
LOAD
OTHER
CHANNELS
resistance and bridge diode D2. Bias current I is supplied
SG
STAB
KX
from V
to V
through D3. No fault is detected if the
CC1
CTR
VOL
D
−
feedback voltage (V
caused by I and the resistance in the path) is greater than
minus the total voltage drop
LOAD
CMP1
Q
A
DRNX
ENA1
+
SG
500 kHz
CLR
V
OL
.
POR
When either V
or R
and R are absent, the
LOAD SG
LOAD
bridge will self−bias so that the voltage at DRN will settle
X
to about V
feedback is between V and V
. An open load fault can be detected since the
CTR
Figure 16. STAB Flag Logic
.
SG
OL
Short to GND detection can tolerate up to a 1.0 V offset
(V ) between the NCV7513’s GND and the short. When
Fault Flag (FLTB)
OS
The open−drain active−low fault flag output can be used
to provide immediate fault notification to a host controller.
Fault detection from all channels is logically ORed to the
flag (Figure 17). The FLTB outputs from several devices
can be wire−ORed to a common pullup resistor connected
to the controller’s 3.3 or 5.0 V V supply.
The flag is set (low) when a channel detects any fault, the
channel’s mask bit (Table 5) is cleared, and both ENA and
R
is present and V
<< V , bias current I is
CTR SG
SG
DRNX
supplied from V
to V
through D1, the internal
CC1
OS
1650 W, and the external R
and R resistances. Bias
SG
DX
current I is supplied from V
to ground through D4.
OL
CTR
A “weak” short to GND can be detected when either
or R is absent and the feedback (V plus the
DD
V
LOAD
LOAD
OS
total voltage rise caused by I and the resistance in the
OL
x
path) is less than V
.
OL
CSB are high. The flag is reset (hi−Z) and disabled when
either ENA1 or CSB is low. See Table 9 for additional
details.
When V
and R
are present, a voltage divider
LOAD
LOAD
between V
and V is formed by R
and R . A
LOAD SG
LOAD
OS
“hard” short to GND may be detected in this case
depending on the ratio of R and R and the values of
LOAD
SG
OTHER
R
, V
, and V
.
CHANNELS
DX
LOAD
OS
KX
FLTB
FAULTX
Note that the comparators see a voltage drop or rise due
only to the 50 W internal resistance and the bias currents.
This produces a small difference in the comparison to the
S
R
ENA2
ENA1
Q
actual feedback voltage at the DRN input.
X
POR
(RESET DOMINANT)
Several equations for choosing R and for predicting
DX
CSB
open load or short to GND resistances, and a discussion of
the dynamic behavior of the short to GND/open load
diagnostic are provided in the Applications Information
section of this data sheet.
Figure 17. FLTB Flag Logic
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NCV7513
Fault Detection and Capture
flag is reset when CSB goes low at the start of the SPI
frame. Fault latches are cleared and re−armed when CSB
goes high at the end of the SPI frame only if a valid frame
has occurred; otherwise the latches retain the detected fault
data until a valid frame occurs. The FLTB flag will be set
if a fault is still present.
Fault latches for all channels and the FLTB flag can also
be cleared and re−armed by toggling ENA1 H−L−H. A full
I/O truth table is given in Table 9.
Each channel of the NCV7513 is capable of detecting
shorted load faults when the channel is on, and short to
ground or open load faults when the channel is off. Each
fault type is uniquely encoded into two−bit per channel
fault data. A drain feedback input for each channel
compares the voltage at the drain of the channel’s external
MOSFET to several internal reference voltages. Separate
detection references are used to distinguish the three fault
types, and blanking and filter timers are used respectively
to allow for output state transition settling and for glitch
suppression.
Fault diagnostics are disabled when either enable input
is low. When both enable inputs are high, each channel’s
drain feedback input is continuously compared to
references appropriate to the channel’s input state to detect
faults, but the comparison result is only latched at the end
of either a blanking or filter timer event.
Blanking timers for all channels are triggered when
either enable input changes state from low to high while the
other enable input is high, or when both enable inputs go
high simultaneously. A single channel’s blanking timer is
triggered when its input state changes. If the comparison of
the feedback to a reference indicates an abnormal condition
when the blanking time ends, a fault has been detected and
the fault data is latched into the channel’s fault latch.
A channel’s filter timer is triggered when its drain
feedback comparison state changes. If the change indicates
an abnormal condition when the filter time ends, a fault has
been detected and the fault data is latched into the channel’s
fault latch.
Fault Data Readback Examples
Several examples are shown to illustrate fault detection,
capture and SPI read−back of fault data for one channel. A
normal SPI frame returns 16 bits of data but only the two
bits of serial data for the single channel are shown for
clarity.
The examples assume:
• The NCV7513 is configured as in Figure 2
• Both enable inputs are high
• The channel’s flag mask bit is cleared
• Disable mode is set to auto−retry
• The parallel input commands the channel
• SPI frame is always valid
Shorted Load Detected
Refer to Figure 18. The channel is commanded on when
IN goes high. GAT goes high and the timers are started.
X
X
At “A”, the STAB flag is set as the DRN feedback falls
X
through the V threshold. A SPI frame sent soon after the
OL
IN command returns data indicating “no fault.”
X
The blanking time ends and the filter timer is triggered
Thus, a state change of the inputs (ENA , IN or G ) or
a state change of an individual channel’s feedback (DRN )
comparison must occur for a timer to be triggered and a
detected fault to be captured.
X
X
X
as DRN rises through the FLTREF threshold. The STAB
X
X
flag is reset as DRN passes through the V threshold.
X
OL
DRN is nearly at V
when the filter time ends at “B”.
X
LOAD
A shorted load fault is detected and captured by the fault
Fault Capture, SPI Communication, and SPI
Frame Error Detection
latch, GAT goes low, the FLTB flag is set, and the
auto−retry timer is started.
X
The fault capture and frame error detection strategies of
the NCV7513 combine to ensure that intermittent faults
can be captured and identified, and that the device cannot
be inadvertently reprogrammed by a communication error.
The NCV7513 latches a fault when it is detected, and
frame error detection will not allow any register to accept
data if an invalid frame occurred.
An SPI frame sent soon after “B” returns data indicating
“shorted load”. The FLTB flag is reset when CSB goes low.
At “C” when CSB goes high at the end of the frame, the
fault latch is cleared and re−armed. Since IN and the
X
DRN feedback are unchanged, FLTB and the fault latch
X
are set and the fault is recaptured.
When the auto−retry timer ends at “D”, GAT goes high
X
When a fault has been detected, the FLTB flag is set and
fault data is latched into a channel’s fault latch. The latch
captures and holds the fault data and ignores subsequent
fault data for that channel until a valid SPI frame occurs.
Fault data from all channels is transferred from each
channel’s fault latch into the SPI shift register and the FLTB
and the blanking and filter timers are started. Since IN and
X
DRN are unchanged, GAT goes low when the blanking
X
X
time ends at “E” and the auto−retry timer is started.
Read−back data continues to indicate a “shorted load” and
the FLTB flag continues to be set while the fault persists.
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NCV7513
1
0
1
0
INx
FAULT DETECTED
GATx
VLOAD
VOL
FLTREF
0
1
A
STAB
0
D
E
B
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tFR
tFR
tBL(ON)
tBL(ON)
INTERNAL
SIGNALS
C
FILTER
TIMER
tFF
FAULT
LATCH
00
00
11
11
11
11
11
CSB
SO
11
11
11
11
11
FLTB
Figure 18. Shorted Load Detected
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NCV7513
Shorted Load Recovery
Figure 19 is a continuation of Figure 18. IN is high
indicate “no fault” but because the latched data has not yet
been read, the data remains unchanged.
X
when the auto−retry timer ends. GAT goes high and the
blanking and filter timers are started. The fault is removed
The SPI frame sent after the blanking time ends returns
a “shorted load” fault because the previous frame occurred
during the blanking time. Since the channel’s fault bits
indicate “no fault”, FLTB is reset and the fault latch is
updated at “C” when CSB goes high. If another SPI frame
is sent before “D”, the returned data will indicate “no
fault”.
X
before the blanking timer ends, and DRN starts to fall. As
X
DRN passes through the V threshold at “A”, the STAB
X
OL
flag is set. DRN continues to fall and settles below the
X
FLTREF threshold.
An SPI frame is sent during the blanking time and returns
data indicating a “shorted load” fault. Although the fault is
removed, updates to the fault latches are suppressed while
a blanking or filter timer is active. The same fault is
captured again and FLTB is set when CSB goes high. At
“B” the blanking time ends and the channel’s fault bits will
The channel is commanded off at “D”. GAT goes low
X
and the timers are started. DRN starts to rise and the STAB
X
flag is reset as DRN passes through the V threshold.
X
OL
The SPI frame sent at “E” returns data indicating “no
fault”.
1
INx
0
D
1
GATx
0
FAULT REMOVED
VLOAD
A
VOL
FLTREF
0
1
STAB
0
B
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tFR
tBL(OFF)
tBL(ON)
INTERNAL
FILTER
TIMER
SIGNALS
tFF
tFF
FAULT
LATCH
11
11
11
00
CSB
SO
C
E
11
11
11
00
FLTB
Figure 19. Shorted Load Recovery
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19
NCV7513
Short to GND/Open Load
Figure 20 illustrates turn−off with an open or high
resistance load when some capacitance is present at DRN .
“open load” but because the latched data has not yet been
read, the data remains unchanged.
An SPI frame sent shortly after “B” returns data
indicating “short to GND” and the fault latch is updated at
“C” when CSB goes high. The next three frames sent after
“C” return data indicating an “open load”.
X
In the case of an open load, DRN rises and settles to V
.
X
CTR
In the case of a high resistance load, DRN may continue
X
to rise and may eventually settle to V
.
LOAD
The channel is commanded off. GAT goes low and the
The STAB flag is reset at “D” as DRN passes through
X
X
timers are started. DRN starts to rise and is below the V
the V threshold. Note that the filter timer is not triggered
OL
X
SG
threshold when the blanking time ends at “A”. A short to
GND fault is detected and captured by the fault latch, and
the FLTB flag is set.
as DRN passes from a fault state to a good state. The
X
channel’s fault bits will indicate “no fault” but because the
latched data has not yet been read, the data remains
unchanged.
DRN continues to rise and as it passes through the V
X
SG
threshold at “B”, the filter timer is triggered. At the end of
the filter time, the channel’s fault bits will indicate an
The fault latch is updated at “E” when CSB goes high and
the FLTB flag remains reset. The next SPI frame sent
returns data indicating “no fault”.
1
INx
0
1
GATx
0
VLOAD
VOL
VCTR
VSG
0
D
1
A
B
C
STAB
0
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tBL(OFF)
tFF
INTERNAL
SIGNALS
E
FILTER
TIMER
tFF
FAULT
LATCH
00
10
01
01
01
00
CSB
SO
00
10
01
01
01
00
FLTB
Figure 20. Short to GND/Open Load
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20
NCV7513
Table 9. I/O Truth Table
POR ENA1 ENA2 CSB
Inputs
Outputs*
K
IN
G
DRN
X
GAT
FLTB
→Z
Z
STAB
→Z
Z
D D
X1 X0
COMMENT
POR RESET
ENA1
X
→0
X
X
X
X
X
0
1
1
1
1
1
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
→0
→L
L
→00
X
X
00
1
0
K
X
K
X
K
X
G
X
L
FLTB
→Z
FLTB
Z
STAB
→Z
STAB
Z
D D
X1 X0
ENA2
X
1→0
1
1
→0
X
→L
→L
L
→00
ENA1 RESET
ENA2 DISABLE
FLAGS MASKED
1→0
X
G
X
D D
X1 X0
X
1
0
X
X
−
1
1
1
1
1
1
1
1
0
0
0
0
X
X
X
X
1
X
X
X
X
X
X
X
X
> V
< V
< V
< V
L
L
L
L
−
−
−
−
Z
−
−
−
−
STAB RESET
STAB SET
OL
OL
OL
OL
1
L
1→0
0→1
L→Z
Z→L
STAB RESET
STAB SET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
> V
L
L
L
L
L
L
L
L
L
L
L
Z
L
Z
L
00
01
01
01
01
01
10
10
10
10
10
FLAGS RESET
FLAGS SET
STAB RESET
STAB SET
OL
V
V
V
V
V
<V<V
SG
<V<V
SG
<V<V
SG
<V<V
SG
<V<V
SG
OL
OL
OL
OL
OL
X
1→0
0→1
1
L
L→Z
X
L
1→0
0→1
1
L→Z
Z→L
L
L
L
FLTB RESET
FLTB SET
1
1
< V
L
FLAGS SET
STAB RESET
STAB SET
SG
SG
SG
SG
SG
X
1→0
0→1
1
< V
L
L→Z
Z→L
L
X
< V
< V
< V
L
1→0
0→1
L→Z
Z→L
FLTB RESET
FLTB SET
1
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
X
X
X
X
X
X
X
1
< V
H
L
L
L
L
L
L
H
L
L
L
L
L
L
Z
L
00
11
11
11
11
11
11
00
11
11
11
11
11
11
STAB SET
FLTREF
1
1→0
0→1
1
V
V
V
V
V
<V<V
<V<V
<V<V
<V<V
<V<V
L
L
L
L→Z
Z→L
L
FLAGS SET
STAB RESET
STAB SET
FLTREF
FLTREF
FLTREF
FLTREF
FLTREF
OL
OL
OL
OL
OL
X
1
X
1
L
1→0
0→1
1
1
L→Z
Z→L
L
FLTB RESET
FLTB SET
1
1
L
1
1
> V
Z
STAB RESET
STAB SET
OL
FLTREF
X
1
X
X
X
X
X
X
X
< V
Z
L
1
1
1
V
V
V
V
V
<V<V
<V<V
<V<V
<V<V
<V<V
L
L
FLAGS SET
STAB RESET
STAB SET
FLTREF
FLTREF
FLTREF
FLTREF
FLTREF
OL
OL
OL
OL
OL
X
1→0
0→1
1
1
L
L→Z
Z→L
L
X
1
L
1→0
0→1
1
1
L→Z
Z→L
L
FLTB RESET
FLTB SET
1
1
L
1
1
> V
Z
STAB RESET
OL
* Output states after blanking and filter timers end and when channel is set to latch−off mode.
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21
NCV7513
APPLICATION GUIDELINES
General
Unused DRN inputs should be connected to V
prevent false open load faults. Unused parallel inputs
should be connected to GND and unused enable inputs
clamp power is limited to the maximum allowable junction
temperature.
To limit power in the DRN input clamps and to ensure
to
CC1
X
X
proper open load or short to GND detection, the R
DX
should be connected to V . The mask bit for each unused
resistor must be dimensioned according to the following
constraint equations:
CC1
channel should be ‘set’ (see Table 5) to prevent activation
of the flags and the user’s software should be designed to
ignore fault information for unused channels. For best
shorted−load detection accuracy, the external MOSFET
source terminals should be star−connected and the
NCV7513’s GND pin, and the lower resistor in the fault
reference voltage divider should be Kelvin connected to
the star (see Figures 2 and 13).
Consideration of auto−retry fault recovery behavior is
necessary from a power dissipation viewpoint (for both the
NCV7513 and the MOSFETs) and also from an EMI
viewpoint.
Driver slew rate and turn−on/off symmetry can be
adjusted externally to the NCV7513 in each channel’s gate
circuit by the use of series resistors for slew control, or
resistors and diodes for symmetry. Any benefit of EMI
reduction by this method comes at the expense of increased
switching losses in the MOSFETs.
The channel fault blanking timers must be considered
when choosing external components (MOSFETs, slew
control resistors, etc.) to avoid false faults. Component
choices must ensure that gate circuit charge/discharge
times stay within the turn−on/turn−off blanking times.
The NCV7513 does not have integral drain−gate flyback
clamps. Clamp MOSFETs, such as ON Semiconductor’s
NID9N05CL, are recommended when driving unclamped
inductive loads. This flexibility allows choice of MOSFET
clamp voltages suitable to each application.
V
−V
PK CL(MIN)
I
(eq. 2)
R
+
DX(MIN)
CL(MAX)
|
|
V
− V
SG OS
(eq. 3)
R
+
DX(MAX)
|
|
I
SG
where V is the peak transient drain voltage, V is the
PK
CL
DRN input clamp voltage, I
is the input clamp
CL(MAX)
X
current, and V and I are the respective short to GND
SG
SG
fault detection voltage and diagnostic current, and V is
OS
the allowable offset (1.0 V max) between the NCV7513’s
GND and the short.
Once R
is chosen, the open load and short to GND
DX
detection resistances in the application can be predicted:
V
−V
LOAD OL
(eq. 4)
R
OL
w
* R
DX
I
OL
|
|
R
R
(V
" V − I
)
LOAD SG
OS SG DX
(eq. 5)
R
SG
v
|
|
(R
V
−V
) I
) R
)
LOAD SG
SG DX
LOAD
Using the data sheet values for V
= 27 V,
CL(MIN)
I
= 10 mA, and choosing V = 55 V as an
PK
CL(MAX)
example, Equation 2 evaluates to 2.8 kW minimum.
Choosing V = 5.0 V and using the typical data sheet
CC1
values for V = 30%V , I = 20 mA, and choosing
SG
CC1 SG
V
OS
= 0, Equation 3 evaluates to 75 kW maximum.
Selecting R = 6.8 kW "5%, V
= 5.0 V, V
=
LOAD
DX
CC1
12.0 V, V = 0 V, R
= 555 W, and using the typical
LOAD
OS
data sheet values for V , I , V , and I , Equation 4
OL OL
SG
SG
predicts an open load detection resistance of 130.7 kW and
DRN Feedback Resistor
X
Equation 5 predicts a short to GND detection resistance of
Each DRN feedback input has a clamp to keep the
X
71.1 W. When R and the data sheet values are taken to
applied voltage below the breakdown voltage of the
DX
their extremes, the open load detection range is 94.1 kW v
NCV7513. An external series resistor (R ) is required
DX
R
v 273.5 kW, and the short to GND detection range is
between each DRN input and MOSFET drain. Channels
OL
X
59.2 W v R v 84.4 W.
may be clamped sequentially or simultaneously but total
SG
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22
NCV7513
PACKAGE DIMENSIONS
32 LEAD LQFP
FT SUFFIX
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
AE
AE
−U−
V1
−T−
P
B
V
B1
DETAIL Y
−Z−
BASE
METAL
DETAIL Y
17
8
N
9
4X
0.20 (0.008) AC T−U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
MIN
MAX
A
A1
B
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
3.500 BSC
7.000 BSC
3.500 BSC
3. DATUM PLANE −AB− IS LOCATED AT
B1
C
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150
0.200
0.750
0.002
0.004
0.018
0.006
0.008
0.030
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
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23
NCV7513
FLEXMOS and SMARTDISCRETES are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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NCV7513/D
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