NCV7705DQR2G_技术文档

NCV7705, NCV7706

Mirror-Module Driver-IC

The NCV7705/NCV7706 is a powerful Driver−IC for automotive

body control systems. The IC is designed to control several loads in

the front door of a vehicle. The monolithic IC is able to control mirror

functions like mirror positioning, heating and folding. In addition,

NCV7706 includes the electro−chromic mirror feature. The device

features four high−side outputs to drive LEDs or incandescent bulbs

(up to 5/10 W). To allow maximum flexibility, all lighting outputs can

be PWM controlled thru PWM inputs (external signal source) or by an

internal programmable PWM generator unit. The

NCV7705/NCV7706 is controlled thru a 24 bit SPI interface with

in−frame response.

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SSOP36 EP

DQ SUFFIX

CASE 940AB

Features

• Operating Range from 5.5 V to 28 V

MARKING DIAGRAM

• Four High−Side and Four Low−Side Drivers Connected as

Half−Bridges

♦ 2x Half−bridges I

♦ 2x Half−Bridges I

= 0.75 A; R

= 1.6 W @ 25°C

DS(on)

load

= 3 A; R

= 300 mW @ 25°C

load

DS(on)

NCV770x

AWLYYWWG

• Four High−Side Lamp Drivers

♦ 2x LED; I = 0.3 A; R

= 1.4 W @ 25°C

DS(on)

load

♦ 1x 10 W; Configurable as LED Driver; I

= 2.5 A;

load

R

= 300 mW @ 25°C

DS(on)

♦ 1x 5 W; Configurable as LED Driver; I

= 1.25 A;

= 6 A;

NCV770x = Specific Device Code

NCV770x = (x = 5 or 6)

load

R

= 600 mW @ 25°C

DS(on)

A

= Assembly Location

= Wafer Lot

• 1x High−Side Driver for Mirror Heating; I

load

WL

YY

WW

G

R

= 100 mW @ 25°C

DS(on)

= Year

= Work Week

= Pb−Free Package

• Electro Chromic Mirror Control (NCV7706 Only)

♦ 1x 6−Bit Selectable Output Voltage Controller

♦ 1x LS for EC Control; I

= 0.75 A; R

= 1.6 W @ 25°C

load

DS(on)

ORDERING INFORMATION

• Independent PWM Functionality for All Outputs

†

• Integrated Programmable PWM Generator Unit for All Lamp Driver

Shipping

Device

Package

Outputs

SSOP36−EP

GREEN

(Pb−Free)

NCV7705DQR2G

NCV7706DQR2G*

1500 / Tape &

Reel

♦ 7−bit / 10−bit Selectable Duty−cycle Setting Precision

• Programmable Soft−start Function to Drive Loads with Higher

Inrush Currents as Current Limitation Value

• Multiplex Current Sense Analog Output for Advanced Load

Monitoring

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

• Very Low Current Consumption in Standby Mode

* Contact local sales office for availability

• Charge Pump Output to Control an External Reverse Polarity

Protection MOSFET

• 24−Bit SPI Interface for Output Control and Diagnostic

• SSOP36−EP Power Package

• This is a Pb−Free Device

• Protection Against Short−circuit, Overvoltage and

Over−temperature

Typical Applications

• Downwards Pin−to−Pin and SPI Registers Compatible

with NCV7707

• AEC−Q100 Qualified and PPAP Compliant

• De−centralized Door Electronic Systems

• Body Control Units (BCUs)

1

Publication Order Number:

NCV7705/D

January, 2016 − Rev. 0

NCV7705, NCV7706

VS

CHP

NCV7705/06

Diagnostic

short circuit

openload

overload

overtemperature

overvoltage

Undervoltage

Lockout

Overvoltage

Lockout

Power−on Reset

Chargepump

VS

undervoltage

VCC

SI

SCLK

CSB

overload

OUT1

CONTROL _0 Register

Driver

SO

Interface

VS

CONTROL _1 Register

CONTROL _2 Register

CONTROL _3 Register

PWM_5/6 Register

OUT2

OUT3

VS

PWM

Unit

OUT4

PWM_7/8 Register

STATUS _0 Register

STATUS _1 Register

VS

OUT5

OUT6

OUT7

OUT8

VS

STATUS _2 Register

CONFIG Register

VS

Special Function Register

PWM1

PWM2

PWM1

OUT9

ISOUT/

PWM2

MUX

GND

ECON

ECFB

DAC

EC Control

6

NCV7706 only

Figure 1. Block Diagram

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2

NCV7705, NCV7706

footstep

light

safety

light

10W

/LED

OUT6

safety

light

Vbat

blinker

LED

OUT8

LED

5W

Switches

VS

/LED

OUT7

OUT5

CHP

NCV7705/06

High−Side High−Side

High−Side

Switch

High−Side

Switch

Ω)

Charge Pump

Switch

24−bit

Serial

Data

Ω)

SO

SI

(1.4

(0.3/1.4

(0.6/1.4

Power−on Reset

Interface

SCLK

CSB

Protection :

short circuit

open load

over temperature

VS undervoltage

VS overvoltage

PWM Generator Unit

Logic Control

mC

Logic IN

PWM1

Current Sensing

ISOUT /

PWM2

Rs

GND

PWM

High−Side

Switch

High−Side

Switch

High−Side

Switch

High−Side

Switch

High−Side

Switch

Ω)

(1.6

Ω)

(0.3

Ω)

(0.1

(0.3

Low−Side

Switch

Low−Side

Switch

Low−Side

Switch

Low−Side

Switch

Low−Side

Switch

DAC

EC Control

CAN/LIN SBC

Ω)

(1.6

Ω)

(0.3

(1.6

Ω)

(0.3

(NCV7462)

VCC

OUT4

OUT3

OUT2

ECON

OUT8

OUT9

OUT1

mirror

y−axis

ECFB

LIN

mirror

defroster

(NCV7321)

mirror

x−axis

mirror

fold

CAN

LIN

ECM

NCV7706 only

Figure 2. Application Diagram

NCV7705

NCV7706

1

36

1

36

GND

OUT9

OUT8

OUT7

VS

OUT6

OUT5

VS

PWM1

CHP

VS/TEST

n.c.

GND

OUT9

OUT1

OUT2

OUT3

GND

OUT9

OUT1

OUT2

OUT3

VS

SI

OUT9

OUT8

OUT7

ECFB

OUT6

OUT5

VS

SI

ISOUT/PWM2

CSB

VS

ISOUT/PWM2

CSB

PWM1

CHP

ECON

n.c.

SO

VCC

SCLK

n.c.

VCC

SCLK

n.c.

VS

n.c.

OUT4

n.c.

VS

n.c.

OUT4

n.c.

18

GND

19

GND

19

GND

Figure 3. Pin Connections (Top View)

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3

NCV7705, NCV7706

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

GND

Pin Type

Ground

Description

1

2

3

4

5

6

7

8

9

Ground Supply (all GND pins have to be connected externally)

Heater Output (has to be connected externally to pin 35)

Mirror common Output

OUT9

OUT1

OUT2

OUT3

VS

HS driver Output

Half bridge driver Output

Supply

Mirror x/y control Output

Battery Supply Input (all VS pins have to be connected externally)

SPI interface Serial Data Input

VS

Supply

SI

Digital Input

ISOUT/PWM2

Digital Input /

Analog Output

PWM control Input / Current Sense Output. This pin is a bidirectional pin.

Depending on the selected multiplexer bits, an image of the instant current of

the corresponding HS stage can be read out.

This pin can also be used as PWM control input pin for OUT6 and OUT8.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CSB

SO

Digital Input

Digital Output

Supply

SPI interface Chip Select

SPI interface Serial Data Output

VCC

SCLK

n.c.

Logic Supply Input

Digital Input

SPI interface Shift Clock

Not connected

VS

Supply

Battery Supply Input (all VS pins have to be connected externally)

n.c.

Not connected

n.c.

Not connected

GND

n.c.

Ground

Ground Supply (all GND pins have to be connected externally)

Not connected

n.c.

Not connected

OUT4

n.c.

Half bridge driver Output

Mirror Fold Output

Not connected

n.c.

Not connected

VS/TEST

Supply

Test Input, has to be connected to VS in application

(NCV7705 only)

ECON

(NCV7706 only)

ECM driver Output

Electrochromic mirror control DAC output. If the Electrochrome feature is

selected, this output controls an external Mosfet, otherwise it remains in

high−impedance state.

If the electrochrome feature is not used in the application and not selected via

SPI the pin can be connected to VS.

26

27

28

29

30

31

32

CHP

PWM1

VS

Analog Output

Digital Input

Supply

Reverse Polarity FET Control Output

PWM control Input for OUT1−4, OUT5/7, OUT9

Battery Supply Input (all VS pins have to be connected externally)

LED / Bulb Output

VS

Supply

OUT5

OUT6

HS driver Output

Supply

LED / Bulb Output

VS

Connect to VS pins externally (no power connection)

(NCV7705 only)

ECFB

ECM Input / Output

Electrochromic Mirror Feedback Input, Fast discharge transistor Output

(NCV7706 only)

33

34

35

36

OUT7

OUT8

HS driver Output

Ground

LED Output

OUT9

Heater Output (has to be connected externally to pin 2)

Ground Supply (all GND pins have to be connected externally)

Substrate; Heat slug has to be connected to all GND pins

GND

Heat slug

Ground

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4

NCV7705, NCV7706

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Min

Max

Unit

Vs

Power supply voltage

− Continuous supply voltage

− Transient supply voltage (t < 500 ms, ”clamped load dump”)

V

−0.3

28

40

V

Logic supply

−0.3

5.5

V

CC

Vdig

Visout/pwm2

Vchp

DC voltage at all logic pins (SO, SI, SCLK, CSB, PWM1)

Current monitor output / PWM2 logic input

Charge pump output (the most stringent value is applied)

V

+ 0.3

CC

+ 0.3

−25

40

Vs − 25

Vs + 15

Voutx,

Vecon, Vecfb

Static output voltage (OUT1−9, ECON, ECFB)

OUT1/4 Output current

−0.3

Vs + 0.3

V

A

Iout1/4

Iout2/3

Iout5

− T > 25°C

−5

−5.5

5

5.5

J

− T < 25°C

J

OUT2/3 Output current

A

− T > 25°C

−1.25

−1.35

1.35

J

− T < 25°C

J

OUT5 Output current

− DC

− Transient

−5

−2.5

−1.25

−10

5

Iout6

OUT6 Output current

− DC

− Transient

A

2.5

1.25

Iout7/8

Iout9

OUT7/8 Output current

− DC

− Transient

A

OUT9 Output current

− DC

A

− Transient

10

Iout_ecfb

(NCV7706

only)

ECFB Output current

1.25

A

ESD_HBM

ESD Voltage, Human Body Model (HBM); (100 pF, 1500 W) (Note 1)

− All pins

− Output pins OUT1−4 and ECFB to GND (all unzapped pins grounded)

kV

V

−2

−4

2

4

ESD_CDM

ESD according to CDM (Charge Device Model) (Note 1)

− All pins

− Corner pins

−500

−750

500

750

T

Operating junction temperature range

Storage temperature range

−40

−55

150

°C

J

Tstg

MSL

Moisture sensitivity level (Note 2)

MSL3

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Charge Device Model tested per EIA/JES D22/C101, Field Induced Charge Model

2. For soldering information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

THERMAL CHARACTERISTICS

Symbol

Rating

Value

Unit

R

Thermal Characteristics, SSOP36−EP, 1−layer PCB

Thermal Resistance, Junction−to−Air (Note 3)

49.4

°C/W

θJA

R

Thermal Characteristics, SSOP36−EP, 4−layer PCB

Thermal Resistance, Junction−to−Air (Note 4)

24

°C/W

θJA

3. Values based on PCB of 76.2 x 114.3 mm, 72 μm copper thickness, 20% copper area coverage and FR4 PCB substrate.

4. Values based on PCB of 76.2 x 114.3 mm, 72 / 36 μm copper thickness (signal layers / internal planes), 20 / 90% copper area coverage (signal

layers / internal planes) and FR4 PCB substrate.

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5

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

SUPPLY

Functional (see V

Parameter specification

/ V

OV_VS

)

5.5

8

28

18

UV_VS

Vs

Supply voltage

V

Standby mode,

VS = 16 V, 0 V v V v 5.25 V,

CC

Supply Current (VS),

Standby mode

Is(standby)

CSB = V , OUTx/ECx = floating,

3.5

(9)

12

mA

CC

SI = SCLK = 0 V, T < 85°C

J

(T = 150°C)

J

(25)

Active mode,

VS = 16 V,

OUTx/ECx = floating

Supply current (VS),

Active mode

Is(active)

8

20

mA

Standby mode,

Supply Current (VCC),

Standby mode

V

CC

= 5.25 V,

4.5

6

I

(standby)

mA

CC

SI = SCLK = 0 V, T < 85°C

J

(T = 150°C)

(15)

(50)

J

Active mode,

VS = 16 V,

OUTx/ECx = floating

Supply current (VCC),

Active mode

I

(active)

6.5

8

mA

CC

Standby mode,

Total Standby mode supply current

VS = 16 V, T < 85°C,

I(standby)

18

mA

J

(Is + I

)

CC

CSB = V , OUTx/ECx = floating

CC

OVERVOLTAGE AND UNDERVOLTAGE DETECTION

Vuv_vs(on)

VS increasing

5.6

5.2

6.2

5.8

V

VS Undervoltage detection

Vuv_vs(off)

VS decreasing

Vuv_vs(hys)

Vov_vs(off)

Vov_vs(on)

Vov_vs(hys)

Vuv_vcc(off)

Vuv_vcc(on)

Vuv_vcc(hys)

VS Undervoltage hysteresis

Vuv_vs(on) − Vuv_vs(off)

VS increasing

0.65

2

20

19

24.5

23.5

VS Overvoltage detection

VS Overvoltage hysteresis

VS decreasing

Vov_vs(off) − Vov_vs(on)

V

increasing

decreasing

2.9

CC

VCC Undervoltage detection

2

CC

VCC Undervoltage hysteresis

VS Undervoltage filter time

− V

0.11

uv_VCC(off)

uv_VCC(on)

Time to set the power supply fail bit

UOV_OC in the Global Status Byte

td_uv

td_ov

6

13

ms

Time to set the power supply fail bit

UOV_OC in the Global Status Byte

VS Overvoltage filter time

50

100

CHARGE PUMP OUTPUT CHP

Vchp8

Vchp10

Vchp12

Ichp

Chargepump Output Voltage

Vs = 8 V, Ichp = −60 mA

Vs + 6

Vs + 8

Vs + 9.5 Vs + 13

Vs + 11 Vs + 13

V

Chargepump Output Voltage

Chargepump Output current

Vs = 10 V, Ichp = −80 mA

VS > 12 V, Ichp = −100 mA

VS = 13.5 V, Vchp = Vs + 10 V

Vs + 9.5 Vs + 11 Vs + 13

−750 −95

V

mA

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6

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

MIRROR COMMON OUTPUT (X/Y, FOLD) OUT1, OUT4

T = 25°C, Iout1,4 = 1.5 A

0.3

J

Ron_out1,4

On−resistance HS or LS

W

T = 125°C, Iout1,4 = 1.5 A

J

0.6

−3

T < 25°C

−5.5

−5

J

Ioc1,4_hs

Ioc1,4_ls

Overcurrent threshold HS

Overcurrent threshold LS

A

T ≥ 25°C

J

T < 25°C

5.5

5

J

3

T ≥ 25°C

J

Vlim1,4

Vds voltage limitation HS or LS

Underload detection threshold HS

Underload detection threshold LS

Output delay time, HS Driver on

Output delay time, HS Driver off

Output delay time, LS Driver on

Output delay time, LS Driver off

2

−80

5

3

V

mA

ms

Iuld1,4_hs

−5

80

12

Iuld1,4_ls

td_HS1,4(on)

td_HS1,4(off)

td_LS1,4(on)

td_LS1,4(off)

2.5

3

Time from CSB going high to

V(OUT1,4) = 0.1·Vs / 0.9·Vs (on/off)

ms

1

ms

Time from CSB going low to

V(OUT1,4) = 0.9·Vs / 0.1·Vs (on/off)

1.5

ms

Cross conduction protection time,

low−to−high transition including LS

slew−rate

tdLH1,4

tdHL1,4

0.5

5.5

22

ms

Cross conduction protection time,

high−to−low transition including HS

slew−rate

Output HS leakage current,

Active mode

Ileak_act_hs1,4

Ileak_act_ls1,4

V(OUT1,4) = 0 V

V(OUT1,4) = VS

V(OUT1,4) = 0 V

−40

−5

−16

105

mA

Output pull−down current,

Active mode

185

Output HS leakage current,

Standby mode

Ileak_stdby_hs1,4

Ileak_stdby_ls1,4

Output pull−down current,

Standby mode

V(OUT1,4) = VS, T w 25°C

120

175

J

80

V(OUT1,4) = VS, T < 25°C

td_uld1,4

Underload blanking delay

430

16

610

25

ms

tdb_old1,4

Overload shutdown blanking delay Timer started after output activation

Timer started after blanking delay

td_old1,4

frec1,4L

Overload shutdown filter time

elapsed

5

1

25

4

ms

Recovery frequency, slow recovery

CONTROL_3.OCRF = 0

mode

kHz

Recovery frequency, fast recovery

CONTROL_3.OCRF = 1

mode

frec1,4H

dVout1,4

2

6

kHz

Slew rate of HS driver

Vs = 13.5 V, Rload = 16 W to GND

1.3

2.3

3.3

V/ms

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7

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

MIRROR X/Y POSITIONING OUTPUTS OUT2, OUT3

T = 25°C, Iout2,3 = 0.5 A

1.6

W

J

Ron_out2,3

On−resistance HS or LS

T = 125°C, Iout2,3 = 0.5 A

J

3

T < 25°C

J

−1.35

−1.25

J

Ioc2,3_hs

Ioc2,3_ls

Overcurrent threshold HS

Overcurrent threshold LS

−0.75

A

T ≥ 25°C

T < 25°C

1.35

1.25

J

0.75

T ≥ 25°C

J

Vlim2,3

Vds voltage limitation HS or LS

Underload detection threshold HS

Underload detection threshold LS

Output delay time, HS Driver on

Output delay time, HS Driver off

Output delay time, LS Driver on

Output delay time, LS Driver off

2

3

−10

32

6

V

mA

ms

Iuld2,3_hs

−32

10

−20

20

2.5

3

Iuld2,3_ls

td_HS2,3(on)

td_HS2,3(off)

td_LS2,3(on)

td_LS2,3(off)

Time from CSB going high to

V(OUT2,3) = 0.1·Vs / 0.9·Vs (on/off)

6

ms

1

6

ms

Time from CSB going low to

V(OUT2,3) = 0.9·Vs / 0.1·Vs (on/off)

1

6

ms

Cross conduction protection time,

low−to−high transition including LS

slew−rate

tdLH2,3

tdHL2,3

0.5

5.5

22

ms

Cross conduction protection time,

high−to−low transition including HS

slew−rate

Output HS leakage current,

Active mode

Ileak_act_hs2,3

Ileak_act_ls2,3

V(OUT2,3) = 0 V

V(OUT2,3) = VS

V(OUT2,3) = 0 V

−40

−5

−16

105

mA

Output pull−down current,

Active mode

185

Output HS leakage current,

Standby mode

Ileak_stdby_hs2,3

Ileak_stdby_ls2,3

Output pull−down current,

Standby mode

V(OUT2,3) = VS, T w 25°C

120

175

mA

J

80

V(OUT2,3) = VS, T < 25°C

td_uld2,3

Underload blanking delay

430

16

610

25

ms

tdb_old2,3

Overload shutdown blanking delay Timer started after output activation

Timer started after blanking delay

td_old2,3

frec2,3L

Overload shutdown filter time

elapsed

16

1

50

4

ms

Recovery frequency, slow recovery

CONTROL_3.OCRF = 0

mode

kHz

Recovery frequency, fast recovery

CONTROL_3.OCRF = 1

mode

frec2,3H

dVout2,3

2

6

kHz

Slew rate of HS driver

Vs = 13.5 V, Rload = 64 W to GND

1.3

2.3

3.3

V/ms

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8

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

0.3

1.4

Max

Unit

BULB / LED DRIVER OUTPUT OUT5

T = 25°C, Iout5 = −1 A

J

On−resistance to supply,

HS switch, Bulb mode

Ron_out5_ICB

Ron_out5_LED

W

T = 125°C, Iout5 = −1 A

0.6

J

T = 25°C, Iout5 = −0.2 A

J

On−resistance to supply,

HS switch, LED mode

T = 125°C, Iout5 = −0.2 A

3

J

Output current limitation to GND,

Bulb mode

T < 25°C

J

−3.9

−3.7

J

Ilim5_ICB

Ilim5_LED

−2.5

A

T ≥ 25°C

Overcurrent threshold,

LED mode

−1.1

−65

−15

−0.5

−5

48

A

Underload detection threshold,

Bulb mode

Iuld5_ICB

mA

Underload detection threshold,

LED mode

Iuld5_LED

Output delay time, Driver on,

Bulb mode

td_OUT5_ICB(on)

td_OUT5_ICB(off)

td_OUT5_LED(on)

td_OUT5_LED(off)

Ileak_act5

15

21

15

21

Time from CSB going high to

V(OUT5) = 0.1·Vs / 0.9·Vs (on/off);

Rload = 16 W

ms

Output delay time, Driver off,

Bulb mode

48

Output delay time, Driver on,

LED mode

48

Time from CSB going high to

V(OUT5) = 0.1·Vs / 0.9·Vs (on/off);

Rload = 64 W

ms

Output delay time, Driver off,

LED mode

48

Output leakage current,

Active mode

V(OUT5) = 0 V

−15

−5

mA

Output leakage current, Standby

mode

Ileak_stdby5

Ileak_out_vs5

td_uld5_ICB

V(OUT5) = 0 V

V(OUT5) = VS

mA

ms

Output leakage current

1

Underload blanking delay

Bulb mode

1350

430

200

100

200

50

1910

Underload blanking delay

LED mode

td_uld5_LED

tdb_old_ICB5

td_old_ICB5

tdb_old_LED5

td_old_LED5

frec5L

610

290

160

290

100

2.1

6

ms

Overload shutdown blanking delay,

Bulb mode

Timer started after output activation

Overload shutdown filter time, Bulb Timer started after blanking delay

mode

ms

elapsed

Overload shutdown blanking delay,

LED mode

Timer started after output activation

ms

Overload shutdown filter time, LED Timer started after blanking delay

mode

ms

elapsed

Recovery frequency, slow recovery

mode recovery

CONTROL_3.OCRF = 0

1

kHz

Recovery frequency, fast recovery

mode (LED mode only)

frec5H

CONTROL_3.OCRF = 1

2

dVout5_ICB

dVout5_LED

Slew rate, Bulb mode

Slew rate, LED mode

Vs = 13.5 V, Rload = 16 W

Vs = 13.5 V, Rload = 64 W

0.22

V/ms

Slew rate in overcurrent recovery

mode

dVout5_ocr

Vs = 13.5 V, Rload = 16 W

1

2

3

V/ms

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9

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

0.6

1.4

Max

Unit

BULB / LED DRIVER OUTPUT OUT6

T = 25°C, Iout6 = −0.5 A

J

On−resistance to supply,

HS switch, Bulb mode

Ron_out6_ICB

Ron_out6_LED

W

T = 125°C, Iout6 = −0.5 A

1.2

J

T = 25°C, Iout6 = −0.2 A

J

On−resistance to supply,

HS switch, LED mode

T = 125°C, Iout6 = −0.2 A

3

J

Output current limitation to GND,

Bulb mode

T < 25°C

J

−1.95

−1.85

J

Ilim6_ICB

Ilim6_LED

−1.25

A

T ≥ 25°C

Overcurrent threshold,

LED mode

−1.1

−30

−15

−0.5

−2.5

−5

A

Underload detection threshold,

Bulb mode

Iuld6_ICB

mA

Underload detection threshold,

LED mode

Iuld6_LED

Output delay time, Driver on,

Bulb mode

td_OUT6_ICB(on)

td_OUT6_ICB(off)

td_OUT6_LED(on)

td_OUT6_LED(off)

Ileak_act6

15

21

15

21

48

Time from CSB going high to

V(OUT6) = 0.1·Vs / 0.9·Vs (on/off);

Rload = 16 W

ms

Output delay time, Driver off,

Bulb mode

48

Output delay time, Driver on,

LED mode

48

Time from CSB going high to

V(OUT6) = 0.1·Vs / 0.9·Vs (on/off);

Rload = 64 W

ms

Output delay time, Driver off,

LED mode

48

Output leakage current,

Active mode

V(OUT6) = 0 V

−15

−5

mA

Output leakage current, Standby

mode

Ileak_stdy6

Ileak_out_vs6

td_uld6_ICB

V(OUT6) = 0 V

V(OUT6) = VS

mA

ms

Output leakage current

1

Underload blanking delay

Bulb mode

1350

430

200

100

200

50

1910

Underload blanking delay

LED mode

td_uld6_LED

tdb_old_ICB6

td_old_ICB6

tdb_old_LED6

td_old_LED6

frec6L

610

290

160

290

100

2.1

6

ms

Overload shutdown blanking delay,

Bulb mode

Timer started after output activation

Overload shutdown filter time, Bulb Timer started after blanking delay

mode

ms

elapsed

Overload shutdown blanking delay,

LED mode

Timer started after output activation

ms

Overload shutdown filter time, LED Timer started after blanking delay

mode

ms

elapsed

Recovery frequency, slow recovery

mode recovery

CONTROL_3.OCRF = 0

1

kHz

Recovery frequency, fast recovery

mode (LED mode only)

frec6H

CONTROL_3.OCRF = 1

2

dVout6_ICB

dVout6_LED

Slew rate, Bulb mode

Slew rate, LED mode

Vs = 13.5 V, Rload = 16 W

Vs = 13.5 V, Rload = 64 W

0.22

V/ms

Slew rate in overcurrent recovery

mode

dVout6_ocr

Vs = 13.5 V, Rload = 16 W

1

2

3

V/ms

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10

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

LED DRIVER OUTPUTS OUT7, OUT8

T = 25°C, Iout7,8 = −0.2 A

1.4

W

J

On−resistance to supply,

HS switch

Ron_out7,8

T = 125°C, Iout7,8 = −0.2 A

J

3

−0.3

−4

Ioc7,8

Overcurrent threshold

−0.6

−18

A

Iuld7,8

Underload detection threshold

Output delay time, Driver on

Output delay time, Driver off

mA

td_OUT7,8(on)

td_OUT7,8(off)

48

Time from CSB going high to

V(OUT7,8) = 0.1·Vs / 0.9·Vs (on/off)

ms

48

Output leakage current, Active

mode

Ileak_act7,8

V(OUT7,8) = 0 V

−10

−5

18

23

mA

Output leakage current, Standby

mode

Ileak_stdby7,8

V(OUT7,8) = 0 V

V(OUT7,8) = VS

Ileak_out_vs7,8

td_uld7,8

Output leakage current

1

mA

ms

Underload blanking delay

430

200

610

290

tdb_old_OUT7,8 Overload shutdown blanking delay Timer started after output activation

Timer started after blanking delay

ms

td_old_OUT7,8

Overload shutdown filter time

16

1

50

4

ms

elapsed

Recovery frequency, slow recovery

mode

frec7,8L

CONTROL_3.OCRF = 0

kHz

Recovery frequency, fast recovery

mode

frec7,8H

dVout7,8

CONTROL_3.OCRF = 1

2

6

kHz

Slew rate

Vs = 13.5 V, Rload = 64 W

0.2

0.1

V/ms

HEATER OUTPUT OUT9

T = 25°C, Iout9 = −3 A

J

W

On−resistance to supply,

HS switch

Ron_out9

T = 125°C, Iout9 = −3 A

J

0.2

−6

Ioc9

Overcurrent threshold

−10

A

Iuld9

Underload detection threshold

Output delay time, Driver on

Output delay time, Driver off

−300

−30

12

mA

Time from CSB going high to

V(OUT9) = 0.1·Vs / 0.9·Vs (on/off);

Rload = 64 W

td_OUT9(on)

td_OUT9(off)

3

ms

12

Output leakage current, Active

mode

Ileak_act9

V(OUT9) = 0 V

−10

−5

mA

Output leakage current, Standby

mode

Ileak_stdby9

V(OUT9) = 0 V

V(OUT9) = VS

Ileak_out9_vs

td_uld9

Output leakage current

1

mA

ms

Underload blanking delay

430

30

610

48

tdb_old_OUT9

Overload shutdown blanking delay Timer started after output activation

ms

Timer started after blanking delay

td_old_OUT9

frec9L

Overload shutdown blanking delay

elapsed

16

1

25

4

ms

Recovery frequency, slow recovery

CONTROL_3.OCRF = 0

mode

kHz

Recovery frequency, fast recovery

CONTROL_3.OCRF = 1

mode

frec9H

dVout9

2

6

kHz

Slew rate

Vs = 13.5 V, Rload = 4 W

1.3

2.3

3.3

V/ms

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11

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

ELECTROCHROMIC MIRROR CONTROL (ECFB, ECON) (NCV7706 ONLY)

T = 25°C, Iecfb = 0.5 A

1.6

W

J

Ron_ecfb

On−resistance to GND, LS switch

T = 125°C, Iecfb = 0.5 A

J

3

1.25

3

Ilim_ecfb_src

Vlim_ecfb

Output current limitation to GND

Vds voltage limitation

Vs = 13.5 V, V = 5 V

0.75

2

A

CC

Output enabled

V

Iuld_ecfb

Underload detection threshold

Output delay time, LS Driver on

Output delay time, LS Driver off

Vs = 13.5 V, V = 5 V

10

20

1

35

12

15

10

610

48

mA

CC

Vs = 13.5 V, V = 5 V,

td_ecfb(on)

td_ecfb(off)

CC

Rload = 64 W,

ms

2

V(ECFB) = 0.9·VS / 0.1·VS (on /off)

Ileak_ecfb_stdby

Ileak_ecfb_act

td_uld_ecfb

tdb_old_ecfb

Vecfb = Vs, Standby mode

Vecfb = Vs, Active mode

−15

−10

430

30

mA

ms

Output leakage current, LS off

Underload blanking delay

Overload shutdown blanking delay Timer started after output activation

Timer started after blanking delay

td_old_ecfb

Overload shutdown filter time

elapsed

16

50

ms

dVecfb/dt(on/off) Slew rate of ECFB, LS switch

Vs = 13.5 V, V = 5 V, Rload = 64 W

5

V/ms

V

CC

CONTROL_2.FSR = 1

CONTROL_2.FSR = 0

1 LSB = 23.8 mV

1.4

1.12

−1

1.6

1.28

1

Vctrl_max

DNL

Maximum EC control voltage

Differential non linearity

V

LSB

dV_ecfb = Vtarget – Vecfb,

Iecon < 1 mA

gain

Voltage deviation between target

and ECFB

dV_ecfb

mV

−5%

+5%

offset

−1 LSB

+1 LSB

Difference voltage between target

and ECFB sets flag if Vecfb is

below target

dV_ecfb = Vtarget – Vecfb,

Toggle bit STATUS_2.ECLO = 1

dV_ecfb_lo

dV_ecfb_hi

120

mV

Difference voltage between target

and ECFB sets flag if Vecfb is

above target

dV_ecfb = Vtarget – Vecfb,

Toggle bit STATUS_2.ECHI = 1

−120

Vecon_min_hi

Vecon_max_lo

Iecon = −10 mA

Iecon = 10 mA

4.5

0

5.5

0.7

ECON output voltage range

V

Vtarget > Vecfb + 500 mV,

Vecfb = 3.5 V

−100

10

−10

100

mA

Iecon

ECON output current capability

Vtarget < Vecfb – 500 mV,

Vecon = 0.5 V, Vtarget = 1 LSB,

Vecfb = 0.5 V

mA

kW

Vecon = 0.7 V,

Pull−down resistance at ECON in

fast discharge mode

CONTROL_1.ECEN = 1,

CONTROL_1.LSECFB = 1,

CONTROL_1.DAC[5:0] = 0

Recon_pd

5

Iq_econ

t_disc

t_rec

ECON quiescent current

Vecon = Vs, CONTROL_1.ECEN = 0

Config.LSPWM=1

1

mA

ms

Auto−discharge pulse width

Auto−discharge blanking time

230

300

3

360

3.75

Config.LSPWM=1

2.25

PWM discharge threshold level

V(ECON) (Note 5)

Vthdisc_abs

Vthdisc_diff

Config.LSPWM=1

350

−50

400

0

450

50

mV

PWM discharge threshold level

V(ECON) – V(ECFB) (Note 5)

5. If V(ECON) < Vthdisc_abs or V(ECON)−V(ECFB) < Vthdisc_diff then ECON_LOW =1; see description in paragraph Controller for

Electro−chromic Glass

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12

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

CURRENT SENSE MONITOR OUTPUT ISOUT/PWM2

Current Sense output functional

voltage range

Vis

V

CC

= 5 V, Vs = 8−20 V

0

V

CC

− 0.5

V

Current Sense output ratio OUT1/4

12000

10000

Current Sense output ratio OUT9

and 5 (low on−resistance bulb

mode)

K = Iout / Iis,

0 V v Vis v 4.5 V, V = 5 V

Kis

Current Sense output ratio OUT6

(low on−resistance bulb mode)

CC

5000

2000

Current Sense output ratio OUT7/8

and 5/6 (high on−resistance LED

mode)

Current Sense output accuracy

OUT1/4

0.3 V v Vis v 4.5 V, V = 5 V

−12.5% −

1% FS

12.5% +

1% FS

CC

Iout1/4 = 0.5−2.9 A

Current Sense output accuracy

OUT5/6 (low on−resistance bulb

mode)

0.3 V v Vis v 4.5 V, V = 5 V

Iout6 = 0.25−0.65 A

CC

−14% −

1% FS

14% +

1% FS

Iout5 = 0.5−1.3 A,

Current Sense output accuracy

OUT5/6 (high on−resistance LED

mode)

Iis,acc

(Notes 6 and 7)

0.3 V v Vis v 4.5 V, V = 5 V

−14% −

1% FS

14% +

1% FS

CC

Iout5,6 = 0.1−0.3 A

Current Sense output accuracy

OUT7/8

−8% −

1.5% FS

8% +

1.5% FS

0.3 V v Vis v 4.5 V, V = 5 V

CC

Current Sense output accuracy

OUT9

0.3 V v Vis v 4.5 V, V = 5 V

−10% −

1.5% FS

10% +

1.5% FS

CC

Iout9 = 0.5−5.9 A

Blanking time after current sense

selection or driver activation

tis_blank

tis

Current Sense blanking time

Current Sense settling time

50

65

ms

0 V to FSR (full scale range)

230

265

6. Current sense output accuracy = Isout−Isout_ideal relative to Isout_ideal

7. FS (Full scale) = Ioutmax/Kis

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13

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DIGITAL INPUTS CSB, SCLK, PWM1/2, SI

Vinl

Vinh

Input low level

Input high level

Input hysteresis

V

= 5 V

0.3·V

V

CC

0.7·V

CC

Vin_hyst

500

30

mV

V

CC

= 5 V,

Rcsb_pu

Rsclk_pd

Rsi_pd

CSB pull−up resistor

120

60

250

220

kW

0 V < Vcsb < 0.7·V

CC

V

CC

= 5 V,

SCLK pull−down resistor

SI pull−down resistor

PWM1 pull−down resistor

30

Vsclk = 1.5 V

V

CC

= 5 V,

60

Vsi = 1.5 V

V

CC

= 5 V,

Rpwm1_pd

60

Vpwm1 = 1.5 V

V

CC

= 5 V,

Vpwm2 = 1.5 V,

current sense disabled

Rpwm2_pd

Ileak_isout

PWM2 pull−down resistor

30

−2

60

220

kW

Output leakage current

Pin capacitance

current sense enabled

2

mA

Ccsb / sclk /

pwm1/2

0 V < V < 5.25 V (Note 8)

10

pF

CC

DIGITAL INPUTS CSB, SCLK, SI; TIMING

tsclk

Clock period

V

CC

= 5 V

1000

ns

tsclk_h

tsclk_l

Clock high time

Clock low time

115

CSB setup time, CSB low before

rising edge of SCLK

tset_csb

tset_sclk

400

ns

SCLK setup time, SCLK low before

rising edge of CSB

tset_si

SI setup time

SI hold time

200

ns

thold_si

Rise time of input signal SI, SCLK,

CSB

tr_in

tf_in

100

ns

Fall time of input signal SI, SCLK,

CSB

Transfer of SPI−command to input

register, valid before tsact mode

transition delay expires

Minimum CSB high time, switching

from Standby mode

tcsb_hi_stdby

tcsb_hi_min

5

2

10

4

ms

Minimum CSB high time,

Active mode

8. Values based on design and/or characterization.

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14

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DIGITAL OUTPUT SO

Vsol

Output low level

Output high level

Iso = 5 mA

Iso = −5 mA

Vcsb = V

0.2·V

V

CC

Vsoh

0.8·V

CC

,

CC

Ileak_so

Cso

Tristate leakage current

Tristate input capacitance

−10

10

mA

0 V < Vso < V

CC

Vcsb = V

,

CC

pF

0 V < V < 5.25 V (Note 8)

CC

DIGITAL OUTPUT SO; TIMING

tr_so

tf_so

SO rise time

SO fall time

Cso = 100 pF

80

50

140

100

ns

SO enable time from tristate to low Cso = 100 pF, Iload = 1 mA,

ten_so_tril

tdis_so_ltri

ten_so_trih

tdis_so_htri

td_so

100

380

100

380

50

250

450

250

450

250

ns

level

pull−up load to V

CC

SO disable time from low level to

tristate

Cso = 100 pF, Iload = 4 mA,

pull−up load to V

CC

SO enable time from tristate to

high level

Cso = 100 pF, Iload = −1 mA,

pull−down load to GND

SO disable time from high level to Cso = 100 pF, Iload = −4 mA,

tristate

pull−down load to GND

Vso < 0.3·V , or Vso > 0.7·V

Cso = 100 pF

,

CC

SO delay time

8. Values based on design and/or characterization.

0.8 • V

CC

0.2 • V

CSB

CC

t

set_csb

sclk

set_sclk

t

ri_in

csb_hi_min

t

f_in

0.8 • V

CC

SCLK

0.2 • V

CC

t

sclk_h

sclk_l

t

set_si

t

hold_si

0.8 • V

CC

SI

Valid

t

d_so

t

en_so_trix

0.7 • V

0.3 • V

0.7 • V

CC

Valid

SO

Valid

CC

Figure 4. SPI Signals Timing Parameters

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15

NCV7705, NCV7706

ELECTRICAL CHARACTERISTICS (continued)

4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.

CC

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

THERMAL PROTECTION

Tjtw_on

Temperature warning threshold

Thermal warning hysteresis

Thermal shutdown threshold,

Junction temperature

140

160

°C

Tjtw_hys

5

Tjsd_on

Junction temperature

160

180

°C

T increasing

J

Thermal shutdown threshold,

T decreasing

J

Tjsd_off

Tjsd_hys

°C

Thermal shutdown hysteresis

5

Temperature difference between

warning and shutdown threshold

Tjsdtw_delta

20

Filter time for thermal warning and

shutdown

td_tx

TW / TSD Global Status bits

10

100

ms

OPERATING MODES TIMING

Time delay for mode change from

SPI communication ready after V

CC

Unpowered mode into Standby

mode

tact

tsact

tacts

30

ms

reached V

threshold

uv_VCC(off)

Time until output drivers are enabled

after CSB going to high and

CONTROL_0.MODE = 1

Time delay for mode change from

Standby mode into Active mode

210

400

300

Time delay for mode change from Time until output drivers are disabled

Active mode into Standby mode via after CSB going to high and

SPI

CONTROL_0.MODE = 0

INTERNAL PWM CONTROL UNIT (OUT5 – OUT8)

CONTROL_2.PWMI = 1,

PWMx.FSELx = 0

PWMlo

PWMhi

PWM frequency, low selection

PWM frequency, high selection

135

175

170

225

200

260

Hz

CONTROL_2.PWMI = 1,

PWMx.FSELx = 1

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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16

NCV7705, NCV7706

DETAILED OPERATING AND PIN DESCRIPTION

General

monitored for undervoltage conditions supporting a safe

power−up transition. When Vs drops below the

undervoltage threshold Vuv_vs(off) (Vs undervoltage

threshold) all output stages are switched to high−impedance

state and the global status bit UOV_OC is set. This bit is a

multi information bit in the Global Status Byte which is set

in case of overcurrent, Vs over− and undervoltage. In case

of undervoltage the status bit STATUS_2.VSUV is set, too.

Bit CONTROL_3.OVUVR (Vs under−/overvoltage

recovery behavior) can be used to select the desired recovery

behavior after a Vs under−voltage event. In case of OVUVR

= 0, all output stages return to their programmed state as

soon as Vs recovers back to its normal operating range. If

OVUVR is set, the automatic recovery function is disabled

thus the output stages will remain in high−impedance

condition until the status bits have been cleared by the

microcontroller. To avoid high current oscillations in case of

output short to GND and low Vs voltage conditions, it is

recommended to disable the Vs−auto−recovery by setting

OVUVR = 1.

The NCV7705/NCV7706 provides four half−bridge

drivers, five independent high−side outputs and a

programmable PWM control unit for free configuration.

Strict adherence to integrated circuit die temperature is

necessary, with a static maximum die temperature of 150°C.

This may limit the number of drivers enabled at one time.

Output drive control and fault reporting are handled via the

SPI (Serial Peripheral Interface) port. A SPI−controlled

mode control provides a low quiescent sleep current mode

when the device is not being utilized. A pull down is

provided on the SI and SCLK inputs to ensure they default

to a low state in the event of a severed input signal. A pull−up

is provided on the CSB input disabling SPI communication

in the event of an open CSB input.

Supply Concept

Power Supply Scheme − VS and VCC

The Vs power supply voltage is used to supply the half

bridges and the high−side drivers. An all−internal

chargepump is implemented to provide the gate−drive

voltage for the n−channel type high−side transistors. The

VCC voltage is used to supply the logic section of the IC,

including the SPI interface.

Due to the independent logic supply voltage the control

and status information will not be lost in case of a loss of Vs

supply voltage. The device is designed to operate inside the

specified parametric limits if the VCC supply voltage is

within the specified voltage range (4.5 V to 5.25 V).

Between the operational level and the VCC undervoltage

threshold level (Vuv_VCC) it is guaranteed that the device

remains in a safe functional state without any inadvertent

change to logic information.

Chargepump

In Standby mode, the chargepump is disabled. After

enabling the device by setting bit CONTROL_0.MODE to

active (1), the internal oscillator is started and the voltage at

the CHP output pin begins to increase. The output drivers are

enabled after a delay of tsact once MODE was set to active.

Driver Outputs

Output PWM Control

For all half−bridge outputs as well as the HS output OUT9

the device features the possibility to logically combine the

SPI−setting with a PWM signal that can be provided to the

inputs PWM1 and ISOUT/PWM2, respectively. Each of the

outputs has a fixed PWM signal assigned which is shown in

Table 1. The PWM modulation is enabled by the respective

bits in the control registers (CONTROL_2.OUTx_PWMx

and CONTROL_3.OUTx_PWMx). In case of using pin

ISOUT/PWM2, the application design has to take care of

either disabling the current sense feature or to provide

sufficient overdrive capability to maintain proper logic input

levels for the PWM input.

In addition to the external signal control, all lighting

outputs (OUT5−9) can also be PWM controlled via an

internal PWM generator unit. While the PWM frequency

can be individually selected between 170 Hz and 225 Hz

thru bits PWMx.FSELx, the duty cycle can be programmed

with 7 or 10−bits resolution PWMx.PW[6/9:0]. The

selection between the different signal sources for these

Device / Module Ground Concept

The high−side output stages OUT5−9 are designed to

handle DC output voltage conditions down to −0.3 V and

allow for short negative transient currents due to parasitic

line inductances. Therefore the application has to take care

that these ratings are not violated under abnormal operating

conditions (module loss of GND, ground shift if load

connected to external GND) by either implementing

external bypass diodes connected to GND or a direct

connection between load−GND and module−GND. Since

these output stages are designed to drive resistive loads,

restrictions on maximum inductance / clamping energy

apply.

The heat slug is not hard−connected to internal GND rail.

It has to be connected externally.

outputs

is

performed

by

programming

bit

Power Up/Down Control

In order to prevent uncontrolled operation of the device

during power/up down, an undervoltage lockout feature is

CONTROL_2.PWMI. Default value is 0 (external signal

source). The general principle of the PWM generation

control scheme is shown in Figure 5.

implemented. Both supply voltages (V

and Vs) are

CC

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17

NCV7705, NCV7706

Table 1. PWM CONTROL SCHEME

PWM Control Input

CONTROL_2.PWMI = 1

CONFIG.PWM_RESEN=0

PWM1

CONFIG.PWM_RESEN=1

PWM1

Output

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

CONTROL_2.PWMI = 0

PWM1

PWM_5/6.PW5[6:0]

PWM_5/6.PW6[6:0]

PWM_7/8.PW7[6:0]

PWM_7/8.PW8[6:0]

PWM1

PWM_5.PW5[9:0]

PWM_6.PW6[9:0]

PWM_7.PW7[9:0]

PWM_8.PW8[9:0]

PWM1

ISOUT/PWM2

PWM1

ISOUT/PWM2

PWM1

CONTROL_2/3.OUTx_PWMx

PWM1/2

PWM enable

H… Enable Output

external PWM source

&

f2

f1

internal

clock

H … CT

=0

Prescaler

S

R

Counter10 Bit

internal PWM source

[9:3]

[9:0]

10

7

A

B

CONTROL_2.PWMI

A>B

PWM_x/y.FSELx

A

B

A>B

PWM_x/y.PWx[6:0]

CONFIG.PWM_RESEN

9

SPI

PWM_x.PWx[9:0]

SPI

Figure 5. PWM Generation Diagram

Programmable Soft−start Function to Drive Loads with

Inrush Current Behavior

real overload and a non linear load like a bulb. Therefore a

real overload condition can only be qualified by time. It is

recommended to only enable auto−recovery for a minimum

amount of time to drive the connected load into a steady state

condition. After turning off the auto−recovery function, the

respective channel is automatically disabled if the overload

condition still persists.

Loads with startup currents higher than the overcurrent

limits (e.g. inrush current of bulbs, block current of motors

and cold resistance of heaters) can be driven using the

programmable soft−start function (Overcurrent auto−recovery

mode). Each output driver provides a corresponding

overcurrent recovery bit (CONTROL_2/3.OCRx) to control

the output behavior in case of a detected overcurrent event.

If auto−recovery is enabled, the device automatically

re−enables the output after a programmable recovery time.

For all half−bridge outputs as well as the high−side outputs

OUT5−9 and OUT5/6 in LED mode, the recovery frequency

can be selected via SPI. OUT5/6 in bulb mode provides a

fixed recovery frequency. The PWM modulated current will

provide sufficient average current to power up the load (e.g.

heat up the bulb) until the load reaches a steady state

condition. The device itself cannot distinguish between a

Inductive Loads

Each half bridge (OUT1−4) is built by internally

connected low−side and high−side N−MOS transistors. Due

to the built−in body diodes of the output transistors,

inductive loads can be driven at the outputs without external

free−wheeling diodes. The high−side drivers OUT5 to

OUT9 are designed to drive resistive loads. Therefore only

a limited clamping energy (W < 1 mJ) can be dissipated by

the device. For inductive loads (L > 100 mH) an external

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18

NCV7705, NCV7706

freewheeling diode connected between GND and the

corresponding output is required.

The low−side driver at ECFB does not feature any

freewheeling diode or clamping structure to handle

inductive loads.

the electro−chromic element. The target voltage at ECFB is

binary coded with a selectable full scale range (bit

CONTROL_2.FSR). The default clamping value for the

output voltage (CONTROL_2.FSR = 0) is 1.2 V, by setting

CONFIG_1.FSR to “1”, the maximum output voltage is

1.5 V. The resolution of the DAC output voltage is

independent of the full−scale−range selection.

Current Sensing

The charging of the mirror (positive slope) is determined

by the positive slew rate of the transconductance amplifier

and the compensation capacitor, while in case of capacitive

loads, the negative slope is mainly determined by the current

consumption thru the load and its capacitance. To allow fast

settling time changing from higher to lower output voltage

values, the device provides two modes of operation:

Current Sense Output / PWM2 Input (Bidirectional Pin

ISOUT/PWM2)

The current sense output allows a more precise analysis of

the actual state of the load rather than the basic detection of

an under− or overload condition. The sense output provides

an image of the actual load current at the selected high side

driver transistor. The current monitor function is available

for high current half−bridge outputs (OUT1 and OUT4), the

high current high−side output (OUT9) as well as for the all

bulb and LED outputs (OUT5−8).

1. Fast discharge: When the target output voltage is

set to 0 V and bit CONTROL_1.LS_ECFB is set,

the voltage at pin ECFB is pulled to ground by a

1.6 W low−side switch.

2. PWM discharge: In case of PWM discharge being

activated (CONFIG.ECM_LSPWM = 1 and

CONTROL_1.LS_ECFB = 1) (Figure 6):

a. The circuit regulation starts in normal

regulation. The DAC value is turned to new

lower value.

The current sense ratio is fixed for the low resistance

outputs OUT1/4/9 and OUT5/6 (bulb mode) to 1/12000

resp. 1/10000 and for the high ohmic outputs OUT7/8 and

OUT5/6 (LED mode) to 1/2000. To prevent from false

readouts, the signal at pin ISOUT is blanked after switching

on the driver until correct settlement of the circuitry

(> 65 ms). Bits CONTROL_3.IS[3:0] are used to select the

output to be multiplexed to the current sense output.

The NCV7705/NCV7706 provides a sample−and−hold

functionality for the current sense output to enable precise

and simple load current diagnostics even during PWM

operation of the respective output. While in active high−side

output state, the current provided at ISOUT reflects a

(low−pass−filtered) image of the actual output current, the

IS−output current is sampled and held constant as soon as the

HS output transistor is commanded off via PWM (low−side

or high−impedant on half−bridge outputs, high−impedant

on HS−outputs). In case no previous current information is

available in the Sample−and−hold stage (current sense

channel changed while actual channel is commanded off)

the sample stage is reset so that it reflects zero output current.

b. If the loop is detected out of regulation for a

time longer than t_rec (~3 ms), the ECON

voltage is detected low (internal signal

ECON_LOW = 1), the regulator is switched off

(DAC voltage at 0) and the fast discharge

transistor is activated for ~300 ms (t_disc).

During this fast discharge, the ECON output is

pulled low to prevent from shoot−thru currents.

c. At the end of the discharge pulse t_disc the fast

discharge is switched off and the regulation

loop is activated again (with DAC to the correct

wanted value), so the loop goes back to step b.)

and the ECON_LOW comparator is observed

again. Before starting a discharge pulse, the

ECLO and ECHI comparator data is latched.

Electro Chromic Mirror (NCV7706 ONLY)

Controller for Electro−chromic Glass

The feedback loop out of regulation is monitored by

comparing V(ECON) versus V(ECFB) and versus 400 mV.

If the regulation is activated and ECON is below ECFB, or

below 400 mV, then the loop is detected as out of regulation

and internal signal ECON_LOW is made 1. By activating

the PWM discharge feature, the overcurrent recovery

function is automatically disabled, regardless of the setting

in CONTROL_2.OC_ECFB.

The voltage of the electro−chromic element connected at

pin ECFB can be controlled to a target value which is set by

Control Register 1 (bits CONTROL_1.DAC[5:0]). Setting

bit CONTROL_1.ECEN enables this function. At the same

time OUT8 is enabled, regardless of its own control bit

CONTROL_1.HS8 and the respective PWM setting. An

on−chip differential amplifier is used to control an external

logic−level N−MOS pass device that delivers the power to

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19

NCV7705, NCV7706

new ECM target

voltage requested

CSB

V(ECON)

Sampling of

ECON−ECFB

voltage

Vtarget + offset

Vtarget − offset

V(ECFB)

V(ECON)

V(ECFB)

Vtarget,

V(ECFB),

V(ECON)

Vtarget

(CONTROL_1.DAC)

tdisc

disabled

trec

enabled

(on)

LS_ECFB

trec

(off)

switch status

disabled

(5 kW to GND)

ECON status

enabled

ECON_LOW

(internal signal)

V(ECON) < V(ECFB),

out of regulation

Figure 6. PWM Discharge Mode for ECFB

The controller provides a chip−internal diode from ECFB

(Anode) to pin ECON (Cathode) to protect the external

MOSFET. A capacitor of at least 4.7 nF has to be added to

pin ECON for stability of the control loop. It is

recommended to place 220 nF capacitor between ECFB and

ground to increase the stability.

The status of the voltage control loop is reported via SPI.

Bit STATUS_2.ECHI = 1 indicates that the voltage on ECFB

is higher than the programmed target value,

STATUS_2.ECLO = 1 indicates that the ECFB voltage is

below the programmed value. Both status bits are valid if

they are stable for at least 150 ms (settling time of the

regulation loop). If PWM discharge is enabled

(CONFIG.ECM_LSPWM = 1), STATUS_2.ECHI is

latched at the end of the discharge cycle, therefore if set it

indicates that the device is in active discharge operation.

Since OUT8 is the output of a high−side driver, it contains

the same diagnostic functions as the other high−side drivers

(e.g. switch−off during overcurrent condition). In

electro−chrome mode, OUT8 can’t be controlled by PWM.

For noise immunity reasons, it is recommended to place the

loop capacitors at ECON as well as another capacitor

between ECFB and GND as close as possible to the

respective pins.

VS

NCV7706

OUT8

ECON

DAC−EC Control

6

DAC

SI

SCLK

SPI

Electro−Chromic

CSB

4.7 nF

Mirror

ECM

SO

ECFB

Auto

discharge

LS Discharge

Transistor

220 nF

Figure 7. Electro Chromic Mirror Application Diagram

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NCV7705, NCV7706

Openload (Underload) Detection

Diagnostic Functions

The openload detection monitors the load current in the

output stage while the transistor is active. If the load current

is below the openload detection threshold for at least td_uld,

the corresponding bit (ULDx) is set in the status registers

STATUS_1/2. The status of the output remains unchanged.

Once set, ULDx remains set regardless of the actual load

condition. It has to be reset by a read&write access to the

corresponding status register.

All diagnostic functions (overcurrent, underload, power

supply monitoring, thermal warning and thermal shutdown)

are internally filtered. The failure condition has to be valid

for the minimum specified filtering time (td_old, td_uld,

td_uvov and td_tx) before the corresponding status bit in the

status register is set. The filter function is used to improve

the noise immunity of the device. The undercurrent and

temperature warning functions are intended for information

purpose and do not affect the state of the output drivers. An

overcurrent condition disables the corresponding output

driver while a thermal shutdown event disables all outputs

into high impedance state. Depending on the setting of the

overcurrent recovery bits in the input register, the driver can

either perform an auto−retry or remain latched off until the

microcontroller clears the corresponding status bits.

Overtemperature shutdown is latch−off only, without

auto−retry functionality.

Overload Detection

An overcurrent condition is indicated by the flag

(UOV_OC) in the Global Status Byte after a filter time of at

least td_old. The channel dependent overcurrent flags are set

in the status registers (STATUS_0/2.OCx) and the

corresponding driver is switched into high impedance state

to protect the device. Each low−side and high−side driver

stage provides its own overcurrent flag. Resetting this

overcurrent flag automatically re−enables the respective

output (provided it is still enabled thru the Control register).

If the over current recovery function is enabled, the internal

chip logic automatically resets the overcurrent flag after a

fixed delay time, generating a PWM modulated current with

a programmable duty cycle. Otherwise the status bits have

to be cleared by the microcontroller by a read&clear access

to the corresponding status register.

Overvoltage / Undervoltage Shutdown

If the supply voltage Vs rises above the switch off voltage

Vov_vs(off) or falls below Vuv_vs(off), all output

transistors are switched to high−impedance state and the

global status bit UOV_OC (multi information) is set. The

status flag STATUS_2.VSOV, resp. STATUS_2.VSUV is

set, too, to log the over−/under−voltage event. The bit

CONTROL_3.OVUVR can be used to determine the

recovery behavior once the Vs supply voltage gets back into

the specified nominal operating range. OVUVR = 0 enables

auto−recovery, with OVUVR = 1 the output stages remain

in high impedance condition until the status flags have been

cleared. Once set, STATUS2.VSOV / VSUV can only be

reset by a read&clear access to the status register

STATUS_2.

Cross−current Protection

All six half−bridges are protected against cross−currents

by internal circuitry. If one driver is turned off (LS or HS),

the activation of the other driver of the same output will be

automatically delayed by the cross current protection

mechanism until the active driver is safely turned off.

Mode Control

Thermal Warning and Overtemperature Shutdown

The device provides a dual−stage overtemperature

protection. If the junction temperature rises above Tjtw_on,

a temperature warning flag (TW) is set in the Global Status

Byte and can be read via SPI. The control software can then

react onto this overload condition by a controlled disable of

individual outputs. If however the junction temperature

reaches the second threshold Tjsd_on, the thermal shutdown

bit TSD is set in the Global Status Byte and all output stages

are switched into high impedance state to protect the device.

The minimum shutdown delay for overtemperature is td_tx.

The output channels can be re−enabled after the device

cooled down and the TSD flag has been reset by the

microcontroller by setting CONTROL_0.MODE = 0.

Wake−up and Mode Control

Two different modes are available:

• Active mode

• Standby mode

After power−up of VCC the device starts in Standby

mode. Pulling the chip−select signal CSB to low level causes

the device to change into Active mode (analog part active).

After at least 10 ms delay, the first SPI communication is

valid and bit CONTROL_0.MODE can be used to set the

desired mode of operation. If bit MODE remains reset (0) or

CSB remains low longer than tcsb_low_stdby, the device

returns to the Standby mode after an internal delay of max.

8 ms, clearing all register content and setting all output stages

into high impedance state.

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NCV7705, NCV7706

VCC Power−up

Delay (tact)

Output stages Hi−Z

Register content cleared

SPI not ready

SPI Control

General Description

The 4−wire SPI interface establishes a full duplex

synchronous serial communication link between the

NCV7705/NCV7706 and the application’s microcontroller.

The NCV7705/NCV7706 always operates in slave mode

whereas the controller provides the master function. A SPI

access is performed by applying an active−low slave select

signal at CSB. SI is the data input, SO the data output. The

SPI master provides the clock to the NCV7705/NCV7706

via the SCLK input. The digital input data is sampled at the

rising edge at SCLK. The data output SO is in high

impedance state (tri−state) when CSB is high. To readout the

global error flag without sending a complete SPI frame, SO

indicates the corresponding value as soon as CSB is set to

active. With the first rising edge at SCLK after the

high−to−low transition of CSB, the content of the selected

register is transferred into the output shift register.

MODE = 1

or

CSB = 0

Delay (tsact)

MODE = 1

CSB = 0

CSB = 1

and

MODE = 0

Standby

Output stages High−Z

Active

Output stages controlled

thru output registers

Register content cleared

CSB = 0

MODE = 0

and

CSB = 1

Delay timer

expired

Delay (tacts)

Output stages controlled

thru output registers

Register content valid

Figure 8. Mode Transitions Diagram

The NCV7705/NCV7706 provides four control registers

(CONTROL_0/1/2/3), two PWM configuration registers

(PWM_7/8 and PWM_9/10), three status registers

(STATUS_0/1/2) and one general configuration register

(CONFIG). Each of these register contains 16−bit data,

together with the 8−bit frame header (access type, register

address), the SPI frame length is therefore 24 bits. In

addition to the read/write accessible registers, the

NCV7705/NCV7706 provides five 8−bit ID registers

(ID_HEADER, ID_VERSION, ID_CODE1/2 and

ID_SPI−FRAME) with 8−bit data length. The content of

these registers can still be read out by a 24−bit access, the

data is then transferred in the MSB section of the data frame.

CSB

t

0

1

2

3

4

5

21 22 23

SCLK

D18

D23 D22 D21 D20 D19

CSB = 0

D2 D1 D0

SI

t

CONTROL_0 MODE = 1

active

Mode

standby

active

SPI Frame Format

Figure 10 shows the general format of the

NCV7705/NCV7706 SPI frame.

CSB = 0

&

MODE = 0

Mode

standby

active

standby

t

< 8 ms

Figure 9. Mode Timing Diagram

Access

Type

Register Address

Input Data

CSB

SCLK

OC1

FLT

OC0

TF

A5

A4

A3

A2

A1

A0

DI6

DI2

DI1

DI0

DI7

SI

UOV

_OC

SO

RES

TSD

TW

ULD NRDY DO7

DO6

DO2

DO1

DO0

X

Device Status Bits

Address−dependent Data

Figure 10. SPI Frame Format

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22

NCV7705, NCV7706

24−bit SPI Interface

way. The device features a stuck−at−one detection, thus

upon detection of a command = FFFFFFh, the device will be

forced into the Standby mode. All output drivers are

switched off.

Both 24−bit input and output data are MSB first. Each

SPI−input frame consists of a command byte followed by

two data bytes. The data returned on SO within the same

frame always starts with the global status byte. It provides

general status information about the device. It is then

followed by 2 data bytes (in−frame response) which content

depends on the information transmitted in the command

byte. For write access cycles, the global status byte is

followed by the previous content of the addressed register.

Serial Data Out (SO)

The SO data output driver is activated by a logical low

level at the CSB input and will go from high impedance to

a low or high level depending on the global status bit, FLT

(Global Error Flag). The first rising edge of the SCLK input

after a high to low transition of the CSB pin will transfer the

content of the selected register into the data out shift register.

Each subsequent falling edge of the SCLK will shift the next

bit thru SO out of the device.

Chip Select Bar (CSB)

CSB is the SPI input pin which controls the data transfer

of the device. When CSB is high, no data transfer is possible

and the output pin SO is set to high impedance. If CSB goes

low, the serial data transfer is allowed and can be started. The

communication ends when CSB goes high again.

Command Byte / Global Status Byte

Each communication frame starts with a command byte

(Table 2). It consists of an operation code (OP[1:0], Table 3)

which specifies the type of operation (Read, Write, Read &

Clear, Readout Device Information) and a six bit address

(A[5:0], Table 4). If less than six address bits are required,

the remaining bits are unused but are reserved. Both Write

and Read mode allow access to the internal registers of the

device. A “Read & Clear”−access is used to read a status

register and subsequently clear its content. The “Read

Device Information” allows to read out device related

information such as ID−Header, Product Code, Silicon

Version and Category and the SPI−frame ID. While

receiving the command byte, the global status byte is

transmitted to the microcontroller. It contains global fault

information for the device, as shown in Table 6.

Serial Clock (SCLK)

If CSB is set to low, the communication starts with the

rising edge of the SCLK input pin. At each rising edge of

SCLK, the data at the input pin Serial IN (SI) is latched. The

data is shifted out thru the data output pin SO after the falling

edges of SCLK. The clock SCLK must be active only within

the frame time, means when CSB is low. The correct

transmission is monitored by counting the number of clock

pulses during the communication frame. If the number of

SCLK pulses does not correspond to the frame width

indicated in the SPI−frame−ID (Chip ID Register, address

3Eh) the frame will be ignored and the communication

failure bit “TF” in the global status byte will be set. Due to

this safety functionality, daisy chaining the SPI is not

possible. Instead, a parallel operation of the SPI bus by

controlling the CSB signal of the connected ICs is

recommended.

ID Register

Chip ID Information is stored in five special 8−bit ID

registers (Table 5). The content can be read out at the

beginning of the communication.

Serial Data In (SI)

During the rising edges of SCLK (CSB is low), the data

is transferred into the device thru the input pin SI in a serial

Table 2. COMMAND BYTE / GLOBAL STATUS BYTE STRUCTURE

Command Byte (IN) / Global Status Byte (OUT)

23

OP1

FLT

1

22

OP0

TF

0

21

A5

20

A4

TSD

0

19

A3

TW

0

18

17

A1

ULD

0

16

A0

Bit

NCV7705/06 IN

NCV7705/06 OUT

Reset Value

A2

UOV_OC

0

RESB

0

NRDY

1

Table 3. COMMAND BYTE, ACCESS MODE

OP1

OP0

Description

0

1

0

1

0

1

Write Access (W)

Read Access (R)

Read and Clear Access (RC)

Read Device ID (RDID)

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NCV7705, NCV7706

Table 4. COMMAND BYTE, REGISTER ADDRESS

A[5:0]

Access

Description

Content

Control Register

CONTROL_0

00h

R/W

Device mode control, Bridge outputs control

Control Register

CONTROL_1

01h

02h

03h

08h

09h

10h

11h

12h

13h

14h

15h

16h

3Fh

R/W

R/RC

R/W

High−side outputs control, ECM control (NCV7706 only)

Bridge outputs recovery control, PWM enable, ECM setup (NCV7706 only)

High−side outputs recovery control, PWM enable, Current Sense selection

PWM control register for OUT5/6 (7b control only)

PWM control register for OUT7/8 (7b control only)

Bridge outputs Overcurrent diagnosis

Control Register

CONTROL_2

Control Register

CONTROL_3

PWM Control Register

PWM_5/6

PWM Control Register

PWM_7/8

Status Register

STATUS_0

Status Register

STATUS_1

Bridge outputs Underload diagnosis

Status Register

STATUS_2

HS outputs Overcurrent and Underload diagnosis, Vs Over− and Under-

voltage, EC−mirror

PWM Control Register

PWM_5

PWM control register for OUT5 (10b control only)

PWM control register for OUT6 (10b control only)

PWM control register for OUT7 (10b control only)

PWM control register for OUT8 (10b control only)

Mask bits for global fault bits

PWM Control Register

PWM_6

PWM Control Register

PWM_7

PWM Control Register

PWM_8

Configuration Register

CONFIG

Table 5. CHIP ID INFORMATION

A[5:0]

00h

Access

RDID

Description

ID header

Content

4300h

0001h

7700h

01h

Version

02h

Product Code 1

Product Code 2

03h

0500h (NCV7705)

0600h (NCV7706)

3Eh

RDID

SPI−Frame ID

0200h

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NCV7705, NCV7706

Table 6. GLOBAL STATUS BYTE CONTENT

FLT

Global Fault Bit

Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit

is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected

via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of

SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the

Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be masked.

0

1

No fault Condition

Fault Condition

TF

0

SPI Transmission Error

No Error

Error

If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The

frame was ignored and this flag was set.

1

RESB

Reset Bar (Active low)

0

1

Reset

Bit is set to ”0” after a Power−on−Reset or a stuck−at−1 fault at SI (SPI−input data = FFFFFFh)

has been detected. All outputs are disabled.

Normal Operation

TSD

Overtemperature Shutdown

No Thermal

Shutdown

Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including

the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a

SW reset to reactivate the output drivers and the chargepump output.

0

1

Thermal Shutdown

TW

0

Thermal Warning

No Thermal Warning

Thermal Warning

This bit indicates a pre−warning level of the junction temperature. It is maskable by the

Configuration Register (CONFIG.NO_TW).

1

UOV_OC

VS Monitoring, Overcurrent Status

0

1

No Fault

Fault

This bit represents a logical OR combination of under−/overvoltage signals (VS) and overcurrent

signals.

ULD

Underload

This bit represents a logical OR combination of all underload signals. It is maskable by the

Configuration Register (CONFIG.NO_ULDx). It is also possible to deactivate this flag for HS1 or

LS1, only (CONFIG.NO_ULD_HS1/LS1).

0

1

No Underload

Underload

NRDY

Not Ready

0

1

Device Ready

After transition from Standby to Active mode, an internal timer is started to allow the internal

chargepump to settle before any outputs can be activated. This bit is cleared automatically after

the startup is completed.

Device Not Ready

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NCV7705, NCV7706

SPI REGISTERS CONTENT

CONTROL_0 Register

Address: 00h

Bit

D15

D14

D13

D12

D11

D10

D9

−

D8

−

D7

−

D6

−

D5

RW

HS4

0

D4

RW

LS4

0

D3

−

D2

−

D1

−

D0

RW

Access type

Bit name

Reset value

RW

HS1 LS1

HS2 LS2

HS3 LS3

0

MODE

0

HSx

LSx

0

Description

Remark

0

1

default

OUTx High impedance

LSx enabled

If a driver is enabled by the control register AND the

corresponding PWM enable bit is set in CONTROL_2

register, the output is only activated if PWM1 (PWM2)

input signal is high. Since OUT1..OUT4 are

half−bridge outputs, activating both HS and LS at the

same time is prevented by internal logic.

HS/LS Outputs

OUT1−4 Driver

Control

1

0

HSx enabled

1

OUTx High impedance

MODE

Description

Remark

If MODE is set, the device is switched to Active mode.

Resetting MODE forces the device to transition into

Standby mode, all internal memory is cleared and all

output stages are switched into their default state (off).

0

default

Standby

Mode Control

1

Active

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26

NCV7705, NCV7706

CONTROL_1 Register

Address: 01h

NCV7705:

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access type

RW

−

LS

ECFB

Bit name

HS5.1 HS5.0 HS6.1 HS6.0 HS7 HS8 HS9

DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ECEN

0

Reset value

0

NCV7706:

Bit

D15

D14

D13

D12

D11

D10

D9

D8

−

D7

−

D6

−

D5

−

D4

−

D3

−

D2

−

D1

−

D0

−

Access type

Bit name

Reset value

RW

HS5.1 HS5.0 HS6.1 HS6.0 HS7 HS8 HS9

0

HSx.1

HSx.0

Description

Remark

0

default

OUTx High impedance

Output enabled, low

current mode (LED mode)

If a driver is enabled by the control register AND the

corresponding PWM enable bit is set in CONTROL_3

register, the output is only activated if the

corresponding PWM input signal (PWM pin or internal

PWM signal) is high.

HS Outputs

OUT5,6

Control

0

1

Output enabled, high

current mode (bulb mode)

1

0

1

OUTx High impedance

HSx

Description

Remark

If a driver is enabled by the control register AND the

corresponding PWM enable bit is set in CONTROL_3

register, the output is only activated if the

corresponding PWM input signal (PWM pin or internal

PWM signal) is high.

HS Outputs

OUT7−9

Control

0

default

OUTx High impedance

1

OUTx enabled

NCV7706 ONLY:

LS ECFB

Description

Remark

ECFB

Pull−down

Output

Pull−down transistor

disabled (high impedance)

The ECFB−pull−down transistor can only be activated

if the DAC output voltage is set to 0 V (DAC[5:0]=0). If

the PWM enable bit CONTROL_2.ECFB_PWM1 is

set, the output will only be activated when the PWM1

signal input is high.

0

default

Control

Pull−down transistor

enabled

1

NCV7706 ONLY:

DAC[5:0]

Description

Remark

Electrochrom.

Mirror

Reference

Voltage

6

Reference voltage for

ECON/ECFB differential

amplifier

V(DAC) = 1 + (1.5 / 2 ) ⋅ DAC[5:0]

If bit CONTROL_2.FSR=0, the output voltage is

clamped to 1.2 V.

0

n

default

NCV7706 ONLY:

ECEN

Description

Remark

Electrochromic mirror

controller disabled

By enabling the electrochromic mirror controller

(ECEN=1), the output driver for the external pass

transistor (ECON) is enabled. In addition, OUT8 is

activated, regardless of the setting of

CONTROL_1.HS8.

0

Electrochrom.

Mirror Enable

Electrochromic mirror

controller enabled

1

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27

NCV7705, NCV7706

CONTROL_2 Register

Address: 02h

NCV7705:

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access type

RW

−

RW

−

RW

−

RW

−

OUT1 OUT2 OUT3

PWM1 PWM1 PWM1

OUT4

PWM1

Bit name

OCR1 OCR2 OCR3

0

OCR4

0

PWMI

0

Reset value

0

NCV7706:

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access type

RW

−

RW

−

RW

OCR

ECFB

OUT1 OUT2 OUT3

PWM1 PWM1 PWM1

OUT4 ECFB

PWM1 PWM1

Bit name

OCR1 OCR2 OCR3

0

OCR4

0

PWMI

0

FSR

0

Reset value

0

OCRx

Description

Remark

During an overcurrent event the overcurrent status bit

STATUS_0/2.OCx is set and the dedicated output is

switched off. (The global multi bit UOV_OC is set,

also). When the overcurrent recovery bit is enabled,

the output will be reactivated automatically after a

programmable delay time (CONTROL_3.OCRF).

Overcurrent Recovery

disabled

0

default

Overcurrent

Recovery

Overcurrent Recovery

enabled

1

PWMI

Description

Remark

Internal PWM unit

disabled

0

default

The device has three different PWM sources: external

pins PWM1, PWM2 and the internal PWM unit which

can be used to control the lamp drivers in an

PWM Unit

Internal PWM unit

enabled

1

additional way. PWMI selects the internal PWM unit.

OUTx PWM

Description

Remark

For the half−bridge outputs it is possible to select the

PWM input pin PWM1. In this case the dedicated

output (selected in CONTROL_0 register) is on if the

PWM input signal is high. All half−bridges are

controlled by PWM1.

0

default

PWMx not selected

PWM1/2

Selection

1

PWMx selected

NCV7706 ONLY:

FSR

Description

Remark

6

Vout = 1.5 / 2

⋅

DAC[5:0] clamped at

1.2 V

0

default

DAC Full−scale

Range Control

The default voltage at ECFB in electrochrome mode is

clamped at 1.2 V, when FSR=1 the maximum value is

1.5 V.

6

Vout = 1.5 / 2

DAC[5:0]

⋅

1

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28

NCV7705, NCV7706

CONTROL_3 Register

Address: 03h

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type RW

RW

RW RW RW RW

OUT5 OUT6 OUT7 OUT8 OUT9

PWM1 PWM2 PWM1 PWM2 PWM1

Bit name

OCR5 OCR6 OCR7 OCR8 OCR9

OCRF OVUVR IS3 IS2 IS1 IS0

Reset value

0

OCRx

Description

Remark

During an overcurrent event the overcurrent status bit

STATUS_0/2.OCx is set and the dedicated output is

switched off. (The global multi bit UOV_OC is set,

also). When the overcurrent recovery bit is enabled,

the output will be reactivated automatically after a

programmable delay time (CONTROL_3.OCRF).

Overcurrent Recovery

disabled

0

default

Overcurrent

Recovery

Overcurrent Recovery

enabled

1

OUTx PWM

Description

Remark

For the HS outputs it is possible to select the PWM

input pins PWM1, PWM2 or internal PWMI unit

(OUT5−8 only). In this case the dedicated output

(selected in CONTROL_1 register) is on if the PWM

input signal is high. OUT6 and OUT8 are controlled by

PWM2, OUT5,7 and OUT9 are controlled by PWM1.

0

default

PWMx not selected

PWM1/2

Selection

1

PWMx selected

OCRF

Description

Remark

Overcurrent

Recovery

Frequency

Selection

Slow Overcurrent

recovery mode

0

default

If the overcurrent recovery bit is set, the output will be

switched on automatically after a delay time. The

recovery behavior of OUT5,6 in bulb mode is not

affected by this bit.

Fast Overcurrent recovery

mode

1

OVUVR

Description

Remark

Over− and undervoltage

recovery function enabled

Over− /

Under−voltage

Recovery

0

default

If the OV/UV recovery is disabled by setting

OVUVR=1, the status register STATUS_2 bits VSOV

or VSUV have to be cleared after an OV/UV event.

No over− and undervoltage

recovery

1

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29

NCV7705, NCV7706

IS3

0

1

IS2

0

1

0

1

IS1

0

1

0

1

0

1

0

1

IS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Description

OUT1

Remark

current sensing deactivated

OUT4

The current in all high−side power stages

(except of OUT2/3) can be monitored at the

bidirectional multifunctional pin ISOUT/PWM2.

This pin is a multifunctional pin and can be

activated as output by setting the current

selection bits IS[3:0]. The selected high−side

output will be multiplexed to the output ISOUT.

OUT5

Current

Sensing

Selection

OUT6

OUT7

OUT8

OUT9

current sensing deactivated

PWM_5/6 Register

Address: 08h

Bit

D15

D14

D13

D12

RW

D11

RW

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL5 PW5.6 PW5.5 PW5.4 PW5.3 PW5.2 PW5.1 PW5.0 FSEL6 PW6.6 PW6.5 PW6.4 PW6.3 PW6.2 PW6.1 PW6.0

0

PW5[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT5

It is possible to control OUT5 by the internal PWM unit

if bit PWMI is set in the control register CONTROL_2.

If CONFIG.PWM_RESEN is set, OUT5 duty cycle is

controlled by register PWM_5 with 10−bit resolution.

0

default

Duty Cycle for OUT5 =

(PW5[6:0] +1) / 128

1 .. 7Fh

FSEL5

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT5

0

1

default

Bit FSEL5 selects between 170 and 225 Hz PWM

frequency for OUT5.

PW6[6:0]

Description

Remark

It is possible to control OUT6 by the internal PWM

unit if bit PWMI is set in the control register

CONTROL_2. If CONFIG.PWM_RESEN is set,

OUT6 duty cycle is controlled by register PWM_6

with 10−bit resolution.

PWM Duty

Cycle selector

for OUT6

0

Duty Cycle for OUT6

= (PW6[6:0] +1) / 128

1 .. 7Fh

FSEL6

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT6

0

1

default

Bit FSEL6 selects between 170 and 225 Hz PWM

frequency for OUT6.

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30

NCV7705, NCV7706

PWM_7/8 Register

Address: 09h

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL7 PW7.6 PW7.5 PW7.4 PW7.3 PW7.2 PW7.1 PW7.0 FSEL8 PW8.6 PW8.5 PW8.4 PW8.3 PW8.2 PW8.1 PW8.0

0

PW7[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT7

0

default

It is possible to control OUT7 by the internal PWM unit

if bit PWMI is set in the control register CONTROL_2.

If CONFIG.PWM_RESEN is set, OUT7 duty cycle is

controlled by register PWM_7 with 10−bit resolution.

Duty Cycle for OUT7 =

(PW7[6:0] +1) / 128

1 .. 7Fh

FSEL7

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT7

0

1

default

Bit FSEL7 selects between 170 and 225 Hz PWM

frequency for OUT7.

PW8[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT8

It is possible to control OUT8 by the internal PWM unit

if bit PWMI is set in the control register CONTROL_2.

If CONFIG.PWM_RESEN is set, OUT8 duty cycle is

controlled by register PWM_8 with 10−bit resolution.

0

Duty Cycle for OUT8 =

(PW8[6:0] +1) / 128

1 .. 7Fh

FSEL8

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT8

0

1

default

Bit FSEL8 selects between 170 and 225 Hz PWM

frequency for OUT8.

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31

NCV7705, NCV7706

STATUS_0 Register

Address: 10h

Bit

D15

R/RC R/RC R/RC R/RC R/RC R/RC

OC OC OC OC OC OC

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

−

R/RC R/RC

−

OC

HS4

OC

LS4

Bit Name

0

HS1 LS1 HS2 LS2 HS3 LS3

Reset Value

0

OCx

0

Description

Remark

During an overcurrent event in one of the HS or LS, the belonging

overcurrent status bit STATUS_0.OCx is set and the dedicated

output is switched off. (The global multi bit UOV_OC is set, also).

When the overcurrent recovery bit is enabled, the output will be

reactivated automatically after a programmable delay time

(CONTROL_3.OCRF). If the overcurrent recovery bit is not set the

microcontroller has to clear the OC failure bit and to reactivate the

output stage again.

No overcurrent

detected

OUT1−4

Overcurrent

Detection

1

Overcurrent detected

STATUS_1 Register

Address: 11h

Bit

D15

D14

D13

D12

D11

D10

D9

−

D8

−

D7

−

D6

−

D5

D4

D3

−

D2

−

D1

−

D0

−

Access Type

Bit Name

R/RC R/RC R/RC R/RC R/RC R/RC

ULD ULD ULD ULD ULD ULD

R/RC R/RC

ULD ULD

0

HS1 LS1

HS2 LS2

HS3 LS3

HS4

LS4

Reset Value

0

ULDx

Description

Remark

For each output stage an underload status bit ULD is available. The

underload detection is done in “on−mode”. If the load current is

below the undercurrent detection threshold for at least td_uld, the

corresponding underload bit ULDx is set.

If an ULD event occurs the global status bit ULD will be set.

For ULD_HS1 and ULD_LS1 it is possible to deactivate the global

ULD failure bit by setting the configuration bits

0

1

No underload detected

Underload detected

OUT1−4

Underload

Detection

CONFIG.NO_ULD_HS1/LS1. With setting

CONFIG.NO_ULD_OUTn the global ULD failure bit is deactivated

in general.

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32

NCV7705, NCV7706

STATUS_2 Register

Address: 12h

NCV7705:

Bit

D15

R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC

OC ULD OC ULD OC ULD OC ULD OC ULD

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access type

−

R/RC R/RC

VSUV VSOV

−

Bit name

0

HS5 HS5 HS6 HS6 HS7 HS7 HS8 HS8 HS9 HS9

Reset value

0

NCV7706:

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access type

R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC

OC ULD OC ULD OC ULD OC ULD OC ULD OC ULD

HS5 HS5 HS6 HS6 HS7 HS7 HS8 HS8 HS9 HS9 ECFB ECFB

Bit name

VSUV VSOV ECLO ECHI

Reset value

0

OCx

Description

Remark

During an overcurrent event in one of the HS the belonging

overcurrent status bit STATUS_2.OCx is set and the dedicated

output is switched off. (The global multi bit UOV_OC is set,

also). When the overcurrent recovery bit is enabled, the output

will be reactivated automatically after a programmable delay

time (CONTROL_3.OCRF). If the overcurrent recovery bit is not

set the microcontroller has to clear the OC failure bit and to

reactivate the output stage again.

0

No overcurrent detected

Overcurrent detected

OUT5−9

Overcurrent

Detection

1

ULDx

Description

Remark

For each output stage an underload status bit ULD is available.

The underload detection is done in ”on−mode”. If the load

current is below the undercurrent detection threshold for at

least td_uld, the corresponding underload bit ULDx is set.

0

No underload detected

OUT5−9

Underload

Detection

If an ULD event occurs the global status bit ULD will be set.

1

Underload detected

It is possible to deactivate the global ULD failure bit by setting

the configuration bits CONFIG.NO_ULD_OUTn.

VSUV

Description

Remark

In case of an Vs undervoltage event, the output stages will be

deactivated immediately and the corresponding failure flag will

be set. By default the output stages will be reactivated

automatically after Vs is recovered unless the control bit

CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the

bit VSUV has to be cleared after an UV event.

0

No undervoltage detected

Vs

Undervoltage

1

Undervoltage detected

VSOV

Description

Remark

In case of an Vs overvoltage event, the output stages will be

deactivated immediately and the corresponding failure flag will

be set. By default the output stages will be reactivated

automatically after Vs is recovered unless the control bit

CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the

bit VSOV has to be cleared after an OV event.

0

No overvoltage detected

Vs

Overvoltage

1

Overvoltage detected

ECLO

ECHI

Description

Remark

0

1

0

1

0

1

ECM output regulation in range

ECM output V > Vregulation

ECM output V < Vregulation

not used

Two comparators monitor the voltage at pin ECFB (feedback)

in electrocrome mode. If this voltage is below / above the

programmed target these bits signal the difference after at least

32 ms. The bits are not latched and may toggle after at least

32 ms, if the ECFB voltage has not yet reached the target. They

are not assigned to the Global Error Flag.

EC Mirror

Control

Status

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33

NCV7705, NCV7706

PWM_5 Register

Address: 13h

Bit

D15

D14

−

D13

−

D12

−

D11

−

D10

−

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL5

0

RW

0

PW5.9 PW5.8 PW5.7 PW5.6 PW5.5 PW5.4 PW5.3 PW5.2 PW5.1 PW5.0

0

PW5[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT5

0

default

It is possible to control OUT5 by the internal PWM unit

with 10 bit resolution if bits CONTROL_2.PWMI and

CONFIG.PWM_RESEN are set; PWM_5.PW5[9:0] is

ignored otherwise.

Duty Cycle for OUT5 =

(PW5[9:0] +1) / 1024

1 .. 7Fh

FSEL5

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT5

0

1

default

Bit FSEL5 selects between 170 and 225 Hz PWM

frequency for OUT5.

PWM_6 Register

Address: 14h

Bit

D15

D14

−

D13

D12

D11

D10

−

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL6

0

−

0

−

0

−

0

RW

0

PW6.9 PW6.8 PW6.7 PW6.6 PW6.5 PW6.4 PW6.3 PW6.2 PW6.1 PW6.0

0

PW6[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT6

0

default

It is possible to control OUT6 by the internal PWM unit

with 10 bit resolution if bits CONTROL_2.PWMI and

CONFIG.PWM_RESEN are set; PWM_6.PW6[9:0] is

ignored otherwise.

Duty Cycle for OUT6 =

(PW6[9:0] +1) / 1024

1 .. 7Fh

FSEL6

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT6

0

1

Bit FSEL6 selects between 170 and 225 Hz PWM

frequency for OUT6.

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34

NCV7705, NCV7706

PWM_7 Register

Address: 15h

Bit

D15

D14

−

D13

−

D12

−

D11

−

D10

−

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL7

0

RW

0

PW7.9 PW7.8 PW7.7 PW7.6 PW7.5 PW7.4 PW7.3 PW7.2 PW7.1 PW7.0

0

PW7[6:0]

Description

Remark

PWM Duty

Cycle selector

for OUT7

0

default

It is possible to control OUT7 by the internal PWM unit

with 10 bit resolution if bits CONTROL_2.PWMI and

CONFIG.PWM_RESEN are set; PWM_7.PW7[9:0] is

ignored otherwise.

Duty Cycle for OUT7 =

(PW7[9:0] +1) / 1024

1 .. 7Fh

FSEL7

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT7

0

1

default

Bit FSEL7 selects between 170 and 225 Hz PWM

frequency for OUT7.

PWM_8 Register

Address: 16h

Bit

D15

D14

−

D13

D12

D11

D10

−

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

Bit Name

Reset Value

RW

FSEL8

0

−

0

−

0

−

0

RW

0

PW8.9 PW8.8 PW8.7 PW8.6 PW8.5 PW8.4 PW8.3 PW8.2 PW8.1 PW8.0

0

PW8[9:0]

Description

Remark

PWM Duty

Cycle selector

for OUT8

0

default

It is possible to control OUT8 by the internal PWM unit

with 10 bit resolution if bits CONTROL_2.PWMI and

CONFIG.PWM_RESEN are set; PWM_8.PW8[9:0] is

ignored otherwise.

Duty Cycle for OUT8 =

(PW8[9:0] +1) / 1024

1 .. 7Fh

FSEL8

Description

f(PWM) = 170 Hz

f(PWM) = 225 Hz

Remark

PWM

Frequency

selector for

OUT8

0

1

Bit FSEL8 selects between 170 and 225 Hz PWM

frequency for OUT8.

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35

NCV7705, NCV7706

CONFIG Register

Address: 3Fh

NCV7705:

Bit

D15

D14

D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

−

RW

−

0

−

0

−

0

−

0

−

0

−

RW

−

RW

−

PWM

RESEN

NO_ULD NO_ULD NO_

HS1

NO_ULD

OUTn

Bit Name

0

LS1

TW

Reset Value

0

NCV7706:

Bit

D15

D14

D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Access Type

−

0

RW

−

0

−

0

−

0

−

0

−

0

−

0

RW

−

RW

−

RW

−

PWM

RESEN

ECM

LSPWM

NO_ULD NO_ULD NO_

HS1

NO_ULD

OUTn

Bit Name

0

LS1

TW

Reset Value

0

NO_ULD

HS1

NO_ULD

LS1

Description

Remark

Global underload flag

at HS1/LS1 active

0

1

0

1

0

1

default

For ULD_HS1 and ULD_LS1 it is possible to

deactivate the global ULD failure bit by setting the

configuration bits

Global

Underload Flag

HS1/LS1

No global underload

flag at LS1

CONFIG.NO_ULD_HS1/LS1.With setting

CONFIG.NO_ULD_OUTn the global ULD failure

bit is deactivated in general.

No global underload

flag at HS1

No global underload

flag at HS1/LS1

NO_TW

Description

Remark

Thermal warning flag

active

0

1

default

No Thermal

Warning Flag

The global thermal warning bit TW can be

deactivated.

No thermal warning

flag active

NO_ULD_OUTn

Description

Remark

Global underload flag

active

Global

Undeload Flag

OUTn

0

By setting CONFIG.NO_ULD_OUTn the global

ULD failure bit is deactivated in general.

No global underload

flag active

1

NCV7706 ONLY:

ECM_LSPWM

Description

Remark

LS PWM feature

disabled

If this bit is set, automatic PWM discharge on the

ECM output is enabled. In case of PWM

discharge the Overcurrent recovery feature is

disabled, regardless of the setting of

CONTROL_2.OC_ECFB.

0

ECM PWM

Discharge

LS PWM feature

enabled

1

PWM_RESEN

Description

Remark

By default, 7 bits internal PWM resolution is used

and duty cycle is controlled by registers

PWM_5/6 and PWM_7/8.

0

default

7 bits PWM

Increased

PWM

Resolution

If this bit is set, 10 bits internal PWM resolution is

used and duty cycle is controlled by registers

PWM_5, PWM_6, PWM_7 and PWM_8.

1

10 bits PWM

www.onsemi.com

36

NCV7705, NCV7706

PACKAGE DIMENSIONS

SSOP36 EP

CASE 940AB

ISSUE A

NOTES:

0.20 C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

4X

DETAIL B

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE b DIMENSION AT MMC.

4. DIMENSION b SHALL BE MEASURED BE-

TWEEN 0.10 AND 0.25 FROM THE TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. DIMENSIONS D AND E1 SHALL BE

DETERMINED AT DATUM H.

A

X

36

19

X = A or B

e/2

E1

E

DETAIL B

6. THIS CHAMFER FEATURE IS OPTIONAL. IF

IT IS NOT PRESENT, A PIN ONE IDENTIFIER

MUST BE LOACATED WITHIN THE INDICAT-

ED AREA.

36X

0.25 C

PIN 1

REFERENCE

MILLIMETERS

1

18

DIM MIN

MAX

2.65

0.10

2.60

0.30

0.32

e

A

A1

A2

b

---

36X b

B

M

S

0.25

T A

B

2.15

0.18

0.23

NOTE 6

TOP VIEW

c

h

DETAIL A

A

A2

D

10.30 BSC

H

D2

E

5.70

5.90

10.30 BSC

7.50 BSC

3.90 4.10

0.50 BSC

0.25 0.75

0.90

c

E1

E2

e

h

0.10 C

h

A1

SEATING

PLANE

END VIEW

M1

36X

C

SIDE VIEW

D2

L

0.50

L2

M

0.25 BSC

0

8

_

M1

5

15

_

GAUGE

PLANE

M

E2

L2

SEATING

PLANE

C

36X

L

DETAIL A

BOTTOM VIEW

SOLDERING FOOTPRINT

36X

1.06

5.90

4.10

10.76

1

36X

0.36

0.50

PITCH

DIMENSIONS: MILLIMETERS

www.onsemi.com

37

NCV7705, NCV7706

ON Semiconductor and the

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or

unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable

copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCV7705/D

www.onsemi.com

38


型号：	NCV7705DQR2G
厂家：	ONSEMI
描述：	Mirror-Module Driver-IC
文件：	总38页 (文件大小：269K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV7705DQR2G [ONSEMI]

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