NCV7707DQBR2G [ONSEMI]
Interface Circuit;
| 型号： | NCV7707DQBR2G |
| 厂家： | 
ONSEMI |
| 描述： | Interface Circuit 驱动 光电二极管 接口集成电路 |
| 文件： | 总38页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7707, NCV7707B
Door-Module Driver-IC
The NCV7707/B is a powerful Driver−IC for automotive body
control systems. The IC is designed to control several loads in the front
door of a vehicle. The monolithic IC is able to control mirror functions
like mirror positioning, heating and folding including the
electro−chromic mirror feature. Besides two half−bridge outputs to
control lock and safe−lock motors, the device features four high−side
outputs to drive LEDs or incandescent bulbs (up to 10 W). To allow
maximum flexibility, all lighting outputs can be PWM controlled thru
PWM inputs (external signal source) or by an internal programmable
PWM generator unit. The NCV7707/B is controlled thru a 24 bit SPI
interface with in−frame response.
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SSOP36 EP
CASE 940AB
Features
• Operating Range from 5.5 V to 28 V
• Six High−Side and Six Low−Side Drivers Connected as
Half−Bridges
MARKING DIAGRAM
♦ 2x Half−bridges I
♦ 2x Half−Bridges I
♦ 2x Half−Bridges I
= 0.75 A; R
= 1.6 W @ 25°C
DS(on)
load
= 3 A; R
= 300 mW @ 25°C
= 150 mW @ 25°C
load
DS(on)
NCV7707x
= 6 A; R
load
DS(on)
AWLYYWWG
• Four High−Side Lamp Drivers
♦ 2x LED; I = 0.3 A; R
= 1.4 W @ 25°C
DS(on)
load
♦ 2x 10 W; configurable as LED Driver; I
= 2.5 A;
load
R
= 300 mW @ 25°C
DS(on)
x
A
WL
YY
WW
G
= blank or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• One High−Side Driver for Mirror Heating; I
= 6 A;
load
R
= 100 mW @ 25°C
DS(on)
• Electro Chromic Mirror Control
♦ 1x 6−Bit Selectable Output Voltage Controller
♦ 1x LS for EC Control; Iload = 0.75 A; R
= 1.6 W @ 25°C
DS(on)
• Independent PWM Functionality for All Outputs
• Integrated Programmable PWM Generator Unit for All Lamp Driver
Outputs
ORDERING INFORMATION
• Programmable Soft−start Function to Drive Loads with Higher
Inrush Currents as Current Limitation Value
• Multiplex Current Sense Analog Output for Advanced Load
Monitoring
†
Shipping
Device
Package
NCV7707DQR2G
SSOP36−EP 1500 / Tape &
(Pb−Free) Reel
NCV7707DQBR2G SSOP36−EP 1500 / Tape &
(Pb−Free) Reel
• Very Low Current Consumption in Standby Mode
• Charge Pump Output to Control an External Reverse Polarity
Protection MOSFET
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• 24−Bit SPI Interface for Output Control and Diagnostic
• Protection Against Short−circuit, Overvoltage and Overtemperature
• AEC−Q100 Qualified and PPAP Capable
• SSOP36−EP Power Package
• This is a Pb−Free Device
Typical Applications
• De−centralized Door Electronic Systems
• Body Control Units (BCUs)
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2016 − Rev. 3
NCV7707/D
NCV7707, NCV7707B
VS
CHP
NCV7707/B
Diagnostic
short circuit
openload
VS
VS
Undervoltage
Lockout
Overvoltage
Lockout
Power−on Reset
Chargepump
OUT1
OUT2
OUT3
overload
overtemperature
overvoltage
undervoltage
VCC
SI
SCLK
CSB
CONTROL_0 Register
Driver
Interface
SO
VS
VS
CONTROL_1 Register
CONTROL_2 Register
CONTROL_3 Register
PWM_7/8 Register
OUT4
OUT4
VS
OUT5
OUT5
PWM
Unit
PWM_9/10 Register
STATUS_0 Register
STATUS_1 Register
VS
VS
OUT6
OUT7
OUT8
OUT9
OUT10
VS
VS
VS
VS
STATUS_2 Register
CONFIG Register
Special Function Register
PWM1
PWM1
PWM2
OUT11
OUT11
ISOUT/PWM2
MUX
ECON
ECFB
DAC
EC Control
6
GND
Figure 1. Block Diagram
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2
NCV7707, NCV7707B
footstep
light
10W
/LED
OUT9
safety
light
10W
/LED
OUT8
safety
light
Vbat
blinker
LED
LED
Switches
VS
OUT10
OUT7
CHP
NCV7707/B
High−Side High−Side
High−Side High−Side
Charge Pump
Switch
Switch
(1.4 W)
Switch
Switch
24−bit
Serial
Data
(1.4 W)
(0.3/1.4 W) (0.3/1.4 W)
SO
SI
Power−on Reset
Interface
SCLK
CSB
Protection:
short circuit
open load
over temperature
VS undervoltage
VS overvoltage
PWM Generator Unit
Logic Control
mC
Logic IN
DAC
EC Control
PWM1
Current Sensing
ISOUT/
PWM2
Rs
PWM
GND
High−Side
Switch
(0.3 W)
High−Side
Switch
(0.15 W)
High−Side
Switch
(0.15 W)
High−Side
Switch
(0.1 W)
High−Side High−Side
High−Side
Switch
(1.6 W)
Switch
Switch
(0.3 W)
(1.6 W)
Low−Side
Switch
(0.15 W)
Low−Side
Switch
(0.3 W)
Low−Side Low−Side
Low−Side
Switch
(1.6 W)
Low−Side
Switch
(0.15 W)
Low−Side
Switch
(0.3 W)
Switch
Switch
CAN/LIN SBC
(NCV7462)
(1.6 W)
(1.6 W)
VCC
OUT6
OUT5
OUT4
lock
OUT3
OUT2
OUT1
mirror
y−axis
ECON
OUT10
ECFB
OUT11
LIN
mirror
defroster
(NCV7321)
safe lock
mirror
x−axis
mirror
fold
CAN
LIN
ECM
Figure 2. Application Diagram
GND
OUT11
OUT1
OUT2
OUT3
VS
1
36
GND
OUT11
OUT10
OUT9
ECFB
OUT8
OUT7
VS
VS
SI
ISOUT/PWM2
CSB
VS
PWM1
CHP
SO
VCC
ECON
VS
SCLK
VS
VS
VS
OUT6
OUT5
OUT5
GND
OUT4
OUT4
GND
18
19
Figure 3. Pin Connections (Top View)
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3
NCV7707, NCV7707B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
GND
Pin Type
Ground
Description
1
2
Ground Supply (all GND pins have to be connected externally)
Heater Output (has to be connected externally to pin 35)
OUT11
HS driver Output
Half bridge driver
Output
3
4
5
OUT1
OUT2
OUT3
Mirror common Output
Mirror x/y control Output
Mirror x/y control Output
Half bridge driver
Output
Half bridge driver
Output
6
7
8
VS
VS
SI
Supply
Supply
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
SPI interface Serial Data Input
Digital Input
PWM control Input / Current Sense Output. This pin is a bidirectional pin. Depend-
ing on the selected multiplexer bits, an image of the instant current of the corres-
ponding HS stage can be read out.
ISOUT /
PWM2
Digital Input /
Analog Output
9
This pin can also be used as PWM control input pin for OUT5, OUT8 and OUT10.
10
11
12
13
14
15
CSB
SO
Digital Input
Digital Output
Supply
SPI interface Chip Select
SPI interface Serial Data Output
VCC
SCLK
VS
Logic Supply Input
Digital Input
Supply
SPI interface Shift Clock
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
VS
Supply
Half bridge driver
Output
16
17
OUT4
OUT4
Door Lock Output (has to be connected externally to pin 17)
Door Lock Output (has to be connected externally to pin 16)
Half bridge driver
Output
18
19
GND
GND
Ground
Ground
Ground Supply (all GND pins have to be connected externally)
Ground Supply (all GND pins have to be connected externally)
Half bridge driver
Output
20
21
22
OUT5
OUT5
OUT6
Door Lock Output (has to be connected externally to pin 21)
Door Lock Output (has to be connected externally to pin 20)
Safe−Lock / Mirror Fold Output
Half bridge driver
Output
Half bridge driver
Output
23
24
VS
VS
Supply
Supply
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
Electrochromic mirror control DAC output. If the Electrochrome feature is selec-
ted, this output controls an external Mosfet, otherwise it remains in high−imped-
ance state.
25
ECON
ECM driver Output
If the electrochrome feature is not used in the application and not selected via SPI
the pin can be connected to VS.
26
27
28
29
30
31
32
33
34
35
36
CHP
PWM1
VS
Analog Output
Digital Input
Reverse Polarity FET Control Output
PWM control Input for OUT1−4, OUT6/7, OUT9, OUT11
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
LED / Bulb Output
Supply
VS
Supply
OUT7
OUT8
ECFB
OUT9
OUT10
OUT11
GND
HS driver Output
HS driver Output
ECM Input / Output
HS driver Output
HS driver Output
HS driver Output
Ground
LED / Bulb Output
Electrochromic Mirror Feedback Input, Fast discharge transistor Output
LED Output
LED Output
Heater Output (has to be connected externally to pin 2)
Ground Supply (all GND pins have to be connected externally)
Substrate; Heat slug has to be connected to all GND pins
Heat slug
Ground
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4
NCV7707, NCV7707B
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Min
Max
Unit
Power supply voltage
− Continuous supply voltage
− Transient supply voltage (t < 500 ms, ”clamped load dump”)
−0.3
−0.3
28
40
Vs
V
V
Logic supply
−0.3
−0.3
−0.3
5.5
V
V
V
CC
Vdig
DC voltage at all logic pins (SO, SI, SCLK, CSB, PWM1)
Current monitor output / PWM2 logic input
V
V
+ 0.3
CC
CC
Visout/pwm2
+ 0.3
−25
Vs − 25
40
Vs + 15
Vchp
Charge pump output (the most stringent value is applied)
Static output voltage (OUT1−11, ECON, ECFB)
V
V
Voutx,
Vecon, Vecfb
−0.3
Vs + 0.3
Iout1/6
Iout2/3
Iout4/5
Iout7/8
Iout9/10
Iout11
OUT1/6 Output current
OUT2/3 Output current
OUT4/5 Output current
OUT7/8 Output current
OUT9/10 Output current
OUT11 Output current
ECFB Output current
−5
−1.25
−10
5
A
A
A
A
A
A
A
1.25
10
−5
5
−1.25
−10
1.25
10
Iout_ecfb
1.25
ESD Voltage, Human Body Model (HBM); (100 pF, 1500 W) (Note 1)
− All pins
− Output pins OUT1−6 and ECFB to GND (all unzapped pins grounded)
−2
−4
2
4
ESD_HBM
ESD_CDM
kV
V
ESD according to CDM (Charge Device Model) (Note 1)
− All pins
− Corner pins
−500
−750
500
750
T
Operating junction temperature range
Storage temperature range
−40
−55
150
150
°C
°C
J
Tstg
MSL
Moisture sensitivity level (Note 2)
MSL3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charge Device Model tested per EIA/JES D22/C101, Field Induced Charge Model
2. For soldering information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
Thermal Characteristics, SSOP36−EP
R
2.5
°C/W
θJC
Thermal Resistance, Junction−to−Case
Thermal Characteristics, SSOP36−EP, 1−layer PCB
Thermal Resistance, Junction−to−Air (Note 3)
R
42
°C/W
°C/W
θJA
Thermal Characteristics, SSOP36−EP, 4−layer PCB
Thermal Resistance, Junction−to−Air (Note 4)
R
19.5
θJA
3. Values based on PCB of 76.2 x 114.3 mm, 72 μm copper thickness, 20 % copper area coverage and FR4 PCB substrate.
4. Values based on PCB of 76.2 x 114.3 mm, 72 / 36 μm copper thickness (signal layers / internal planes), 20 / 90 % copper area coverage
(signal layers / internal planes) and FR4 PCB substrate.
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5
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SUPPLY
Functional (see V
Parameter specification
/ V
OV_VS
)
5.5
8
28
18
UV_VS
Vs
Supply voltage
V
Standby mode,
VS = 16 V, 0 V v V v 5.25 V,
CC
Supply Current (VS),
Standby mode
Is(standby)
CSB = V , OUTx/ECx = floating,
3.5
(9)
12
mA
CC
SI = SCLK = 0 V, T < 85°C
J
(T = 150°C)
J
(25)
Active mode,
VS = 16 V,
OUTx/ECx = floating
Supply current (VS), Active
mode
Is(active)
8
20
mA
Standby mode,
Supply Current (VCC),
Standby mode
V
CC
= 5.25 V,
4.5
6
I
(standby)
mA
CC
SI = SCLK = 0 V, T < 85°C
J
(T = 150°C)
(15)
(50)
J
Active mode,
VS = 16 V,
OUTx/ECx = floating
Supply current (VCC),
Active mode
I
(active)
6.5
8
8.4
18
mA
CC
Standby mode,
Total Standby mode supply
VS = 16 V, T < 85°C,
I(standby)
mA
J
current (Is + I
)
CC
CSB = V , OUTx/ECx = floating
CC
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
Vuv_vs(on)
Vuv_vs(off)
VS increasing
5.6
5.2
6.2
5.8
V
V
VS Undervoltage detection
VS decreasing
VS Undervoltage
hysteresis
Vuv_vs(hys)
Vuv_vs(on) − Vuv_vs(off)
0.65
V
Vov_vs(off)
Vov_vs(on)
Vov_vs(hys)
Vuv_vcc(off)
Vuv_vcc(on)
VS increasing
VS decreasing
20
19
24.5
23.5
V
V
V
V
V
VS Overvoltage detection
VS Overvoltage hysteresis Vov_vs(off) − Vov_vs(on)
2
V
increasing
decreasing
2.9
CC
CC
VCC Undervoltage
detection
V
2
6
VCC Undervoltage
hysteresis
Vuv_vcc(hys)
td_uvov
V
− V
0.11
V
uv_VCC(off)
uv_VCC(on)
VS Undervoltage /
Overvoltage filter time
Time to set the power supply fail bit
UOV_OC in the Global Status Byte
100
ms
CHARGE PUMP OUTPUT CHP
Chargepump Output
Vchp8
Vchp10
Vchp12
Ichp
Vs = 8 V, Ichp = −60 mA
Vs + 6
Vs + 8
Vs + 9.5
−750
Vs + 9.5
Vs + 11
Vs + 11
Vs + 13
Vs + 13
Vs + 13
−95
V
V
Voltage
Chargepump Output
Voltage
Vs = 10 V, Ichp = −80 mA
VS > 12 V, Ichp = −100 mA
VS = 13.5 V, Vchp = Vs + 10 V
Chargepump Output
Voltage
V
Chargepump Output
current
mA
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6
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
MIRROR COMMON OUTPUT (X/Y, FOLD) OUT1
T = 25°C, Iout1 = 1.5 A
0.3
J
Ron_out1
On−resistance HS or LS
W
T = 125°C, Iout1 = 1.5 A
J
0.6
−3
5
Ioc1_hs
Ioc1_ls
Overcurrent threshold HS
Overcurrent threshold LS
−5
3
A
A
Vds voltage limitation HS
or LS
Vlim1
2
3
V
mA
mA
ms
Underload detection
threshold HS
Iuld1_hs
−80
10
−5
80
12
12
12
12
Underload detection
threshold LS
Iuld1_ls
Output delay time, HS
Driver on
td_HS1(on)
td_HS1(off)
td_LS1(on)
td_LS1(off)
2.5
3
Time from CSB going high to
V(OUT1) = 0.1·Vs / 0.9·Vs (on/off)
Output delay time, HS
Driver off
ms
Output delay time, LS
Driver on
1
ms
Time from CSB going low to
V(OUT1) = 0.9·Vs / 0.1·Vs (on/off)
Output delay time, LS
Driver off
1.5
ms
Cross conduction
protection time,
low−to−high transition
including LS slew−rate
tdLH1
tdHL1
0.5
5.5
22
22
ms
ms
Cross conduction
protection time,
high−to−low transition
including HS slew−rate
Output HS leakage current,
Active mode
Ileak_act_hs1
Ileak_act_ls1
V(OUT1) = 0 V
V(OUT1) = VS
V(OUT1) = 0 V
−40
−5
−16
100
mA
mA
mA
Output pull−down current,
Active mode
160
Output HS leakage current,
Standby mode
Ileak_stdby_hs1
Output pull−down current,
Standby mode
V(OUT1) = VS, T w 25°C
120
175
J
Ileak_stdby_ls1
td_uld1
80
mA
ms
ms
V(OUT1) = VS, T < 25°C
J
Underload blanking delay
430
5
3000
25
Overload shutdown
blanking delay
td_old1
Recovery frequency, slow
recovery mode
frec1L
CONTROL_3.OCRF = 0
1
4
kHz
Recovery frequency, fast
recovery mode
frec1H
dVout1
CONTROL_3.OCRF = 1
2
1
6
3
kHz
Slew rate of HS driver
Vs = 13.5 V, Rload = 16 W to GND
2
V/ms
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7
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
MIRROR X/Y POSITIONING OUTPUTS OUT2, OUT3
T = 25°C, Iout2,3 = 0.5 A
1.6
W
W
A
A
J
Ron_out2,3
On−resistance HS or LS
T = 125°C, Iout2,3 = 0.5 A
J
3
Ioc2,3_hs
Ioc2,3_ls
Overcurrent threshold HS
Overcurrent threshold LS
−1.25
0.75
−0.75
1.25
Vds voltage limitation HS
or LS
Vlim2,3
2
3
−10
30
12
12
12
12
V
mA
mA
ms
Underload detection
threshold HS
Iuld2,3_hs
−30
10
−20
20
2.5
3
Underload detection
threshold LS
Iuld2,3_ls
Output delay time, HS
Driver on
td_HS2,3(on)
td_HS2,3(off)
td_LS2,3(on)
td_LS2,3(off)
Time from CSB going high to
V(OUT2,3) = 0.1·Vs / 0.9·Vs (on/
off)
Output delay time, HS
Driver off
ms
Output delay time, LS
Driver on
1
ms
Time from CSB going low to
V(OUT2,3) = 0.9·Vs / 0.1·Vs (on/
off)
Output delay time, LS
Driver off
1
ms
Cross conduction
protection time,
low−to−high transition
including LS slew−rate
tdLH2,3
tdHL2,3
0.5
5.5
22
22
ms
ms
Cross conduction
protection time,
high−to−low transition
including HS slew−rate
Output HS leakage current,
Active mode
Ileak_act_hs2,3
Ileak_act_ls2,3
V(OUT2,3) = 0 V
V(OUT2,3) = VS
V(OUT2,3) = 0 V
−40
−5
−16
100
mA
mA
mA
Output pull−down current,
Active mode
160
Output HS leakage current,
Standby mode
Ileak_stdby_hs2,3
Output pull−down current,
Standby mode
V(OUT2,3) = VS, T w 25°C
120
175
mA
mA
J
Ileak_stdby_ls2,3
td_uld2,3
80
V(OUT2,3) = VS, T < 25°C
J
Underload blanking delay
430
10
3000
100
ms
ms
Overload shutdown
blanking delay
td_old2,3
Recovery frequency, slow
recovery mode
frec2,3L
CONTROL_3.OCRF = 0
1
4
kHz
Recovery frequency, fast
recovery mode
frec2,3H
dVout2,3
CONTROL_3.OCRF = 1
2
1
6
3
kHz
Slew rate of HS driver
Vs = 13.5 V, Rload = 64 W to GND
2
V/ms
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NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DOOR LOCK OUTPUTS OUT4, OUT5
T = 25°C, Iout4,5 = 3 A
0.15
W
W
A
A
A
J
Ron_out4,5
On−resistance HS or LS
T = 125°C, Iout4,5 = 3 A
J
0.3
−6
Ioc4,5_hs
Ioc4,5_hs_ct
Ioc4,5_ls
Overcurrent threshold HS
Overcurrent threshold HS
Overcurrent threshold LS
T
> 0°C
v 0°C
−10
−10
6
J
J
T
−5.75
10
Vds voltage limitation HS
or LS
Vlim4,5
2
3
V
mA
mA
ms
Underload detection
threshold HS
Iuld4,5_hs
−300
60
−60
300
12
Underload detection
threshold LS
Iuld4,5_ls
Output delay time, HS
Driver on
td_HS4,5 (on)
td_HS4,5 (off)
td_LS4,5 (on)
td_LS4,5 (off)
2.5
3
Time from CSB going high to
V(OUT4,5) = 0.1·Vs / 0.9·Vs (on/
off)
Output delay time, HS
Driver off
12
ms
Output delay time, LS
Driver on
1
12
ms
Time from CSB going low to
V(OUT4,5) = 0.9·Vs / 0.1·Vs (on/
off)
Output delay time, LS
Driver off
1.5
12
ms
Cross conduction
protection time,
low−to−high transition
including LS slew−rate
tdLH4,5
tdHL4,5
0.5
5.5
22
22
ms
ms
Cross conduction
protection time,
high−to−low transition
including HS slew−rate
Output HS leakage current,
Active mode
Ileak_act_hs4,5
Ileak_act_ls4,5
V(OUT4,5) = 0 V
V(OUT4,5) = VS
V(OUT4,5) = 0 V
−40
−5
−17
100
mA
mA
mA
Output pull−down current,
Active mode
160
Output HS leakage current,
Standby mode
Ileak_stdby_hs4,5
Output pull−down current,
Standby mode
V(OUT4,5) = VS, T w 25°C
120
175
mA
mA
J
Ileak_stdby_ls4,5
td_uld4,5
80
V(OUT4,5) = VS, T < 25°C
J
Underload blanking delay
430
10
3000
25
ms
ms
Overload shutdown
blanking delay
td_old4,5
Recovery frequency, slow
recovery mode
frec4,5L
CONTROL_3.OCRF = 0
1
4
kHz
Recovery frequency, fast
recovery mode
frec4,5H
dVout4,5
CONTROL_3.OCRF = 1
2
1
6
3
kHz
Slew rate of HS driver
Vs = 13.5 V, Rload = 4 W to GND
2
V/ms
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9
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SAFE LOCK, MIRROR FOLD OUTPUT OUT6
T = 25°C, Iout6 = 1.5 A
0.3
J
Ron_out6
On−resistance HS or LS
W
T = 125°C, Iout6 = 1.5 A
J
0.6
−3
5
Ioc6_hs
Ioc6_ls
Overcurrent threshold HS
Overcurrent threshold LS
−5
3
A
A
Vds voltage limitation HS
or LS
Vlim
2
3
V
mA
mA
ms
Underload detection
threshold HS
Iuld6_hs
−80
10
−5
80
12
12
12
12
Underload detection
threshold LS
Iuld6_ls
Output delay time, HS
Driver on
td_HS6(on)
td_HS6(off)
td_LS6(on)
td_LS6(off)
2.5
3
Time from CSB going high to
V(OUT6) = 0.1·Vs / 0.9·Vs (on/off)
Output delay time, HS
Driver off
ms
Output delay time, LS
Driver on
1
ms
Time from CSB going low to
V(OUT6) = 0.9·Vs / 0.1·Vs (on/off)
Output delay time, LS
Driver off
1.5
ms
Cross conduction
protection time,
low−to−high transition
including LS slew−rate
tdLH6
tdHL6
0.5
5.5
22
22
ms
ms
Cross conduction
protection time,
high−to−low transition
including HS slew−rate
Output HS leakage current,
Active mode
Ileak_act_hs6
Ileak_act_ls6
V(OUT6) = 0 V
V(OUT6) = VS
V(OUT6) = 0 V
−40
−5
−16
100
mA
mA
mA
Output pull−down current,
Active mode
160
Output pull−down current,
Standby mode
Ileak_stdby_hs6
Output LS leakage current, V(OUT6) = VS, T w 25°C
120
175
mA
mA
J
Ileak_stdby_ls6
td_uld6
80
Standby mode
V(OUT6) = VS, T < 25°C
J
Underload blanking delay
430
5
3000
25
ms
ms
Overload shutdown
blanking delay
td_old6
Recovery frequency, slow
recovery mode
frec6L
CONTROL_3.OCRF = 0
1
4
kHz
Recovery frequency, fast
recovery mode
frec6H
dVout6
CONTROL_3.OCRF = 1
2
1
6
3
kHz
Slew rate of HS driver
Vs = 13.5 V, Rload = 16 W to GND
2
V/ms
www.onsemi.com
10
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
0.3
1.4
Max
Unit
BULB / LED DRIVER OUTPUTS OUT7, OUT8
T = 25°C, Iout7,8 = −1 A
J
On−resistance to supply,
Ron_out7,8_ICB
W
W
HS switch, Bulb mode
T = 125°C, Iout7,8 = −1 A
0.6
J
T = 25°C, Iout7,8 = −0.2 A
J
On−resistance to supply,
Ron_out7,8_LED
HS switch, LED mode
T = 125°C, Iout7,8 = −0.2 A
3
J
Output current limitation to
Ilim7,8_ICB
−3.7
−1.1
−60
−15
−2.5
A
GND, Bulb mode
Overcurrent threshold,
Ilim7,8_LED
−0.5
−5
A
LED mode
Underload detection
Iuld7,8_ICB
mA
mA
threshold, Bulb mode
Underload detection
Iuld7,8_LED
−5
threshold, LED mode
Output delay time, Driver
on,
Bulb mode
td_OUT7,8_ICB(on)
td_OUT7,8_ICB(off)
td_OUT7,8_LED(on)
td_OUT7,8_LED(off)
15
21
15
21
48
48
48
48
Time from CSB going high to
V(OUT7,8) = 0.1·Vs / 0.9·Vs (on/
off);
ms
ms
Output delay time, Driver
off,
Bulb mode
Rload = 16 W
Output delay time, Driver
on,
LED mode
Time from CSB going high to
V(OUT7,8) = 0.1·Vs / 0.9·Vs (on/
off);
Output delay time, Driver
off,
Rload = 64 W
LED mode
Output leakage current,
Active mode
Ileak_act7,8
V(OUT7,8) = 0 V
−15
−5
mA
mA
Output leakage current,
Standby mode
Ileak_stdby7,8
V(OUT7,8) = 0 V
V(OUT7,8) = VS
Ileak_out_vs7,8
td_uld7,8
Output pull−down current
Underload blanking delay
1
mA
430
100
3000
ms
Overload shutdown
blanking delay, Bulb mode
td_old_ICB7,8
td_old_LED7,8
frec7,8L
160
100
2.1
6
ms
ms
Overload shutdown
blanking delay, LED mode
only
10
1
Recovery frequency, slow
recovery mode recovery
CONTROL_3.OCRF = 0
CONTROL_3.OCRF = 1
kHz
kHz
Recovery frequency, fast
recovery mode (LED mode
only)
frec7,8H
2
dVout7,8_ICB
dVout7,8_LED
Slew rate, Bulb mode
Slew rate, LED mode
Vs = 13.5 V, Rload = 16 W
Vs = 13.5 V, Rload = 64 W
0.2
0.2
V/ms
V/ms
Slew rate in overcurrent
recovery mode
dVout7,8_ocr
Vs = 13.5 V, Rload = 5 W
1
2
3
V/ms
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11
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
LED DRIVER OUTPUTS OUT9, OUT10
T = 25°C, Iout9,10 = −0.2 A
1.4
W
W
A
J
On−resistance to supply,
HS switch
Ron_out9,10
T = 125°C, Iout9,10 = −0.2 A
J
3
Ioc9,10
Iuld9,10
Overcurrent threshold
−0.63
−16
−0.38
Underload detection
threshold
−4
48
48
mA
Output delay time, Driver
on
td_OUT(on)9,10
td_OUT(off)9,10
Ileak_act9,10
18
23
Time from CSB going high to
V(OUT9,10) = 0.1·Vs / 0.9·Vs (on/
off)
ms
Output delay time, Driver
off
Output leakage current,
Active mode
V(OUT9,10) = 0 V
−10
−5
mA
mA
Output leakage current,
Standby mode
Ileak_stdby9,10
V(OUT9,10) = 0 V
V(OUT9,10) = VS
Ileak_out_vs9,10 Output pull−down current
1
mA
td_uld9,10
Underload blanking delay
250
10
750
ms
Overload shutdown
blanking delay
td_old_OUT9,10
100
4
ms
Recovery frequency, slow
recovery mode
frec9,10L
CONTROL_3.OCRF = 0
1
2
kHz
Recovery frequency, fast
recovery mode
frec9,10H
dVout9,10
CONTROL_3.OCRF = 1
6
kHz
Slew rate
Vs = 13.5 V, Rload = 64 W
0.2
0.1
V/ms
HEATER OUTPUT OUT11
T = 25°C, Iout11 = −3 A
J
W
W
A
On−resistance to supply,
HS switch
Ron_out11
T = 125°C, Iout11 = −3 A
J
0.2
Ioc11
Overcurrent threshold
−10
−6.0
Underload detection
threshold
Iuld11
−300
−30
12
mA
Output delay time, Driver
on
td_OUT11(on)
td_OUT11(off)
Ileak_act11
3
3
Time from CSB going high to
V(OUT11) = 0.1·Vs / 0.9·Vs (on/off)
ms
Output delay time, Driver
off
12
Output leakage current,
Active mode
V(OUT11) = 0 V
−10
−5
mA
mA
Output leakage current,
Standby mode
Ileak_stdby11
V(OUT11) = 0 V
V(OUT11) = VS
Ileak_out11_vs
td_uld11
Output pull−down current
Underload blanking delay
1
mA
430
5
3000
ms
Overload shutdown
blanking delay
td_old_OUT11
frec11L
25
4
ms
Recovery frequency, slow
recovery mode
CONTROL_3.OCRF = 0
1
kHz
Recovery frequency, fast
recovery mode
frec11H
dVout11
CONTROL_3.OCRF = 1
2
1
6
3
kHz
Slew rate
Vs = 13.5 V, Rload = 4 W
2
V/ms
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12
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
ELECTROCHROMIC MIRROR CONTROL (ECFB, ECON)
T = 25°C, Iecfb = 0.5 A
1.6
W
W
J
On−resistance to GND, LS
switch
Ron_ecfb
T = 125°C, Iecfb = 0.5 A
J
3
1.25
3
Output current limitation to
GND
Ilim_ecfb_src
Vlim_ecfb
Iuld_ecfb
Vs = 13.5V, V = 5 V
0.75
2
A
V
CC
Vds voltage limitation
Output enabled
Underload detection
threshold
Vs = 13.5 V, V = 5 V
10
20
1
30
mA
CC
Output delay time, LS
Driver on
td_ecfb(on)
td_ecfb(off)
12
12
Vs = 13.5 V, V = 5 V,
CC
ms
Rload = 64 W,
Output delay time, LS
Driver off
V(ECFB) = 0.9·VS / 0.1·VS (on /off)
2
Ileak_ecfb_stdby
Ileak_ecfb_act
td_uld_ecfb
Vecfb = Vs, Standby mode
Vecfb = Vs, Active mode
−15
−10
430
15
10
mA
mA
ms
Output leakage current, LS
off
Underload blanking delay
3000
Overload shutdown
blanking delay
td_old_ecfb
10
100
ms
Slew rate of ECFB, LS
switch
Vs = 13.5 V, V = 5 V,
Rload = 64 W
CC
dVecfb/dt(on/off)
5
V/ms
CONTROL_2.FSR = 1
CONTROL_2.FSR = 0
1 LSB = 23.8 mV
1.4
1.12
−1
1.6
1.28
1
V
V
Maximum EC control
voltage
Vctrl_max
DNL
Differential non linearity
LSB
dV_ecfb = Vtarget – Vecfb,
Iecon < 1 mA
gain
Voltage deviation between
target and ECFB
dV_ecfb
mV
−5%
+5%
offset
−1 LSB
+1 LSB
Difference voltage between
target and ECFB sets flag
if Vecfb is below target
dV_ecfb = Vtarget – Vecfb,
Toggle bit STATUS_2.ECLO = 1
dV_ecfb_lo
dV_ecfb_hi
120
mV
mV
Difference voltage between
target and ECFB sets flag
if Vecfb is above target
dV_ecfb = Vtarget – Vecfb,
Toggle bit STATUS_2.ECHI = 1
−120
Vecon_min_hi
Vecon_max_lo
Iecon = −10 mA
Iecon = 10 mA
4.5
0
5.5
0.7
ECON output voltage
range
V
Vtarget > Vecfb + 500 mV,
Vecfb = 3.5 V
−100
−10
mA
ECON output current
capability
Iecon
Vtarget < Vecfb – 500 mV,
Vecon = 1 V, Vtarget = 1 LSB,
Vecfb = 0.5 V
10
100
mA
kW
Vecon = 0.7 V,
Pull−down resistance at
ECON in fast discharge
mode
CONTROL_1.ECEN = 1,
CONTROL_1.LSECFB = 1,
CONTROL_1.DAC[5:0] = 0
Recon_pd
5
Vecon = Vs,
CONTROL_1.ECEN = 0
Iq_econ
t_disc
ECON quiescent current
1
mA
ms
ms
mV
Auto−discharge pulse
width
Config.LSPWM=1
Config.LSPWM=1
Config.LSPWM=1
240
2.25
350
300
3
360
3.75
450
Auto−discharge blanking
time
t_rec
PWM discharge threshold
level V(ECON) (Note 5)
Vthdisc_abs
400
PWM discharge threshold
level V(ECON) – V(ECFB)
(Note 5)
Vthdisc_diff
Config.LSPWM=1
−50
0
50
mV
5. If V(ECON) < Vthdisc_abs or V(ECON)−V(ECFB) < Vthdisc_diff then ECON_LOW =1; see description in paragraph Controller for
Electro−chromic Glass
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13
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
CURRENT SENSE MONITOR OUTPUT ISOUT/PWM2
Current Sense output
functional voltage range
Vis
V
CC
= 5 V, Vs = 8−20 V
0
V
CC
− 1
V
Current Sense output ratio
OUT1/6 and 7/8 (low
on−resistance bulb mode)
10000
9200
2000
Current Sense output ratio
OUT4/5
Kis
(Note 6)
K = Iout / Iis,
0 V v Vis v 4 V, V
= 5 V
CC
Current Sense output ratio
OUT9/10 and 7/8 (high
on−resistance LED mode)
Current Sense output ratio
OUT11
4500
18000
0 V v Vis v 4 V, V = 5 V
CC
Current Sense output
accuracy OUT1/6
Iout1/6 = 1−1.6 A, T w 25°C
−10% − 2% FS
−10% − 2% FS
−22% − 2% FS
10% + 2% FS
15% + 2% FS
22% + 2% FS
J
Iout1/6 = 1−1.6 A, T < 25°C
J
Iout1/6 = 0.5−1 A; 1.6−2.9 A
0 V v Vis v 4 V, V = 5 V,
CC
Current Sense output
accuracy OUT4/5
Iout4/5 = 2.6−3.3 A, T w 25°C
−10% − 2% FS
−10% − 2% FS
−22% − 3% FS
10% + 2% FS
19% + 2% FS
22% + 3% FS
J
Iout4/5 = 2.6−3.3 A, T < 25°C
J
Iout4/5 = 0.5−2.6 A; 3.3−5.9 A
0 V v Vis v 4 V, V = 5 V
CC
Current Sense output
accuracy OUT7/8 (low
on−resistance bulb mode)
Iis,acc
(Notes 7 and 8)
Iout7/8 = 0.6−0.7 A, T w 25°C
−10% − 2% FS
−10% − 2% FS
−20% − 2% FS
10% + 2% FS
18% + 2% FS
20% + 2% FS
J
Iout7/8 = 0.6−0.7 A, T < 25°C
J
Iout7/8 = 0.5−0.6 A; 0.7−1.3 A
0 V v Vis v 4 V, V = 5 V
CC
Current Sense output
accuracy OUT7/8 (high
on−resistance LED mode)
−12%− 2% FS
−12%− 2% FS
−18% − 2% FS
12% + 2% FS
15% + 2% FS
18% + 2% FS
Iout7/8 = 0.14−0.16 A, T w 25°C
J
Iout7/8 = 0.14−0.16 A, T < 25°C
J
Iout7/8 = 0.1−0.14 A; 0.16−0.3 A
0 V v Vis v 4 V, V = 5 V
Iout9/10 = 0.1−0.15 A; 0.25−0.4 A
CC
Current Sense output
accuracy OUT9/10
Iout9/10 = 0.15−0.25 A
−12%− 2% FS
−18% − 2% FS
12% + 2% FS
18% + 2% FS
Current Sense blanking
time
Blanking time after current sense
selection or driver activation
t
50
65
ms
ms
is_blank
t
is
Current Sense settling time 0 V to FSR (full scale range)
230
265
6. Kis trimmed at 150°C to higher value of spec range to be more centered over temp range.
7. Current sense output accuracy = Isout−Isout_ideal relative to Isout_ideal
8. FS (Full scale) = Ioutmax/Kis
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14
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DIGITAL INPUTS CSB, SCLK, PWM1/2, SI
Vinl
Vinh
Input low level
Input high level
Input hysteresis
V
= 5 V
0.3·V
V
V
CC
CC
0.7·V
CC
Vin_hyst
500
30
mV
V
CC
= 5 V
CC
Rcsb_pu
Rsclk_pd
Rsi_pd
CSB pull−up resistor
120
60
250
220
220
220
kW
kW
kW
kW
0 V < Vcsb < 0.7·V
CC
V
CC
= 5 V,
SCLK pull−down resistor
SI pull−down resistor
PWM1 pull−down resistor
30
30
30
Vsclk = 1.5 V
V
CC
= 5 V,
60
Vsi = 1.5 V
V
CC
= 5 V,
Rpwm1_pd
60
Vpwm1 = 1.5 V
V
CC
= 5 V,
Vpwm2 = 1.5 V,
current sense disabled
Rpwm2_pd
Ileak_isout
PWM2 pull−down resistor
30
−1
60
220
kW
Output leakage current
Pin capacitance
current sense enabled
1
mA
Ccsb / sclk /
pwm1/2
0 V < V < 5.25 V (Note 9)
10
pF
CC
DIGITAL INPUTS CSB, SCLK, SI; TIMING
tsclk
Clock period
V
CC
= 5 V
1000
ns
ns
ns
tsclk_h
tsclk_l
Clock high time
Clock low time
115
115
CSB setup time, CSB low
before rising edge of SCLK
tset_csb
tset_sclk
400
400
ns
ns
SCLK setup time, SCLK
low before rising edge of
CSB
tset_si
SI setup time
SI hold time
200
200
ns
ns
thold_si
Rise time of input signal SI,
SCLK, CSB
tr_in
tf_in
100
100
ns
ns
Fall time of input signal SI,
SCLK, CSB
Minimum CSB high time,
switching from Standby
mode
Transfer of SPI−command to input
register, valid before tsact mode
transition delay expires
tcsb_hi_stdby
tcsb_hi_min
5
2
10
4
ms
ms
Minimum CSB high time,
Active mode
9. Values based on design and/or characterization.
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15
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DIGITAL OUTPUT SO
Vsol
Output low level
Iso = 5 mA
Iso = −5 mA
Vcsb = V
0.2·V
V
V
CC
Vsoh
Output high level
0.8·V
CC
,
CC
Ileak_so
Cso
Tristate leakage current
−10
10
10
mA
0 V < Vso < V
CC
Vcsb = V
,
CC
Tristate input capacitance
pF
0 V < V < 5.25 V (Note 9)
CC
DIGITAL OUTPUT SO; TIMING
tr_so
tf_so
SO rise time
SO fall time
Cso = 100 pF
80
50
140
100
ns
ns
Cso = 100 pF
SO enable time from
tristate to low level
Cso = 100 pF, Iload = 1 mA,
ten_so_tril
tdis_so_ltri
ten_so_trih
tdis_so_htri
td_so
100
380
100
380
50
250
450
250
450
250
ns
ns
ns
ns
ns
pull−up load to V
CC
SO disable time from low
level to tristate
Cso = 100 pF, Iload = 4 mA,
pull−up load to V
CC
SO enable time from
tristate to high level
Cso = 100 pF, Iload = −1 mA,
pull−down load to GND
SO disable time from high Cso = 100 pF, Iload = −4 mA,
level to tristate
pull−down load to GND
Vso < 0.3·V , or Vso > 0.7·V
,
CC
CC
SO delay time
Cso = 100 pF
9. Values based on design and/or characterization.
0.8 • V
CC
0.2 • V
CSB
CC
t
t
t
set_csb
sclk
set_sclk
t
t
ri_in
csb_hi_min
t
f_in
0.8 • V
CC
SCLK
0.2 • V
0.2 • V
CC
CC
t
t
sclk_h
sclk_l
t
set_si
t
hold_si
0.8 • V
CC
SI
Valid
Valid
Valid
t
d_so
t
en_so_trix
0.7 • V
0.3 • V
0.7 • V
CC
CC
Valid
SO
Valid
Valid
CC
Figure 4. SPI Signals Timing Parameters
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16
NCV7707, NCV7707B
ELECTRICAL CHARACTERISTICS (continued)
4.5 V < V < 5.25 V, 8 V < Vs < 18 V, −40°C < T < 150°C; unless otherwise noted.
CC
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
THERMAL PROTECTION
Temperature warning
threshold
Tjtw_on
Junction temperature
140
160
°C
°C
Thermal warning
hysteresis
Tjtw_hys
5
Thermal shutdown
threshold,
T increasing
J
Tjsd_on
Junction temperature
Junction temperature
160
160
180
°C
Thermal shutdown
threshold,
T decreasing
J
Tjsd_off
Tjsd_hys
Tjsdtw_delta
td_tx
°C
°C
°C
ms
Thermal shutdown
hysteresis
5
Temperature difference
between warning and
shutdown threshold
20
Filter time for thermal
warning and shutdown
TW / TSD Global Status bits
10
100
OPERATING MODES TIMING
Time delay for mode
SPI communication ready after V
CC
change from Unpowered
mode into Standby mode
tact
tsact
tacts
30
ms
ms
ms
reached V
threshold
uv_VCC(off)
Time delay for mode
change from Standby
mode into Active mode
Time until output drivers are en-
abled after CSB going to high and
CONTROL_0.MODE = 1
170
300
300
Time delay for mode
Time until output drivers are dis-
abled after CSB going to high and
change from Active mode
into Standby mode via SPI CONTROL_0.MODE = 0
INTERNAL PWM CONTROL UNIT (OUT7 – OUT10)
PWM frequency, low
selection
CONTROL_2.PWMI = 1,
PWMx.FSELx = 0
PWMlo
PWMhi
135
175
170
225
190
250
Hz
Hz
PWM frequency, high
selection
CONTROL_2.PWMI = 1,
PWMx.FSELx = 1
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17
NCV7707, NCV7707B
DETAILED OPERATING AND PIN DESCRIPTION
General
monitored for undervoltage conditions supporting a safe
power−up transition. When Vs drops below the
undervoltage threshold Vuv_vs(off) (Vs undervoltage
threshold) all output stages are switched to high−impedance
state and the global status bit UOV_OC is set. This bit is a
multi information bit in the Global Status Byte which is set
in case of overcurrent, Vs over− and undervoltage. In case
of undervoltage the status bit STATUS_2.VSUV is set, too.
Bit CONTROL_3.OVUVR (Vs under−/overvoltage
recovery behavior) can be used to select the desired recovery
behavior after a Vs under−voltage event. In case of OVUVR
= 0, all output stages return to their programmed state as
soon as Vs recovers back to its normal operating range. If
OVUVR is set, the automatic recovery function is disabled
thus the output stages will remain in high−impedance
condition until the status bits have been cleared by the
microcontroller. To avoid high current oscillations in case of
output short to GND and low Vs voltage conditions, it is
recommended to disable the Vs−auto−recovery by setting
OVUVR = 1.
The NCV7707/B provides six half−bridge drivers, five
independent high−side outputs and a programmable PWM
control unit for free configuration. Strict adherence to
integrated circuit die temperature is necessary, with a static
maximum die temperature of 150°C. This may limit the
number of drivers enabled at one time. Output drive control
and fault reporting are handled via the SPI (Serial Peripheral
Interface) port. A SPI−controlled mode control provides a
low quiescent sleep current mode when the device is not
being utilized. A pull down is provided on the SI and SCLK
inputs to ensure they default to a low state in the event of a
severed input signal. A pull−up is provided on the CSB input
disabling SPI communication in the event of an open CSB
input.
Supply Concept
Power Supply Scheme − VS and VCC
The Vs power supply voltage is used to supply the half
bridges and the high−side drivers. An all−internal
chargepump is implemented to provide the gate−drive
voltage for the n−channel type high−side transistors. The
VCC voltage is used to supply the logic section of the IC,
including the SPI interface.
Due to the independent logic supply voltage the control
and status information will not be lost in case of a loss of Vs
supply voltage. The device is designed to operate inside the
specified parametric limits if the VCC supply voltage is
within the specified voltage range (4.5 V to 5.25 V).
Between the operational level and the VCC undervoltage
threshold level (Vuv_VCC) it is guaranteed that the device
remains in a safe functional state without any inadvertent
change to logic information.
Chargepump
In Standby mode, the chargepump is disabled. After
enabling the device by setting bit CONTROL_0.MODE to
active (1), the internal oscillator is started and the voltage at
the CHP output pin begins to increase. The output drivers are
enabled after a delay of tsact once MODE was set to active.
Driver Outputs
Output PWM Control
For all half−bridge outputs as well as the high−side
outputs the device features the possibility to logically
combine the SPI−setting with a PWM signal that can be
provided to the inputs PWM1 and ISOUT/PWM2,
respectively. Each of the outputs has a fixed PWM signal
assigned which is shown in Table 1. The PWM modulation
is enabled by the respective bits in the control registers
Device / Module Ground Concept
The high−side output stages OUT7−11 are designed to
handle DC output voltage conditions down to −0.3 V and
allow for short negative transient currents due to parasitic
line inductances. Therefore the application has to take care
that these ratings are not violated under abnormal operating
conditions (module loss of GND, ground shift if load
connected to external GND) by either implementing
external bypass diodes connected to GND or a direct
connection between load−GND and module−GND. Since
these output stages are designed to drive resistive loads,
restrictions on maximum inductance / clamping energy
apply.
(CONTROL_2.OUTx_PWMx
and
CONTROL_3.OUTx_PWMx). In case of using pin
ISOUT/PWM2, the application design has to take care of
either disabling the current sense feature or to provide
sufficient overdrive capability to maintain proper logic input
levels for the PWM input.
In addition to the external signal control, all lighting
outputs (OUT7−10) can also be PWM controlled via an
internal PWM generator unit. While the PWM frequency
can be individually selected between 170 Hz and 225 Hz
thru bits PWMx.FSELx, the duty cycle can be programmed
with 7−bits resolution PWMx.PW[6:0]. The selection
between the different signal sources for these outputs is
performed by programming bit CONTROL_2.PWMI.
Default value is 0 (external signal source). The general
principle of the PWM generation control scheme is shown
in Figure 5.
The heat slug is not hard−connected to internal GND rail.
It has to be connected externally.
Power Up/Down Control
In order to prevent uncontrolled operation of the device
during power/up down, an undervoltage lockout feature is
implemented. Both supply voltages (V
and Vs) are
CC
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18
NCV7707, NCV7707B
Table 1. PWM CONTROL SCHEME
PWM Control Input
CONTROL_2.PWMI = 0
PWM1
CONTROL_2.PWMI = 1
PWM1
Output
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
PWM1
PWM1
PWM1
PWM1
PWM1
PWM1
ISOUT/PWM2
PWM1
ISOUT/PWM2
PWM1
PWM1
PWM_7/8.PW7[6:0]
PWM_7/8.PW8[6:0]
PWM_9/10.PW9[6:0]
PWM_9/10.PW10[6:0]
PWM1
ISOUT/PWM2
PWM1
ISOUT/PWM2
PWM1
CONTROL_2/3.OUTx_PWMx
PWM enable
PWM1/2
external PWM source
H… Enable Output
&
f2
f1
H … CT=0
internal
clock
Prescaler
S
R
Counter 7 Bit
internal PWM source
7
A
CONTROL_2.PWMI
A>B
PWM_x/y.FSELx
B
7
PWM_x/y.PWx[6:0]
SPI
Figure 5. PWM Generation Diagram
Programmable Soft−start Function to Drive Loads with
Inrush Current Behavior
Loads with startup currents higher than the overcurrent
limits (e.g. inrush current of bulbs, block current of motors
and cold resistance of heaters) can be driven using the
real overload condition can only be qualified by time. It is
recommended to only enable auto−recovery for a minimum
amount of time to drive the connected load into a steady state
condition. After turning off the auto−recovery function, the
respective channel is automatically disabled if the overload
condition still persists.
programmable
auto−recovery mode). Each output driver provides a
corresponding overcurrent recovery bit
soft−start
function
(Overcurrent
Inductive Loads
Each half bridge (OUT1−6) is built by internally
connected low−side and high−side N−MOS transistors. Due
to the built−in body diodes of the output transistors,
inductive loads can be driven at the outputs without external
free−wheeling diodes. The high−side drivers OUT7 to
OUT11 are designed to drive resistive loads. Therefore only
a limited clamping energy (W < 1 mJ) can be dissipated by
the device. For inductive loads (L > 100 mH) an external
freewheeling diode connected between GND and the
corresponding output is required.
(CONTROL_2/3.OCRx) to control the output behavior in
case of a detected overcurrent event. If auto−recovery is
enabled, the device automatically re−enables the output
after a programmable recovery time. For all half−bridge
outputs as well as the high−side outputs OUT9−11 and
OUT7/8 in LED mode, the recovery frequency can be
selected via SPI. OUT7/8 in bulb mode provides a fixed
recovery frequency. The PWM modulated current will
provide sufficient average current to power up the load (e.g.
heat up the bulb) until the load reaches a steady state
condition. The device itself cannot distinguish between a
real overload and a non linear load like a bulb. Therefore a
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19
NCV7707, NCV7707B
The low−side driver at ECFB does not feature any
freewheeling diode or clamping structure to handle
inductive loads.
the electro−chromic element. The target voltage at ECFB is
binary coded with a selectable full scale range (bit
CONTROL_2.FSR). The default clamping value for the
output voltage (CONTROL_2.FSR = 0) is 1.2 V, by setting
CONTROL_2.FSR to “1”, the maximum output voltage is
1.5 V. The resolution of the DAC output voltage is
independent of the full−scale−range selection.
Current Sensing
Current Sense Output / PWM2 Input (Bidirectional Pin
ISOUT/PWM2)
The charging of the mirror (positive slope) is determined
by the positive slew rate of the transconductance amplifier
and the compensation capacitor, while in case of capacitive
loads, the negative slope is mainly determined by the current
consumption thru the load and its capacitance. To allow fast
settling time changing from higher to lower output voltage
values, the device provides two modes of operation:
The current sense output allows a more precise analysis of
the actual state of the load rather than the basic detection of
an under− or overload condition. The sense output provides
an image of the actual load current at the selected high side
driver transistor. The current monitor function is available
for all high current half−bridge outputs (OUT1, OUT4,
OUT5 and OUT6), the high current high−side output
(OUT11) as well as for the all bulb and LED outputs
(OUT7−10).
The current sense ratio is fixed for the low resistance
outputs OUT1/6/11 and OUT7/8 (bulb mode) to 1/10000,
for door lock outputs OUT4/5 to 1/9200 and for the high
ohmic outputs OUT9/10 and OUT7/8 (LED mode) to
1/2000. To prevent from false readouts, the signal at pin
ISOUT is blanked after switching on the driver until correct
settlement of the circuitry (max 65 ms). Bits
CONTROL_3.IS[3:0] are used to select the output to be
multiplexed to the current sense output.
1. Fast discharge: When the target output voltage is
set to 0 V and bit CONTROL_1.LS_ECFB is set,
the voltage at pin ECFB is pulled to ground by a
1.6 W low−side switch.
2. PWM discharge: In case of PWM discharge being
activated (CONFIG.ECM_LSPWM = 1 and
CONTROL_1.LS_ECFB = 1) (Figure 6):
a. The circuit regulation starts in normal
regulation. The DAC value is turned to new
lower value.
b. If the loop is detected out of regulation for a
time longer than t_rec (~3 ms), the ECON
voltage is detected low (internal signal
The NCV7707/B provides
a
sample−and−hold
functionality for the current sense output to enable precise
and simple load current diagnostics even during PWM
operation of the respective output. While in active high−side
output state, the current provided at ISOUT reflects a
(low−pass−filtered) image of the actual output current, the
IS−output current is sampled and held constant as soon as the
HS output transistor is commanded off via PWM (low−side
or high−impedant on half−bridge outputs, high−impedant
on HS−outputs). In case no previous current information is
available in the Sample−and−hold stage (current sense
channel changed while actual channel is commanded off)
the sample stage is reset so that it reflects zero output current.
ECON_LOW = 1), the regulator is switched off
(DAC voltage at 0) and the fast discharge
transistor is activated for ~300 ms (t_disc).
During this fast discharge, the ECON output is
pulled low to prevent from shoot−thru currents.
c. At the end of the discharge pulse t_disc the fast
discharge is switched off and the regulation
loop is activated again (with DAC to the correct
wanted value), so the loop goes back to step b.)
and the ECON_LOW comparator is observed
again. Before starting a discharge pulse, the
ECLO and ECHI comparator data is latched.
Electro Chromic Mirror
Controller for Electro−chromic Glass
The feedback loop out of regulation is monitored by
comparing V(ECON) versus V(ECFB) and versus 400 mV.
If the regulation is activated and ECON is below ECFB, or
below 400 mV, then the loop is detected as out of regulation
and internal signal ECON_LOW is made 1. By activating
the PWM discharge feature, the overcurrent recovery
function is automatically disabled, regardless of the setting
in CONTROL_2.OCR_ECFB.
The voltage of the electro−chromic element connected at
pin ECFB can be controlled to a target value which is set by
Control Register 1 (bits CONTROL_1.DAC[5:0]). Setting
bit CONTROL_1.ECEN enables this function. At the same
time OUT10 is enabled, regardless of its own control bit
CONTROL_1.HS10 and the respective PWM setting. An
on−chip differential amplifier is used to control an external
logic−level N−MOS pass device that delivers the power to
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20
NCV7707, NCV7707B
new ECM target
voltage requested
CSB
V(ECON)
Sampling of
ECON−ECFB
voltage
Vtarget + offset
Vtarget − offset
V(ECFB)
V(ECON)
V(ECFB)
Vtarget,
V(ECFB),
V(ECON)
Vtarget
(CONTROL_1.DAC)
tdisc
disabled
trec
enabled
(on)
LS_ECFB
trec
trec
(off)
switch status
disabled
(5 kW to GND)
ECON status
enabled
enabled
ECON_LOW
(internal signal)
V(ECON) < V(ECFB),
out of regulation
Figure 6. PWM Discharge Mode for ECFB
The controller provides a chip−internal diode from ECFB
(Anode) to pin ECON (Cathode) to protect the external
MOSFET. A capacitor of at least 4.7 nF has to be added to
pin ECON for stability of the control loop. It is
recommended to place 220 nF capacitor between ECFB and
ground to increase the stability.
The status of the voltage control loop is reported via SPI.
Bit STATUS_2.ECHI = 1 indicates that the voltage on ECFB
is higher than the programmed target value,
STATUS_2.ECLO = 1 indicates that the ECFB voltage is
below the programmed value. Both status bits are valid if
they are stable for at least 150 ms (settling time of the
regulation loop). If PWM discharge is enabled
(CONFIG.ECM_LSPWM = 1), STATUS_2.ECHI is
latched at the end of the discharge cycle, therefore if set it
indicates that the device is in active discharge operation.
Since OUT10 is the output of a high−side driver, it
contains the same diagnostic functions as the other
high−side drivers (e.g. switch−off during overcurrent
condition). In electro−chrome mode, OUT10 can’t be
controlled by PWM. For noise immunity reasons, it is
recommended to place the loop capacitors at ECON as well
as another capacitor between ECFB and GND as close as
possible to the respective pins.
VS
NCV7707/B
OUT10
ECON
DAC−EC Control
6
DAC
SI
SCLK
SPI
Electro−Chromic
CSB
4.7 nF
Mirror
ECM
SO
ECFB
Auto
discharge
LS Discharge
Transistor
220 nF
Figure 7. Electro Chromic Mirror Application Diagram
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21
NCV7707, NCV7707B
Openload (Underload) Detection
Diagnostic Functions
The openload detection monitors the load current in the
output stage while the transistor is active. If the load current
is below the openload detection threshold for at least td_uld,
the corresponding bit (ULDx) is set in the status registers
STATUS_1/2. The status of the output remains unchanged.
Once set, ULDx remains set regardless of the actual load
condition. It has to be reset by a read&write access to the
corresponding status register.
All diagnostic functions (overcurrent, underload, power
supply monitoring, thermal warning and thermal shutdown)
are internally filtered. The failure condition has to be valid
for the minimum specified filtering time (td_old, td_uld,
td_uvov and td_tx) before the corresponding status bit in the
status register is set. The filter function is used to improve
the noise immunity of the device. The undercurrent and
temperature warning functions are intended for information
purpose and do not affect the state of the output drivers. An
overcurrent condition disables the corresponding output
driver while a thermal shutdown event disables all outputs
into high impedance state. Depending on the setting of the
overcurrent recovery bits in the input register, the driver can
either perform an auto−retry or remain latched off until the
microcontroller clears the corresponding status bits.
Overtemperature shutdown is latch−off only, without
auto−retry functionality.
Overload Detection
An overcurrent condition is indicated by the flag
(UOV_OC) in the Global Status Byte after a filter time of at
least td_old. The channel dependent overcurrent flags are set
in the status registers (STATUS_0/2.OCx) and the
corresponding driver is switched into high impedance state
to protect the device. Each low−side and high−side driver
stage provides its own overcurrent flag. Resetting this
overcurrent flag automatically re−enables the respective
output (provided it is still enabled thru the Control register).
If the over current recovery function is enabled, the internal
chip logic automatically resets the overcurrent flag after a
fixed delay time, generating a PWM modulated current with
a programmable duty cycle. Otherwise the status bits have
to be cleared by the microcontroller by a read&clear access
to the corresponding status register.
Overvoltage / Undervoltage Shutdown
If the supply voltage Vs rises above the switch off voltage
Vov_vs(off) or falls below Vuv_vs(off), all output
transistors are switched to high−impedance state and the
global status bit UOV_OC (multi information) is set. The
status flag STATUS_2.VSOV, resp. STATUS_2.VSUV is
set, too, to log the over−/under−voltage event. The bit
CONTROL_3.OVUVR can be used to determine the
recovery behavior once the Vs supply voltage gets back into
the specified nominal operating range. OVUVR = 0 enables
auto−recovery, with OVUVR = 1 the output stages remain
in high impedance condition until the status flags have been
cleared. Once set, STATUS2.VSOV / VSUV can only be
reset by a read&clear access to the status register
STATUS_2.
Cross−current Protection
All six half−bridges are protected against cross−currents
by internal circuitry. If one driver is turned off (LS or HS),
the activation of the other driver of the same output will be
automatically delayed by the cross current protection
mechanism until the active driver is safely turned off.
Mode Control
Thermal Warning and Overtemperature Shutdown
The device provides a dual−stage overtemperature
protection. If the junction temperature rises above Tjtw_on,
a temperature warning flag (TW) is set in the Global Status
Byte and can be read via SPI. The control software can then
react onto this overload condition by a controlled disable of
individual outputs. If however the junction temperature
reaches the second threshold Tjsd_on, the thermal shutdown
bit TSD is set in the Global Status Byte and all output stages
are switched into high impedance state to protect the device.
The minimum shutdown delay for overtemperature is td_tx.
The output channels can be re−enabled after the device
cooled down and the TSD flag has been reset by the
microcontroller by setting CONTROL_0.MODE = 0.
Wake−up and Mode Control
Two different modes are available:
• Active mode
• Standby mode
After power−up of VCC the device starts in Standby
mode. Pulling the chip−select signal CSB to low level causes
the device to change into Active mode (analog part active).
After at least 10 ms delay, the first SPI communication is
valid and bit CONTROL_0.MODE can be used to set the
desired mode of operation. If bit MODE remains reset (0),
the device returns to the Standby mode after an internal
delay of max. 8 ms, clearing all register content and setting
all output stages into high impedance state.
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22
NCV7707, NCV7707B
VCC Power−up
Delay (tact)
Output stages Hi−Z
Register content cleared
SPI not ready
SPI Control
General Description
The 4−wire SPI interface establishes a full duplex
synchronous serial communication link between the
NCV7707/B and the application’s microcontroller. The
NCV7707/B always operates in slave mode whereas the
controller provides the master function. A SPI access is
performed by applying an active−low slave select signal at
CSB. SI is the data input, SO the data output. The SPI master
provides the clock to the NCV7707/B via the SCLK input.
The digital input data is sampled at the rising edge at SCLK.
The data output SO is in high impedance state (tri−state)
when CSB is high. To readout the global error flag without
sending a complete SPI frame, SO indicates the
corresponding value as soon as CSB is set to active. With the
first rising edge at SCLK after the high−to−low transition of
CSB, the content of the selected register is transferred into
the output shift register.
MODE = 1
or
CSB = 0
Delay (tsact)
MODE = 1
CSB = 0
CSB = 1
and
MODE = 0
Standby
Output stages High−Z
Active
Output stages controlled
thru output registers
Register content cleared
CSB = 0
MODE = 0
and
CSB = 1
Delay timer
expired
Delay (tacts)
Output stages controlled
thru output registers
Register content valid
Figure 8. Mode Transitions Diagram
The NCV7707/B provides four control registers
(CONTROL_0/1/2/3), two PWM configuration registers
(PWM_7/8 and PWM_9/10), three status registers
(STATUS_0/1/2) and one general configuration register
(CONFIG). Each of these register contains 16−bit data,
together with the 8−bit frame header (access type, register
address), the SPI frame length is therefore 24 bits. In
addition to the read/write accessible registers, the
NCV7707/B provides five 8−bit ID registers
(ID_HEADER, ID_VERSION, ID_CODE1/2 and
ID_SPI−FRAME) with 8−bit data length. The content of
these registers can still be read out by a 24−bit access, the
data is then transferred in the MSB section of the data frame.
CSB
t
t
0
1
2
3
4
5
21 22 23
SCLK
D18
D23 D22 D21 D20 D19
CSB = 0
D2 D1 D0
SI
t
t
CONTROL_0 MODE = 1
active
Mode
standby
active
SPI Frame Format
Figure 10 shows the general format of the NCV7707/B
SPI frame.
CSB = 0
&
MODE = 0
Mode
standby
active
standby
t
< 8 ms
Figure 9. Mode Timing Diagram
Access
Type
Register Address
Input Data
Input Data
CSB
SCLK
OP1
FLT
OP0
TF
A5
A4
A3
A2
A1
A0
DI6
DI2
DI1
DI0
DI7
SI
UOV
_OC
SO
RES
TSD
TW
ULD NRDY DO7
DO6
DO2
DO1
DO0
X
Device Status Bits
Address−dependent Data
Figure 10. SPI Frame Format
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23
NCV7707, NCV7707B
24−bit SPI Interface
way. The device features a stuck−at−one detection, thus
upon detection of a command = FFFFFFh, the device will be
forced into the Standby mode. All output drivers are
switched off.
Both 24−bit input and output data are MSB first. Each
SPI−input frame consists of a command byte followed by
two data bytes. The data returned on SO within the same
frame always starts with the global status byte. It provides
general status information about the device. It is then
followed by 2 data bytes (in−frame response) which content
depends on the information transmitted in the command
byte. For write access cycles, the global status byte is
followed by the previous content of the addressed register.
Serial Data Out (SO)
The SO data output driver is activated by a logical low
level at the CSB input and will go from high impedance to
a low or high level depending on the global status bit, FLT
(Global Error Flag). The first rising edge of the SCLK input
after a high to low transition of the CSB pin will transfer the
content of the selected register into the data out shift register.
Each subsequent falling edge of the SCLK will shift the next
bit thru SO out of the device.
Chip Select Bar (CSB)
CSB is the SPI input pin which controls the data transfer
of the device. When CSB is high, no data transfer is possible
and the output pin SO is set to high impedance. If CSB goes
low, the serial data transfer is allowed and can be started. The
communication ends when CSB goes high again.
Command Byte / Global Status Byte
Each communication frame starts with a command byte
(Table 2). It consists of an operation code (OP[1:0], Table 3)
which specifies the type of operation (Read, Write, Read &
Clear, Readout Device Information) and a six bit address
(A[5:0], Table 4). If less than six address bits are required,
the remaining bits are unused but are reserved. Both Write
and Read mode allow access to the internal registers of the
device. A “Read & Clear”−access is used to read a status
register and subsequently clear its content. The “Read
Device Information” allows to read out device related
information such as ID−Header, Product Code, Silicon
Version and Category and the SPI−frame ID. While
receiving the command byte, the global status byte is
transmitted to the microcontroller. It contains global fault
information for the device, as shown in Table 6.
Serial Clock (SCLK)
If CSB is set to low, the communication starts with the
rising edge of the SCLK input pin. At each rising edge of
SCLK, the data at the input pin Serial IN (SI) is latched. The
data is shifted out thru the data output pin SO after the falling
edges of SCLK. The clock SCLK must be active only within
the frame time, means when CSB is low. The correct
transmission is monitored by counting the number of clock
pulses during the communication frame. If the number of
SCLK pulses does not correspond to the frame width
indicated in the SPI−frame−ID (Chip ID Register, address
3Eh) the frame will be ignored and the communication
failure bit “TF” in the global status byte will be set. Due to
this safety functionality, daisy chaining the SPI is not
possible. Instead, a parallel operation of the SPI bus by
controlling the CSB signal of the connected ICs is
recommended.
ID Register
Chip ID Information is stored in five special 8−bit ID
registers (Table 5). The content can be read out at the
beginning of the communication.
Serial Data In (SI)
During the rising edges of SCLK (CSB is low), the data
is transferred into the device thru the input pin SI in a serial
Table 2. COMMAND BYTE / GLOBAL STATUS BYTE STRUCTURE
Command Byte (IN) / Global Status Byte (OUT)
23
OP1
FLT
1
22
OP0
TF
0
21
A5
20
A4
TSD
0
19
A3
TW
0
18
17
A1
ULD
0
16
A0
Bit
NCV7707 IN
A2
UOV_OC
0
NCV7707 OUT
Reset Value
RESB
0
NRDY
1
Table 3. COMMAND BYTE, ACCESS MODE
OP1
OP0
Description
0
0
1
1
0
1
0
1
Write Access (W)
Read Access (R)
Read and Clear Access (RC)
Read Device ID (RDID)
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NCV7707, NCV7707B
Table 4. COMMAND BYTE, REGISTER ADDRESS
A[5:0]
Access
Description
Content
Control Register
CONTROL_0
00h
R/W
Device mode control, Bridge outputs control
High−side outputs control, ECM control
Control Register
CONTROL_1
01h
02h
03h
08h
09h
10h
11h
12h
3Fh
R/W
R/W
Control Register
CONTROL_2
Bridge outputs recovery control, PWM enable, ECM setup
High−side outputs recovery control, PWM enable, Current Sense selection
PWM control register for OUT7,8
Control Register
CONTROL_3
R/W
PWM Control Register
PWM_7/8
R/W
PWM Control Register
PWM_9/10
R/W
PWM control register for OUT9,10
Status Register
STATUS_0
R/RC
R/RC
R/RC
R/W
Bridge outputs Overcurrent diagnosis
Status Register
STATUS_1
Bridge outputs Underload diagnosis
Status Register
STATUS_2
HS outputs Overcurrent and Underload diagnosis, Vs Over− and Under-
voltage, EC−mirror
Configuration Register
CONFIG
Mask bits for global fault bits
Table 5. CHIP ID INFORMATION
A[5:0]
00h
Access
RDID
Description
ID header
Version
Content
4300h
01h
RDID
0400h (NCV7707)
0500h (NCV7707B)
02h
03h
3Eh
RDID
RDID
RDID
Product Code 1
Product Code 2
SPI−Frame ID
7700h
0700h
0200h
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25
NCV7707, NCV7707B
Table 6. Global Status Byte Content
FLT
Global Fault Bit
Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit
is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected
via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of
SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the
Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be
masked.
0
1
No fault Condition
Fault Condition
TF
0
SPI Transmission Error
No Error
Error
If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The
frame was ignored and this flag was set.
1
RESB
Reset Bar (Active low)
0
1
Reset
Bit is set to ”0” after a Power−on−Reset or a stuck−at−1 fault at SI (SPI−input data = FFFFFFh)
has been detected. All outputs are disabled.
Normal Operation
TSD
Overtemperature Shutdown
No Thermal
Shutdown
Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including
the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a
SW reset to reactivate the output drivers and the chargepump output.
0
1
Thermal Shutdown
TW
0
Thermal Warning
No Thermal Warning
Thermal Warning
This bit indicates a pre−warning level of the junction temperature. It is maskable by the
Configuration Register (CONFIG.NO_TW).
1
UOV_OC
VS Monitoring, Overcurrent Status
0
1
No Fault
Fault
This bit represents a logical OR combination of under−/overvoltage signals (VS) and overcurrent
signals.
ULD
Underload
This bit represents a logical OR combination of all underload signals. It is maskable by the
Configuration Register (CONFIG.NO_ULDx). It is also possible to deactivate this flag for HS1 or
LS1, only (CONFIG.NO_ULD_HS1/LS1).
0
1
No Underload
Underload
NRDY
Not Ready
0
1
Device Ready
After transition from Standby to Active mode, an internal timer is started to allow the internal
chargepump to settle before any outputs can be activated. This bit is cleared automatically after
the startup is completed.
Device Not Ready
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26
NCV7707, NCV7707B
SPI REGISTERS CONTENT
CONTROL_0 Register
Address: 00h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
RW
LS6
0
D3
−
D2
−
D1
−
D0
RW
Access type
Bit name
Reset value
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
HS1 LS1
HS2 LS2
HS3 LS3
HS4 LS4 HS5
LS5 HS6
0
0
0
MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSx
LSx
0
Description
Remark
0
0
1
1
default
OUTx High impedance
LSx enabled
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_2
register, the output is only activated if PWM1 (PWM2)
input signal is high. Since OUT1..OUT6 are
half−bridge outputs, activating both HS and LS at the
same time is prevented by internal logic.
HS/LS Outputs
OUT1−6 Driver
Control
1
0
HSx enabled
1
OUTx High impedance
MODE
Description
Remark
If MODE is set, the device is switched to Active mode.
Resetting MODE forces the device to transition into
Standby mode, all internal memory is cleared and all
output stages are switched into their default state
(off).
0
default
Standby
Mode Control
1
Active
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27
NCV7707, NCV7707B
CONTROL_1 Register
Address: 01h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
−
LS
ECFB
Bit name
HS7.1 HS7.0 HS8.1 HS8.0 HS9 HS10 HS11
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ECEN
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSx.1
HSx.0
Description
Remark
0
0
default
OUTx High impedance
Output enabled, low
current mode (LED
mode)
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
0
1
HS Outputs
OUT7,8
Control
Output enabled, high
current mode (bulb
mode)
1
1
0
1
OUTx High impedance
HSx
Description
Remark
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
HS Outputs
OUT9−11
Control
0
default
OUTx High impedance
1
OUTx enabled
LS ECFB
Description
Remark
Pull−down transistor
disabled (high
impedance)
The ECFB−pull−down transistor can only be activated
if the DAC output voltage is set to 0 V (DAC[5:0]=0). If
the PWM enable bit CONTROL_2.ECFB_PWM1 is
set, the output will only be activated when the PWM1
signal input is high.
ECFB
Pull−down
Output Control
0
default
Pull−down transistor
enabled
1
DAC[5:0]
Description
Remark
Electrochrom.
Mirror
Reference
Voltage
Reference voltage for
ECON/ECFB
differential amplifier
0
n
default
default
If bit CONTROL_2.FSR=0, the output voltage is
clamped to 1.2 V.
ECEN
Description
Remark
Electrochromic mirror
controller disabled
By enabling the electrochromic mirror controller
(ECEN=1), the output driver for the external pass
transistor (ECON) is enabled. In addition, OUT10 is
activated, regardless of the setting of
0
Electrochrom.
Mirror Enable
Electrochromic mirror
controller enabled
1
CONTROL_1.HS10.
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28
NCV7707, NCV7707B
CONTROL_2 Register
Address: 02h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OCR
ECFB
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 ECFB
PWM1 PWM1 PWM1 PWM1 PWM2 PWM1 PWM1
Bit name
OCR1 OCR2 OCR3 OCR4 OCR5 OCR6
PWMI
0
FSR
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCRx
Description
Remark
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
Overcurrent Recovery
disabled
0
default
Overcurrent
Recovery
Overcurrent Recovery
enabled
1
PWMI
Description
Remark
Internal PWM unit
disabled
0
default
The device has three different PWM sources: external
pins PWM1, PWM2 and the internal PWM unit which
can be used to control the lamp drivers in an
PWM Unit
Internal PWM unit
enabled
1
additional way. PWMI selects the internal PWM unit.
OUTx PWM
Description
Remark
For the half−bridge outputs it is possible to select the
PWM input pins PWM1 or PWM2. In this case the
dedicated output (selected in CONTROL_0 register) is
on if the PWM input signal is high. OUT5 is controlled
by PWM2, all other half−bridges are controlled by
PWM1.
0
default
PWMx not selected
PWM1/2
Selection
1
PWMx selected
FSR
Description
Remark
Vout = 1.5 / 2^6 ·
DAC[5:0] clamped at
1.2 V
0
default
DAC Full−scale
Range Control
The default voltage at ECFB in electrochrome mode is
clamped at 1.2 V, when FSR=1 the maximum value is
1.5 V.
Vout = 1.5 / 2^6 ·
DAC[5:0]
1
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29
NCV7707, NCV7707B
CONTROL_3 Register
Address: 03h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW RW RW RW
OUT7 OUT8 OUT9 OUT10 OUT11
PWM1 PWM2 PWM1 PWM2 PWM1
Bit name
OCR7 OCR8 OCR9 OCR10 OCR11
OCRF OVUVR IS3 IS2 IS1 IS0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCRx
Description
Remark
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
Overcurrent Recovery
disabled
0
1
default
Overcurrent
Recovery
Overcurrent Recovery
enabled
OUTx PWM
Description
Remark
For the HS outputs it is possible to select the PWM
input pins PWM1, PWM2 or internal PWMI unit
(OUT7−10 only). In this case the dedicated output
(selected in CONTROL_1 register) is on if the PWM
input signal is high. OUT8 and OUT10 are controlled
by PWM2, OUT7,9 and OUT11 are controlled by
PWM1.
0
default
PWMx not selected
PWM1/2
Selection
1
PWMx selected
OCRF
Description
Remark
Overcurrent
Recovery
Frequency
Selection
Slow Overcurrent re-
covery mode
0
default
If the overcurrent recovery bit is set, the output will be
switched on automatically after a delay time. The
recovery behavior of OUT7,8 in bulb mode is not
affected by this bit.
Fast Overcurrent re-
covery mode
1
OVUVR
Description
Remark
Over− and
undervoltage recovery
function enabled
Over− /
Under−voltage
Recovery
0
default
If the OV/UV recovery is disabled by setting
OVUVR=1, the status register STATUS_2 bits VSOV
or VSUV have to be cleared after an OV/UV event.
No over− and
undervoltage recovery
1
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30
NCV7707, NCV7707B
IS3
IS2
IS1
IS0
Description
Remark
0
0
0
0
OUT1
current sensing
deactivated
0
0
0
0
0
1
1
0
current sensing
deactivated
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
OUT4
OUT5
OUT6
OUT7
The current in all high−side power stages (except of
OUT2/3) can be monitored at the bidirectional
multifunctional pin ISOUT/PWM2.
This pin is a multifunctional pin and can be activated
as output by setting the current selection bits IS[3:0].
The selected high−side output will be multiplexed to
the output ISOUT.
OUT8
OUT9
OUT10
OUT11
Current
Sensing
Selection
current sensing
deactivated
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
current sensing
deactivated
current sensing
deactivated
current sensing
deactivated
current sensing
deactivated
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31
NCV7707, NCV7707B
PWM_7/8 Register
Address: 08h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
Bit Name
Reset Value
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FSEL7 PW7.6 PW7.5 PW7.4 PW7.3 PW7.2 PW7.1 PW7.0 FSEL8 PW8.6 PW8.5 PW8.4 PW8.3 PW8.2 PW8.1 PW8.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PW7[6:0]
0
Description
Remark
PWM Duty
Cycle selector
for OUT7
default
Duty Cycle for OUT7 =
(PW7[6:0] +1) / 128
It is possible to control OUT7 by the internal PWM unit
if bit PWMI is set in the control register CONTROL_2.
1 .. 7Fh
FSEL7
Description
f(PWM) = 170 Hz
f(PWM) = 225 Hz
Remark
PWM
Frequency
selector for
OUT7
0
1
default
default
Bit FSEL7 selects between 170 and 225 Hz PWM
frequency for OUT7.
PW8[6:0]
0
Description
Remark
PWM Duty
Cycle selector
for OUT8
It is possible to control OUT8 by the internal PWM
unit if bit PWMI is set in the control register
CONTROL_2.
Duty Cycle for OUT8
= (PW8[6:0] +1) / 128
1 .. 7Fh
FSEL8
Description
f(PWM) = 170 Hz
f(PWM) = 225 Hz
Remark
PWM
Frequency
selector for
OUT8
0
1
default
Bit FSEL8 selects between 170 and 225 Hz PWM
frequency for OUT8.
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32
NCV7707, NCV7707B
PWM_9/10 Register
Address: 09h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FSEL
10
Bit Name
FSEL9 PW9.6 PW9.5 PW9.4 PW9.3 PW9.2 PW9.1 PW9.0
PW10.6 PW10.5 PW10.4 PW10.3 PW10.2 PW10.1 PW10.0
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PW9[6:0]
0
Description
Remark
PWM Duty
Cycle selector
for OUT9
default
Duty Cycle for OUT9 =
(PW9[6:0] +1) / 128
It is possible to control OUT9 by the internal PWM unit
if bit PWMI is set in the control register CONTROL_2.
1 .. 7Fh
FSEL9
Description
f(PWM) = 170 Hz
f(PWM) = 225 Hz
Remark
PWM
Frequency
selector for
OUT9
0
1
default
default
default
Bit FSEL9 selects between 170 and 225 Hz PWM
frequency for OUT9.
PW10[6:0]
0
Description
Remark
PWM Duty
Cycle selector
for OUT10
It is possible to control OUT10 by the internal PWM
unit if bit PWMI is set in the control register
CONTROL_2.
Duty Cycle for OUT10
= (PW10[6:0] +1) / 128
1 .. 7Fh
FSEL10
Description
f(PWM) = 170 Hz
f(PWM) = 225 Hz
Remark
PWM
Frequency
selector for
OUT10
0
1
Bit FSEL10 selects between 170 and 225 Hz PWM
frequency for OUT10.
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33
NCV7707, NCV7707B
STATUS_0 Register
Address: 10h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
−
−
−
−
OC
HS1 LS1
OC
OC
HS2 LS2
OC
OC
HS3 LS3
OC
OC
OC
OC
OC
LS5 HS6
OC
OC
LS6
Bit Name
0
0
0
0
0
0
0
0
HS4 LS4 HS5
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
OCx
0
Description
Remark
During an overcurrent event in one of the HS or LS, the belonging
overcurrent status bit STATUS_0.OCx is set and the dedicated
output is switched off. (The global multi bit UOV_OC is set, also).
When the overcurrent recovery bit is enabled, the output will be
reactivated automatically after a programmable delay time
(CONTROL_3.OCRF). If the overcurrent recovery bit is not set the
microcontroller has to clear the OC failure bit and to reactivate the
output stage again.
No overcurrent
detected
OUT1−6
Overcurrent
Detection
1
Overcurrent detected
STATUS_1 Register
Address: 11h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
−
D2
−
D1
−
D0
−
Access Type
Bit Name
R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
ULD ULD ULD ULD ULD ULD ULD ULD ULD ULD ULD ULD
0
0
0
0
HS1 LS1
HS2 LS2
HS3 LS3
HS4 LS4 HS5
LS5 HS6
LS6
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ULDx
Description
Remark
For each output stage an underload status bit ULD is available. The
underload detection is done in ”on−mode”. If the load current is
below the undercurrent detection threshold for at least td_uld , the
corresponding underload bit ULDx is set.
If an ULD event occurs the global status bit ULD will be set.
For ULD_HS1 and ULD_LS1 it is possible to deactivate the global
ULD failure bit by setting the configuration bits
0
1
No underload detected
Underload detected
OUT1−6
Underload
Detection
CONFIG.NO_ULD_HS1/LS1. With setting
CONFIG.NO_ULD_OUTn the global ULD failure bit is deactivated
in general.
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34
NCV7707, NCV7707B
STATUS_2 Register
Address: 12h
Bit
D15
R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
OC ULD OC ULD OC ULD OC ULD OC ULD OC ULD
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
Bit name
VSUV VSOV ECLO ECHI
HS7 HS7 HS8 HS8 HS9 HS9 HS10 HS10 HS11 HS11 ECFB ECFB
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCx
0
Description
Remark
During an overcurrent event in one of the HS the belonging
overcurrent status bit STATUS_2.OCx is set and the dedicated
output is switched off. (The global multi bit UOV_OC is set, also).
When the overcurrent recovery bit is enabled, the output will be
reactivated automatically after a programmable delay time
No overcurrent
detected
OUT7−11
Overcurrent
Detection
(CONTROL_3.OCRF). If the overcurrent recovery bit is not set the
microcontroller has to clear the OC failure bit and to reactivate the
output stage again.
1
Overcurrent detected
ULDx
Description
Remark
For each output stage an underload status bit ULD is available. The
underload detection is done in ”on−mode”. If the load current is
below the undercurrent detection threshold for at least td_uld, the
corresponding underload bit ULDx is set.
0
No underload detected
OUT7−11
Underload
Detection
If an ULD event occurs the global status bit ULD will be set.
1
Underload detected
It is possible to deactivate the global ULD failure bit by setting the
configuration bits CONFIG.NO_ULD_OUTn.
VSUV
Description
Remark
In case of an Vs undervoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will be
set. By default the output stages will be reactivated automatically
after Vs is recovered unless the control bit CONTROL_3.OVUVR is
set. If this is the case (OVUVR=1) the bit VSUV has to be cleared
after an UV event.
No undervoltage
detected
0
Vs
Undervoltage
1
Undervoltage detected
VSOV
Description
Remark
In case of an Vs overvoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will be
set. By default the output stages will be reactivated automatically
after Vs is recovered unless the control bit CONTROL_3.OVUVR is
set. If this is the case (OVUVR=1) the bit VSOV has to be cleared
after an OV event.
No overvoltage
detected
0
Vs Overvoltage
1
Overvoltage detected
ECLO
ECHI
Description
Remark
ECM output regulation
in range
0
0
Two comparators monitor the voltage at pin ECFB (feedback) in
electrocrome mode. If this voltage is below / above the
programmed target these bits signal the difference after at least
32 ms. The bits are not latched and may toggle after at least 32 ms,
if the ECFB voltage has not yet reached the target. They are not
assigned to the Global Error Flag.
ECM output
V > Vregulation
EC Mirror
Control Status
0
1
ECM output
V < Vregulation
1
1
0
1
not used
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35
NCV7707, NCV7707B
CONFIG Register
Address: 3Fh
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
−
RW
−
RW
RW
RW
−
RW
−
ECM
LSPWM
NO_ULD NO_ULD NO_
HS1
NO_ULD
OUTn
Bit Name
0
0
0
0
0
0
0
0
LS1
TW
Reset Value
0
0
0
0
0
NO_ULD
HS1
NO_ULD
LS1
Description
Remark
Global underload flag
at HS1/LS1 active
0
0
1
1
0
1
0
1
default
For ULD_HS1 and ULD_LS1 it is possible to
deactivate the global ULD failure bit by setting the
configuration bits
Global
Underload Flag
HS1/LS1
No global underload
flag at LS1
CONFIG.NO_ULD_HS1/LS1.With setting
CONFIG.NO_ULD_OUTn the global ULD failure
bit is deactivated in general.
No global underload
flag at HS1
No global underload
flag at HS1/LS1
NO_TW
Description
Remark
Thermal warning flag
active
0
default
default
default
No Thermal
Warning Flag
The global thermal warning bit TW can be
deactivated.
No thermal warning
flag active
1
NO_ULD_OUTn
Description
Remark
Global underload flag
active
Global
Undeload Flag
OUTn
0
By setting CONFIG.NO_ULD_OUTn the global
ULD failure bit is deactivated in general.
No global underload
flag active
1
ECM_LSPWM
Description
Remark
LS PWM feature
disabled
If this bit is set, automatic PWM discharge on the
ECM output is enabled. In case of PWM
discharge the Overcurrent recovery feature is
disabled, regardless of the setting of
CONTROL_2.OC_ECFB.
0
ECM PWM
Discharge
LS PWM feature
enabled
1
www.onsemi.com
36
NCV7707, NCV7707B
PACKAGE DIMENSIONS
SSOP36 EP
CASE 940AB
ISSUE A
NOTES:
0.20 C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
4X
DETAIL B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
A
X
36
19
X = A or B
e/2
E1
E
DETAIL B
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICAT-
ED AREA.
36X
0.25 C
PIN 1
REFERENCE
MILLIMETERS
1
18
DIM MIN
MAX
2.65
0.10
2.60
0.30
0.32
e
A
A1
A2
b
---
---
36X b
B
M
S
S
0.25
T A
B
2.15
0.18
0.23
NOTE 6
TOP VIEW
c
h
DETAIL A
A
A2
D
10.30 BSC
H
D2
E
5.70
5.90
10.30 BSC
7.50 BSC
3.90 4.10
0.50 BSC
0.25 0.75
0.90
c
E1
E2
e
h
0.10 C
h
A1
SEATING
PLANE
END VIEW
M1
36X
C
SIDE VIEW
D2
L
0.50
L2
M
0.25 BSC
0
8
_
_
_
M1
5
15
_
GAUGE
PLANE
M
E2
L2
SEATING
PLANE
C
36X
L
DETAIL A
BOTTOM VIEW
SOLDERING FOOTPRINT
36X
1.06
5.90
4.10
10.76
1
36X
0.36
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
37
NCV7707, NCV7707B
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