NCV7710DQBR2G [ONSEMI]
车门模块驱动器（锁驱动器）;
| 型号： | NCV7710DQBR2G |
| 厂家： | 
ONSEMI |
| 描述： | 车门模块驱动器（锁驱动器） 驱动 驱动器 |
| 文件： | 总22页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Door-Module Driver-IC
(Lock Driver-IC)
SSOP36- EP
DQ SUFFIX
CASE 940AB
NCV7710B
The NCV7710B is a powerful Driver-IC for automotive body
control systems. The IC is designed to control lock motor in the door
of a vehicle. With the monolithic full-bridge driver stage, the IC is
able to control lock motor. The NCV7710B is controlled thru a 24 bit
SPI interface with in-frame response.
MARKING DIAGRAM
Features
NCV7710B
FAWLYYWWG
Operating Range from 5.5 V to 28 V
Two High-Side and Two Low-Side Drivers Connected as
Half- bridges
2 Half-bridges Iload = 6 A; Rdson = 150 mW @ 25C
Programmable Soft-Start Function to Drive Loads with Higher
Inrush Currents as Current Limitation Value
Support of PWM Control Frequency Outside the Audible Noise
Support of Active Freewheeling to Reduce Power Dissipation
Multiplex Current Sense Analog Output for Advanced Load
Monitoring
NCV7710B = Specific Device Code
F
A
WL
YY
WW
G
= Fab Location
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb- Free Package
Very Low Current Consumption in Standby Mode
Charge Pump Output to Control an External Reverse Polarity
Protection MOSFET
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
24- Bit SPI Interface for Output Control and Diagnostic
Protection Against Short Circuit, Overvoltage and Over-temperature
Downwards Pin-to-pin and SPI Registers Compatible with
NCV7707
SSOP36-EP Power Package
AEC-Q100 Qualified and PPAP Capable
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
De-centralized Door Electronic Systems
Rear Door Electronic Unit
Body Control Units (BCUs)
Several H-bridge Applications
Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
November, 2022 - Rev. 1
NCV7710B/D
NCV7710B
VS
CHP
NCV7710
Undervoltage Overvoltage
Diagnostic
short circuit
openload
Chargepump
Power- on Reset
Lockout
Lockout
overload
overtemperature
overvoltage
undervoltage
VCC
SI
CONTROL_0 Register
CONTROL_2 Register
SCLK
CSB
SO
Driver
Interface
VS
OUT1
OUT1
CONTROL_3 Register
STATUS_0 Register
VS
OUT2
OUT2
STATUS_1 Register
STATUS_2 Register
CONFIG Register
Special Function Register
PWM1
ISOUT/
PWM2
MUX
GND
Figure 1. Block Diagram
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2
NCV7710B
Vbat
Switches
VS
CHP
NCV7710
Charge Pump
24- bit
SO
SI
Serial
Data
Interface
Power- on Reset
SCLK
CSB
Protection:
short circuit
Logic Control
open load
mC
Logic IN
over temperature
VS undervoltage
VS overvoltage
PWM1
Current Sensing
ISOUT/
PWM2
Rs
GND
PWM
High- Side
Switch
High- Side
Switch
(0.15 W)
(0.15 W)
Low- Side
Switch
(0.15 W)
Low- Side
Switch
(0.15 W)
LIN SBC
(NCV742x)
VCC
LIN
OUT2
OUT1
(NCV7329)
lock
LIN
Figure 2. Application Diagram
GND
n.c.
1
36
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
VS
SI
n.c.
n.c.
ISOUT/PWM2
CSB
n.c.
PWM1
CHP
VS/TEST
VS
SO
VCC
SCLK
VS
VS
VS
n.c.
OUT1
OUT1
GND
OUT2
OUT2
GND
18
19
Figure 3. Pin Connections (Top View)
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3
NCV7710B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
GND
n.c.
Pin Type
Description
1
2
3
4
5
6
7
8
Ground
Ground Supply (all GND pins have to be connected externally)
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
VS
Supply
Battery Supply Input (all VS pins have to be connected externally)
SPI interface Serial Data Input
SI
Digital Input
PWM control Input / Current Sense Output. This pin is a bidirectional pin.
Depending on the selected multiplexer bits, an image of the instant current
of the corresponding HS stage can be read out.
Digital Input /
Analog Output
9
ISOUT/PWM2
This pin can also be used as PWM control input pin for OUT2.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CSB
SO
Digital Input
Digital Output
Supply
SPI interface Chip Select
SPI interface Serial Data Output
VCC
SCLK
VS
Logic Supply Input
Digital Input
SPI interface Shift Clock
Supply
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
Door Lock Output (has to be connected externally to pin 17)
Door Lock Output (has to be connected externally to pin 16)
Ground Supply (all GND pins have to be connected externally)
Ground Supply (all GND pins have to be connected externally)
Door Lock Output (has to be connected externally to pin 21)
Door Lock Output (has to be connected externally to pin 20)
Not connected
VS
Supply
OUT1
OUT1
GND
GND
OUT2
OUT2
n.c.
Half bridge driver Output
Half bridge driver Output
Ground
Ground
Half bridge driver Output
Half bridge driver Output
VS
Supply
Supply
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
Test Input, has to be connected to VS in application
Reverse Polarity FET Control Output
PWM control Input
VS
VS/TEST
CHP
PWM1
n.c.
Supply/Test Input
Analog Output
Digital Input
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
Heat slug
Ground
Substrate; Heat slug has to be connected to all GND pins
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4
NCV7710B
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Min
Max
Unit
Power supply voltage
- Continuous supply voltage
- 0.3
- 0.3
28
40
Vs
V
- Transient supply voltage (t < 500 ms, “clamped load dump”)
Vcc
Vdig
Logic supply
- 0.3
- 0.3
- 0.3
5.5
V
V
V
DC voltage at all logic pins (SO, SI, SCLK, CSB, PWM1)
Current monitor output / PWM2 logic input
Vcc + 0.3
Vcc + 0.3
Visout/pwm2
- 25
Vs - 25
40
Vs + 15
Vchp
Charge pump output (the most stringent value is applied)
V
Voutx
Static output voltage (OUT1/2)
OUT1/2 Output current
- 0.3
- 10
Vs + 0.3
10
V
A
Iout1/2
ESD Voltage, HBM (Human Body Model); (100 pF, 1500 W) (Note 1)
- All pins
- 2
- 4
2
4
ESD_HBM
ESD_CDM
kV
V
- Output pins OUT1/2 to GND (all unzapped pins grounded)
ESD according to CDM (Charge Device Model) (Note 1)
- All pins
- Corner pins
- 500
- 750
500
750
T
Operating junction temperature range
Storage temperature range
- 40
- 55
150
150
C
C
J
Tstg
MSL
Moisture sensitivity level (Note 2)
MSL3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC- Q100- 002 (EIA/JESD22- A114)
ESD Charge Device Model tested per EIA/JES D22/C101, Field Induced Charge Model
2. For soldering information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
Thermal Characteristics, SSOP36- EP, 1- layer PCB
Thermal Resistance, Junction- to- Air (Note 3)
R
49.4
C/W
θJA
θJA
Thermal Characteristics, SSOP36- EP, 4- layer PCB
Thermal Resistance, Junction- to- Air (Note 4)
R
24
C/W
3. Values based on PCB of 76.2 x 114.3 mm, 72 mm copper thickness, 20 % copper area coverage and FR4 PCB substrate.
4. Values based on PCB of 76.2 x 114.3 mm, 72 / 36 mm copper thickness (signal layers / internal planes), 20 / 90 % copper area coverage
(signal layers / internal planes) and FR4 PCB substrate.
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NCV7710B
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, - 40C < Tj < 150C; unless otherwise noted.
Symbol
SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
Functional (see Vuv_vs / Vov_vs)
Parameter specification
5.5
8
28
18
Vs
Supply voltage
V
Standby mode,
VS = 16 V, 0 V ≤ VCC ≤ 5.25 V,
CSB = VCC, OUT1/2 = floating,
SI = SCLK = 0 V, Tj < 85C
Is(standby)
Supply Current (VS), Standby mode
Supply current (VS), Active mode
3
11
mA
(T = 150C)
J
(6)
(25)
Active mode,
VS = 16 V,
Is(active)
6
20
mA
OUT1/2 = floating
Standby mode,
VCC = 5.25 V,
SI = SCLK = 0 V, T < 85C
3
7
Icc(standby)
Supply Current (VCC), Standby mode
Supply current (VCC), Active mode
mA
J
(T = 150C)
J
(12)
3.3
(50)
8
Active mode, VS = 16 V,
OUT1/2 = floating
Icc(active)
I(stdby)
mA
Standby mode,
Total Standby mode supply current
(Is + Icc)
VS = 16 V, T < 85C,
8
18
mA
J
CSB = VCC, OUT1/2 = floating
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
Vuv_vs(on)
VS increasing
5.6
5.2
6.2
5.8
V
V
V
V
V
V
V
V
V
VS Undervoltage detection
Vuv_vs(off)
VS decreasing
Vuv_vs(hys)
Vov_vs(off)
Vov_vs(on)
Vov_vs(hys)
Vuv_vcc(off)
Vuv_vcc(on)
Vuv_vcc(hys)
VS Undervoltage hysteresis
Vuv_vs(on) - Vuv_vs(off)
VS increasing
0.65
2
20
19
24.5
23.5
VS Overvoltage detection
VS Overvoltage hysteresis
VS decreasing
Vov_vs(off) - Vov_vs(on)
VCC increasing
2.9
VCC Undervoltage detection
VCC Undervoltage hysteresis
VCC decreasing
2
6
Vuv_vcc(off) - Vuv_vcc(on)
0.11
Time to set the power supply
fail bit UOV_OC in the Global
Status Byte
td_uvov
VS Undervoltage / Overvoltage filter time
100
ms
CHARGE PUMP OUTPUT CHP
Vchp8
Vchp10
Vchp12
Ichp
Chargepump Output Voltage
Vs = 8 V, Ichp = - 60 mA
Vs + 6
Vs + 9 Vs + 13
V
V
Chargepump Output Voltage
Chargepump Output Voltage
Chargepump Output current
Vs = 10 V, Ichp = - 80 mA
VS > 12 V, Ichp = - 100 mA
VS = 13.5 V, Vchp = Vs + 10 V
Vs + 8 Vs + 11 Vs + 13
Vs + 9.5 Vs + 11 Vs + 13
V
- 750
- 95
mA
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NCV7710B
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, - 40C < Tj < 150C; unless otherwise noted.
Symbol Parameter Test Conditions
DOOR LOCK OUTPUTS OUT1, OUT2
Min
Typ
Max
Unit
T = 25C, Iout1,2 = 3 A
0.15
W
W
J
Ron_out1,2
On- resistance HS or LS
T = 125C, Iout1,2 = 3 A
J
0.3
- 6
10
3
Ioc1,2_hs
Ioc1,2_ls
Overcurrent threshold HS
- 10
6
A
Overcurrent threshold LS
A
Vlim1,2
Vds voltage limitation HS or LS
Underload detection threshold HS
Underload detection threshold LS
Output delay time, HS Driver on
Output delay time, HS Driver off
Output delay time, LS Driver on
Output delay time, LS Driver off
2
V
Iuld1,2_hs
Iuld1,2_ls
- 300
60
- 60
300
3
mA
mA
ms
Time from CSB going high to
V(OUT1,2) = 0.9·Vs / 0.1·Vs
(on/off)
td_HS1,2(on)
td_HS1,2(off)
td_LS1,2(on)
td_LS1,2(off)
1.3
1.5
1
3
ms
ms
ms
Time from CSB going high to
V(OUT1,2) = 0.1·Vs / 0.9·Vs
(on/off)
3
1.5
3
Cross conduction protection time, low- to-
high transition including LS slew- rate
tdLH1,2
tdHL1,2
2
7
7
ms
ms
Cross conduction protection time, high-
to- low transition including HS slew- rate
5.5
Ileak_act_hs1,2
Ileak_act_ls1,2
Output HS leakage current, Active mode
Output pull- down current, Active mode
V(OUT1,2) = 0 V
V(OUT1,2) = VS
- 40
- 5
- 17
150
mA
mA
210
Output HS leakage current, Standby
mode
Ileak_stdby_hs1,2
V(OUT1,2) = 0 V
mA
V(OUT1,2) = VS, Tj ≥ 25C
V(OUT1,2) = VS, Tj < 25C
120
175
mA
mA
Ileak_stdby_ls1,2 Output pull- down current, Standby mode
60
td_uld1,2
td_old1,2
frec1,2L
frec1,2H
dVout1,2
Underload blanking delay
430
5
610
8
ms
ms
Overload shutdown blanking delay
Recovery frequency, slow recovery mode CONTROL_3.OCRF = 0
7.4
14.9
20
kHz
kHz
V/ms
Recovery frequency, fast recovery mode
Slew rate of HS driver
CONTROL_3.OCRF = 1
Vs = 13.5 V, Rload = 4 W to GND
9
0
30
CURRENT SENSE MONITOR OUTPUT ISOUT/PWM2
Current Sense output functional voltage
range
Vcc -
0.5
Vis
VCC = 5 V, Vs = 8- 20 V
V
K = Iout / Iis,
0 V ≤ Vis ≤ 4.5 V, Vcc = 5 V
Kis (Note 5)
Current Sense output ratio OUT1/2
13400
0.3 V ≤ Vis ≤ 4.5 V, Vcc = 5 V
Iout1/2 = 0.5- 5.9 A
- 7% -
4% FS
7% +
4% FS
Iis,acc (Notes 6, 7) Current Sense output accuracy OUT1/2
CONTROL_2.OUTx_PWM = 0
CONTROL_2.OUTx_PWM = 1
0 V to FSR (full scale range)
50
5
65
10
tis_blank
tis
Current Sense blanking time
Current Sense settling time
ms
ms
230
265
5. Kis trimmed at 150C at higher value of spec range to be more centered over temp range.
6. Current sense output accuracy = Isout- Isout_ideal relative to Isout_ideal
7. FS (Full scale) = Ioutmax/Kis
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NCV7710B
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, - 40C < Tj < 150C; unless otherwise noted.
Symbol Parameter Test Conditions
DIGITAL INPUTS CSB, SCLK, PWM1/2, SI
Min
Typ
Max
Unit
Vinl
Vinh
Input low level
Input high level
Input hysteresis
Vcc = 5 V
0.3·Vcc
V
V
0.7·Vcc
Vin_hyst
500
mV
Vcc = 5 V,
Rcsb_pu
Rsclk_pd
Rsi_pd
CSB pull- up resistor
30
30
30
30
120
60
250
220
220
220
kW
kW
kW
kW
0 V < Vcsb < 0.7·Vcc
Vcc = 5 V,
Vsclk = 1.5 V
SCLK pull- down resistor
SI pull- down resistor
PWM1 pull- down resistor
Vcc = 5 V,
Vsi = 1.5 V
60
Vcc = 5 V
Vpwm1 = 1.5 V
Rpwm1_pd
60
Vcc = 5 V,
Vpwm2 = 1.5 V,
current sense disabled
Rpwm2_pd
Ileak_isout
PWM2 pull- down resistor
Output leakage current
30
- 1
60
220
kW
Vpwm2 = 0 V,
current sense enabled
1
mA
Ccsb/sclk/pwm1/2 Pin capacitance
0 V < Vcc < 5.25 V (Note 8)
Vcc = 5 V
10
pF
DIGITAL INPUTS CSB, SCLK, SI; TIMING
tsclk
Clock period
1000
ns
ns
ns
tsclk_h
tsclk_l
Clock high time
Clock low time
115
115
CSB setup time, CSB low before rising
edge of SCLK
tset_csb
tset_sclk
400
400
ns
ns
SCLK setup time, SCLK low before rising
edge of CSB
tset_si
thold_si
tr_in
SI setup time
200
200
ns
ns
ns
ns
SI hold time
Rise time of input signal SI, SCLK, CSB
Fall time of input signal SI, SCLK, CSB
100
100
tf_in
Transfer of SPI- command to
input register, valid before tsact
mode transition delay expires
Minimum CSB high time, switching from
Standby mode
tcsb_hi_stdby
5
2
10
4
ms
ms
tcsb_hi_min
Minimum CSB high time, Active mode
8. Values based on design and/or characterization.
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NCV7710B
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, - 40C < Tj < 150C; unless otherwise noted.
Symbol
DIGITAL OUTPUT SO
Vsol
Parameter
Test Conditions
Min
Typ
Max
Unit
Output low level
Iso = 5 mA
0.2·Vcc
V
V
Vsoh
Output high level
Iso = - 5 mA
0.8·Vcc
Vcsb = Vcc,
Ileak_so
Cso
Tristate leakage current
- 10
10
10
mA
0 V < Vso < Vcc
Vcsb = Vcc,
0 V < Vcc < 5.25 V (Note 9)
Tristate input capacitance
pF
DIGITAL OUTPUT SO; TIMING
tr_so
tf_so
SO rise time
SO fall time
Cso = 100 pF
Cso = 100 pF
80
50
140
100
ns
ns
Cso = 100 pF, Iload = 1 mA,
pull- up load to VCC
ten_so_tril
tdis_so_ltri
ten_so_trih
tdis_so_htri
td_so
SO enable time from tristate to low level
SO disable time from low level to tristate
SO enable time from tristate to high level
SO disable time from high level to tristate
SO delay time
100
380
100
380
50
250
450
250
450
250
ns
ns
ns
ns
ns
Cso = 100 pF, Iload = 4 mA,
pull- up load to VCC
Cso = 100 pF, Iload = - 1 mA,
pull- down load to GND
Cso = 100 pF, Iload = - 4 mA,
pull- down load to GND
Vso < 0.3·Vcc, or Vso > 0.7·Vcc,
Cso = 100 pF
9. Values based on design and/or characterization.
0.8 V
CC
0.2 V
CSB
CC
t
t
t
set_csb
sclk
set_sclk
t
t
ri_in
csb_hi_min
t
f_in
0.8 V
CC
SCLK
0.2 V
0.2 V
CC
CC
t
t
sclk_h
sclk_l
t
set_si
t
hold_si
0.8 V
CC
SI
Valid
Valid
Valid
t
d_so
t
en_so_trix
0.7 V
0.3 V
0.7 V
CC
CC
CC
Valid
SO
Valid
Valid
Figure 4. SPI Signals Timing Parameters
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NCV7710B
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, - 40C < Tj < 150C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
THERMAL PROTECTION
Tjtw_on
Temperature warning threshold
Thermal warning hysteresis
Thermal shutdown threshold,
Junction temperature
140
160
C
C
Tjtw_hys
5
Tjsd_on
Junction temperature
Junction temperature
160
160
180
C
T increasing
J
Thermal shutdown threshold,
T decreasing
J
Tjsd_off
Tjsd_hys
C
C
C
Thermal shutdown hysteresis
5
Temperature difference between warning
and shutdown threshold
Tjsdtw_delta
20
Filter time for thermal warning and
shutdown
td_tx
TW / TSD Global Status bits
10
100
ms
OPERATING MODES TIMING
SPI communication ready after
VCC reached Vuv_vcc(off)
threshold
Time delay for mode change from
tact
tsact
tacts
30
360
8
ms
ms
ms
Unpowered mode into Standby mode
Time until output drivers are
enabled after CSB going to high
and CONTROL_0.MODE = 1
Time delay for mode change from
Standby mode into Active mode
190
Time until output drivers are
disabled after CSB going to high
and CONTROL_0.MODE = 0
Time delay for mode change from Active
mode into Standby mode via SPI
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NCV7710B
DETAILED OPERATING AND PIN DESCRIPTION
General
The NCV7710B provides two half-bridge drivers. Strict
condition until the status bits have been cleared by the
microcontroller. To avoid high current oscillations in case of
output short to GND and low Vs voltage conditions, it is
recommended to disable the Vs-auto-recovery by setting
OVUVR = 1.
adherence to integrated circuit die temperature is necessary,
with a static maximum die temperature of 150C. Output
drive control and fault reporting are handled via the SPI
(Serial Peripheral Interface) port. A SPI-controlled mode
control provides a low quiescent sleep current mode when
the device is not being utilized. A pull down is provided on
the SI and SCLK inputs to ensure they default to a low state
in the event of a severed input signal. A pull-up is provided
on the CSB input disabling SPI communication in the event
of an open CSB input.
Chargepump
In Standby mode, the chargepump is disabled. After
enabling the device by setting bit CONTROL_0.MODE to
active (1), the internal oscillator is started and the voltage at
theCHPoutput pinbeginsto increase. Theoutputdriversare
enabled after a delay of tsact once MODE was set to active.
Driver Outputs
Supply Concept
Output PWM Control
Power Supply Scheme - VS and VCC
For both-half bridge outputs the device features the
possibility tologicallycombinethe SPI-settingwith aPWM
signal that can be provided to the inputs PWM1 and
ISOUT/PWM2, respectively. Each of the outputs has a fixed
PWM signal assigned which is shown in Table 1. The PWM
modulation is enabled by the respective bits in the control
registers (CONTROL_2.OUTx_PWMx). In case of using
pin ISOUT/PWM2, the application design has to take care
of either disabling the current sense feature or to provide
sufficient overdrivecapabilitytomaintainproperlogicinput
levels for the PWM input. To improve power performances,
fast PWMing up to 30 kHz is foreseen.
The Vs power supply voltage is used to supply the half
bridges and the high-side drivers. An all-internal
chargepump is implemented to provide the gate-drive
voltage for the n-channel type high-side transistors. The
VCC voltage is used to supply the logic section of the IC,
including the SPI interface.
Due to the independent logic supply voltage the control
and status information will not be lost in case of a loss of Vs
supply voltage. The device is designed to operate inside the
specified parametric limits if the VCC supply voltage is
within the specified voltage range (4.5 V to 5.25 V).
Between the operational level and the VCC undervoltage
threshold level (Vuv_VCC) it is guaranteed that the device
remains in a safe functional state without any inadvertent
change to logic information.
By setting PWM_SWAP bit in the configurations register
CONFIG it is possible to map both outputs to PWM1.
This is useful if PWM control and current sensing is
required at OUT1 and OUT2.
Device / Module Ground Concept
Table 1. PWM CONTROL SCHEME
PWM Control Input
The heat slug is not hard-connected to internal GND rail.
It has to be connected externally.
CONFIG.PWM_SWAP = 0 CONFIG.PWM_SWAP = 1
Output
OUT1
OUT2
Power Up/Down Control
PWM1
PWM2
PWM1
PWM1
In order to prevent uncontrolled operation of the device
during power/up down, an undervoltage lockout feature is
implemented. Both supply voltages (VCC and Vs) are
monitored for undervoltage conditions supporting a safe
power-up transition. When Vs drops below the
undervoltage threshold Vuv_vs(off) (Vs undervoltage
threshold) both output stages are switched to
high-impedance state and the global status bit UOV_OC is
set. This bit is a multi information bit in the Global Status
Byte which is set in case of overcurrent, Vs over- and
undervoltage. In case of undervoltage the status bit
STATUS_2.VSUV is set, too.
Bit CONTROL_3.OVUVR (Vs under-/overvoltage
recoverybehavior)canbeusedtoselectthedesiredrecovery
behavior after a Vs under-voltage event. In case of OVUVR
= 0, both output stages return to their programmed state as
soon as Vs recovers back to its normal operating range. If
OVUVR is set, the automatic recovery function is disabled
thus the output stages will remain in high-impedance
In case of using pin ISOUT/PWM2, the application
design can decide:
To control all PWM via PWM1 by setting bit
CONFIG.PWM_SWAP to 1
or to disable the current sense feature
or to provide sufficient overdrive capability to maintain
proper logic input levels for the PWM input
Due to the used external network connected between
microcontroller and ISOUT/PWM2 pin, the digital input
signal cannot be guaranteed to be a clean digital high or low
level when the current output ISOUT is activated. During
Current sense the PWM2 digital input stays functional (the
input to the digital is not gated), but the internal pull down
on PWM2 is disabled when CS is activated.
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NCV7710B
Table 2. OUT1/2 CONTROL AND FREEWHEELING SELECTION
CONTROL_2
PWM input pin
PWM1/2
CONTROL_0
Output pin state
OUTx_PWM1/2
OUTx_HS
OUTx_LS
OUTx
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
High Impedance
L
0
X
0
1
(PWM disabled)
H
High Impedance
High Impedance
L
1
(PWM enabled)
High Impedance
L
H
H
Programmable Soft- start Function to Drive Loads with
Inrush Current Behavior
to select the output to be multiplexed to the current sense
output.
Loads with startup currents higher than the overcurrent
limits (e.g. block current of motors) can be driven using the
programmable soft-start function (Overcurrent auto-recovery
mode). Each output driver provides a corresponding
overcurrent recovery bit (CONTROL_2.OCRx) to control
the output behavior in case of a detected overcurrent event.
If auto-recovery is enabled, the device automatically
re-enables the output after a programmable recovery time.
For both half-bridge outputs, the recovery frequency can be
selected via SPI. It is recommended to only enable
auto-recovery for a minimum amount of time to drive the
connected load into a steady state condition. After turning
off the auto-recovery function, the respective channel is
automatically disabled if the overload condition still persists.
If the current sense feature is used in combination with
PWM control, the device will change the slew rate of the
output signal to a faster slope. Also the blanking time is
shortened to 5-10 ms.
The NCV7710B provides
a
sample-and-hold
functionality for the current sense output to enable precise
and simple load current diagnostics even during PWM
operation of the respective output. While in active high-side
output state, the current provided at ISOUT reflects a
(low-pass-filtered) image of the actual output current, the
IS-outputcurrentissampledand heldconstantassoon asthe
HS output transistor is commanded off via PWM (low-side
or high-impedant). In case no previous current information
is available in the Sample-and-hold stage (current sense
channel changed while actual channel is commanded off)
thesamplestageisresetso thatit reflectszerooutputcurrent.
Inductive Loads
Each half bridge (OUT1/2) is built by internally
connected low-side and high-side N-MOS transistors. Due
to the built-in body diodes of the output transistors,
inductive loads can be driven at the outputs without external
free-wheeling diodes.
Diagnostic Functions
All diagnostic functions (overcurrent, underload, power
supply monitoring, thermal warning and thermal shutdown)
are internally filtered. The failure condition has to be valid
for the minimum specified filtering time (td_old, td_uld,
td_uvov and td_tx) before the corresponding status bit in the
status register is set. The filter function is used to improve
the noise immunity of the device. The undercurrent and
temperature warning functions are intended for information
purpose and do not affect the state of the output drivers. An
overcurrent condition disables the corresponding output
driver while a thermal shutdown event disables all outputs
into high impedance state. Depending on the setting of the
overcurrent recovery bits in the input register, the driver can
either perform an auto-retry or remain latched off until the
microcontroller clears the corresponding status bits.
Overtemperature shutdown is latch-off only, without
auto-retry functionality.
Current Sensing
Current Sense Output / PWM2 Input (bidirectional pin
ISOUT/PWM2)
The current sense output allows a more precise analysis of
the actual state of the load rather than the basic detection of
an under- or overload condition. The sense output provides
an image of the actual load current at the selected high side
driver transistor. The current monitor function is available
for both high current half-bridge outputs (OUT1/2).
The current sense ratio is fixed to 1/13400. To prevent
from false readouts, the signal at pin ISOUT is blanked after
switching on the driver until correct settlement of the
circuitry (max. 65 ms). Bits CONTROL_3.IS[2:0] are used
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NCV7710B
Overvoltage / Undervoltage Shutdown
Cross- current Protection
If the supply voltage Vs rises above the switch off voltage
Vov_vs(off) or falls below Vuv_vs(off), all output
transistors are switched to high-impedance state and the
global status bit UOV_OC (multi information) is set. The
status flag STATUS_2.VSOV, resp. STATUS_2.VSUV is
set, too, to log the over-/under-voltage event. The bit
CONTROL_3.OVUVR can be used to determine the
recovery behavior once the Vs supply voltage gets back into
the specified nominal operating range. OVUVR = 0 enables
auto-recovery, with OVUVR = 1 the output stages remain
in high impedance condition until the status flags have been
cleared. Once set, STATUS2.VSOV / VSUV can only be
reset by a read&clear access to the status register STATUS_2.
The half-bridges are protected against cross-currents by
internal circuitry. If one driver is turned off (LS or HS), the
activation of the other driver of the same output will be
automatically delayed by the cross current protection
mechanism until the active driver is safely turned off.
Mode Control
Wake- up and Mode Control
Two different modes are available:
Active mode
Standby mode
After power-up of VCC the device starts in Standby
mode. Pullingthe chip-select signalCSBto lowlevelcauses
the device to change into Active mode (analog part active).
After at least 10 ms delay, the first SPI communication is
valid and bit CONTROL_0.MODE can be used to set the
desired mode of operation. If bit MODE remains reset (0),
the device returns to the Standby mode after an internal
delay of max. 8 ms, clearing all register content and setting
all output stages into high impedance state.
Thermal Warning and Overtemperature Shutdown
The device provides a dual-stage overtemperature
protection. If the junction temperature rises above Tjtw_on,
a temperature warning flag (TW) is set in the Global Status
Byte and can be read via SPI. The control software can then
react onto this overload condition by a controlled disable of
individual outputs. If however the junction temperature
reaches the secondthreshold Tjsd_on, the thermal shutdown
bit TSD is set in the Global Status Byte and all output stages
are switched into high impedance state to protect the device.
The minimum shutdown delay for overtemperature is td_tx.
The output channels can be re-enabled after the device
cooled down and the TSD flag has been reset by the
microcontroller by setting CONTROL_0.MODE = 0.
VCC Power- up
Delay (tact)
Output stages Hi- Z
Register content cleared
SPI not ready
Delay (tsact)
MODE = 1
or
CSB = 0
CSB = 0
MODE = 1
CSB = 1
and
MODE = 0
Standby
Active
Output stages High- Z
Register content cleared
Output stages controlled
thru output registers
Openload (Underload) Detection
The openload detection monitors the load current in the
output stage while the transistor is active. If the load current
is below the openload detection threshold for at least td_uld,
the corresponding bit (ULDx) is set in the status registers
STATUS_1. The status of the output remains unchanged.
Once set, ULDx remains set regardless of the actual load
condition. It has to be reset by a read&write access to the
corresponding status register.
MODE = 0
Delay timer
expired
and
CSB = 1
Delay (tacts)
Output stages controlled
thru output registers
Register content valid
Figure 5. Mode Transitions Diagram
Overload Detection
CSB
An overcurrent condition is indicated by the flag
(UOV_OC) in the Global Status Byte after a filter time of at
leasttd_old. Thechannel dependentovercurrentflagsareset
in the status registers (STATUS_0.OCx) and the
corresponding driver is switched into high impedance state
to protect the device. Each low-side and high-side driver
stage provides its own overcurrent flag. Resetting this
overcurrent flag automatically re-enables the respective
output (provided it is still enabled thru the Control register).
If the over current recovery function is enabled, the internal
chip logic automatically resets the overcurrent flag after a
fixed delay time, generating a PWM modulated current with
a programmable duty cycle. Otherwise the status bits have
to be cleared by the microcontroller by a read&clear access
to the corresponding status register.
t
t
0
1
2
3
4
5
21
22
23
SCLK
D23 D22 D21 D20 D19 D18
CSB = 0
D2
D1
D0
SI
t
t
CONTROL_0.MODE = 1
Mode
standby
active
active
CSB = 0
&
MODE = 0
Mode
standby
active
standby
t
< 8 ms
Figure 6. Mode Timing Diagram
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NCV7710B
SPI Control
CSB, the content of the selected register is transferred into
the output shift register.
General Description
The NCV7710B provides three control registers
(CONTROL_0/2/3), three status registers (STATUS_0/1/2)
and one general configuration register (CONFIG). Each of
these register contains 16-bit data, together with the 8-bit
frame header (access type, register address), the SPI frame
length is therefore 24 bits. In addition to the read/write
accessible registers, the NCV7710B provides five 8-bit ID
registers (ID_HEADER, ID_VERSION, ID_CODE1/2 and
ID_SPI-FRAME) with 8-bit data length. The content of
these registers can still be read out by a 24-bit access, the
data is then transferred in the MSB section of the data frame.
The 4-wire SPI interface establishes a full duplex
synchronous serial communication link between the
NCV7710B and the application’s microcontroller. The
NCV7710B always operates in slave mode whereas the
controller provides the master function. A SPI access is
performed by applying an active-low slave select signal at
CSB. SI is the data input, SO the data output. The SPI master
provides the clock to the NCV7710B via the SCLK input.
The digital input data is sampled at the rising edge at SCLK.
The data output SO is in high impedance state (tri-state)
when CSB is high. To readout the global error flag without
sending
a complete SPI frame, SO indicates the
SPI Frame Format
corresponding value as soon as CSB is set toactive. With the
first rising edge at SCLK after the high-to-low transition of
Figure 7 shows the general format of the NCV7710B SPI
frame.
Access
Register Address
Type
Input Data
Input Data
CSB
SCLK
OC1 OC1 A5 A4
A3
A2
A1
A0
DI7
DI6
DI2 DI1 DI0
DO2 DO1 DO0
SI
UOV
_OC
SO
FLT
TF RES TSD TW
ULD NRDY DO7 DO6
X
Device Status Bits
Address- dependent Data
Figure 7. SPI Frame Format
24- bit SPI Interface
SCLK, the data at the input pin Serial IN (SI) is latched. The
data is shifted out thruthe data output pin SO after thefalling
edges of SCLK. The clock SCLK must be active only within
the frame time, means when CSB is low. The correct
transmission is monitored by counting the number of clock
pulses during the communication frame. If the number of
SCLK pulses does not correspond to the frame width
indicated in the SPI-frame-ID (Chip ID Register, address
3Eh) the frame will be ignored and the communication
failure bit “TF” in theglobal status byte willbe set. Duetothis
safety functionality, daisy chaining the SPI is not possible.
Instead, a parallel operation of the SPI bus by controlling the
CSB signal of the connected ICs is recommended.
Both 24-bit input and output data are MSB first. Each
SPI-input frame consists of a command byte followed by
two data bytes. The data returned on SO within the same
frame always starts with the global status byte. It provides
general status information about the device. It is then
followed by 2 data bytes (in-frame response) which content
depends on the information transmitted in the command
byte. For write access cycles, the global status byte is
followed by the previous content of the addressed register.
Chip Select Bar (CSB)
CSB is the SPI input pin which controls the data transfer
of the device. When CSB is high, no data transfer is possible
and the output pin SO is set to high impedance. If CSB goes
low, theserial datatransferisallowedand canbestarted. The
communication ends when CSB goes high again.
Serial Data In (SI)
During the rising edges of SCLK (CSB is low), the data
is transferred into the device thru the input pin SI in a serial
way. The device features a stuck-at-one detection, thus
upon detection of a command = FFFFFFh, the device will be
forced into the Standby mode. All output drivers are
switched off.
Serial Clock (SCLK)
If CSB is set to low, the communication starts with the
rising edge of the SCLK input pin. At each rising edge of
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NCV7710B
Serial Data Out (SO)
the remaining bits are unused but are reserved. Both Write
and Read mode allow access to the internal registers of the
device. A “Read & Clear”-access is used to read a status
register and subsequently clear its content. The “Read
Device Information” allows to read out device related
information such as ID-Header, Product Code, Silicon
Version and Category and the SPI-frame ID. While
receiving the command byte, the global status byte is
transmitted to the microcontroller. It contains global fault
information for the device, as shown in Table 7.
The SO data output driver is activated by a logical low
level at the CSB input and will go from high impedance to
a low or high level depending on the global status bit, FLT
(Global Error Flag). The first rising edge of the SCLK input
after a high to low transition of the CSB pin will transfer the
content of the selected register into the dataout shift register.
Each subsequent falling edge of the SCLK will shift the next
bit thru SO out of the device.
Command Byte / Global Status Byte
Each communication frame starts with a command byte
(Table 3). It consists of an operation code (OP[1:0], Table 4)
which specifies the type of operation (Read, Write, Read &
Clear, Readout Device Information) and a six bit address
(A[5:0], Table 5). If less than six address bits are required,
ID Register
Chip ID Information is stored in five special 8-bit ID
registers (Table 6). The content can be read out at the
beginning of the communication.
Table 3. COMMAND BYTE / GLOBAL STATUS BYTE STRUCTURE
Command Byte (IN) / Global Status Byte (OUT)
23
OP1
FLT
1
22
OP0
TF
0
21
A5
20
A4
TSD
0
19
A3
TW
0
18
17
A1
ULD
0
16
A0
Bit
NCV7710B IN
NCV7710B OUT
Reset Value
A2
UOV_OC
0
RESB
0
NRDY
1
Table 4. COMMAND BYTE, ACCESS MODE
OP1
OP0
Description
0
0
1
1
0
1
0
1
Write Access (W)
Read Access ( R)
Read and Clear Access (RC)
Read Device ID (RDID)
Table 5. COMMAND BYTE, REGISTER ADDRESS
A[5:0]
Access
Description
Content
Control Register
CONTROL_0
00h
R/W
Device mode control, Bridge outputs control
Bridge outputs recovery control, PWM enable
Current Sense selection
Control Register
CONTROL_2
02h
03h
10h
11h
12h
3Fh
R/W
R/W
Control Register
CONTROL_3
Status Register
STATUS_0
R/RC
R/RC
R/RC
R/W
Bridge outputs Overcurrent diagnosis
Bridge outputs Underload diagnosis
Vs Over- and Undervoltage
Status Register
STATUS_1
Status Register
STATUS_2
Configuration Register
CONFIG
Mask bits for global fault bits, PWM mapping
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NCV7710B
Table 6. CHIP ID INFORMATION
A[5:0]
00h
Access
RDID
RDID
RDID
RDID
RDID
Description
ID header
Content
4300h
01h
Version
0900h
7700h
0A00h
0200h
02h
Product Code 1
Product Code 2
SPI- Frame ID
03h
3Eh
Table 7. GLOBAL STATUS BYTE CONTENT
FLT
Global Fault Bit
Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit
is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected
via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of
SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the
Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be masked.
0
1
No fault Condition
Fault Condition
TF
0
SPI Transmission Error
No Error
Error
If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The
frame was ignored and this flag was set.
1
RESB
Reset Bar (Active low)
0
1
Reset
Bit is set to “0” after a Power- on- Reset or a stuck- at- 1 fault at SI (SPI- input data = FFFFFFh)
has been detected. All outputs are disabled.
Normal Operation
TSD
Overtemperature Shutdown
Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including
the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a
SW reset to reactivate the output drivers and the chargepump output.
0
1
No Thermal Shutdown
Thermal Shutdown
TW
0
Thermal Warning
No Thermal Warning
Thermal Warning
This bit indicates a pre- warning level of the junction temperature. It is maskable by the
Configuration Register (CONFIG.NO_TW).
1
UOV_OC
VS Monitoring, Overcurrent Status
0
1
No Fault
Fault
This bit represents a logical OR combination of under- /overvoltage signals (VS) and overcurrent
signals.
ULD
Underload
0
1
No Underload
Underload
This bit represents a logical OR combination of all underload signals. It is maskable by the
Configuration Register (CONFIG.NO_ULDx).
NRDY
Not Ready
0
1
Device Ready
After transition from Standby to Active mode, an internal timer is started to allow the internal
chargepump to settle before any outputs can be activated. This bit is cleared automatically after
the startup is completed.
Device Not Ready
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16
NCV7710B
SPI REGISTERS CONTENT
CONTROL_0 Register
Address: 00h
Bit
D15
D14
D13
D12
D11
D10
D9
RW
HS1
0
D8
RW
LS1
0
D7
RW
HS2
0
D6
RW
LS2
0
D5
-
D4
-
D3
-
D2
-
D1
-
D0
RW
Access type
Bit name
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODE
0
Reset value
0
0
0
0
0
HSx
LSx
Description
Remark
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_2
register, the HS output is activated if PWM1 (PWM2)
input signal is high, LS is activated otherwise.
Since OUT1 and OUT2 are half- bridge outputs,
activating both HS and LS at the same time is prevented
by internal logic.
0
0
1
0
1
0
default
OUTx High impedance
LSx enabled
HS/LS
Outputs
Control
HSx enabled
OUTx High impedance /
LS or HS enabled in PWM
1
1
MODE
Description
Remark
If MODE is set, the device is switched to Active mode.
Resetting MODE forces the device to transition into
Standby mode, all internal memory is cleared, all output
stages are switched into their default state (off).
Mode
Control
0
1
default
Standby
Active
CONTROL_2 Register
Address: 02h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
-
-
-
RW
RW
-
-
-
-
-
-
RW
RW
-
-
-
OUT1 OUT2
PWM1 PWM2
Bit name
0
0
0
0
0
0
OCR1 OCR2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
OCRx
Description
Remark
During an overcurrent event the overcurrent status bit
STATUS_0.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set, also).
When the overcurrent recovery bit is enabled, the output
will be reactivated automatically after a programmable
delay time (CONTROL_3.OCRF).
Overcurrent Recovery
disabled
0
default
Overcurrent
Recovery
Overcurrent Recovery
enabled
1
OUTx PWM
Description
Remark
For the outputs it is possible to select the PWM input
pins PWM1 or PWM2. In this case the dedicated output
(selected in CONTROL_0 register) is on if the PWM input
signal is high. By default, OUT2 is controlled by PWM2,
OUT1 is controlled by PWM1. By setting
CONFIG.PWM_SWAP bit, both outputs are mapped to
PWM1
0
default
PWMx not selected
PWM1/2
Selection
1
PWMx selected
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NCV7710B
CONTROL_3 Register
Address: 03h
Bit
D15 D14 D13 D12 D11 D10
D9
-
D8
-
D7
-
D6
-
D5
D4
D3
-
D2
RW
IS2
0
D1
RW
IS1
0
D0
RW
IS0
0
Access type
Bit name
-
-
-
-
-
-
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCRF OVUVR
0
Reset value
0
0
0
0
0
0
0
OCRF
Description
Remark
Overcurrent
Recovery
Frequency
Selection
Slow Overcurrent recovery
mode
0
default
default
If the overcurrent recovery bit is set, the output will be
switched on automatically after a delay time.
Fast Overcurrent recovery
mode
1
OVUVR
Description
Remark
Over- and undervoltage
recovery function enabled
Over- /Under-
voltage
Recovery
0
If the OV/UV recovery is disabled by setting
OVUVR=1, the status register STATUS_2 bits VSOV
or VSUV have to be cleared after an OV/UV event to
reactivate the outputs.
No over- and undervoltage
recovery
1
IS2
IS1
0
IS0
0
Description
current sensing deactivated
current sensing deactivated
current sensing deactivated
OUT1
Remark
0
0
0
0
1
1
1
1
0
1
The current in high- side power stages can be
monitored at the bidirectional multifunctional pin
ISOUT/PWM2.
This pin is a multifunctional pin and can be activated
as output by setting the current selection bits IS[2:0].
The selected high- side output will be multiplexed to
the output ISOUT.
1
0
Current
Sensing
Selection
1
1
0
0
OUT2
0
1
current sensing deactivated
current sensing deactivated
current sensing deactivated
1
0
1
1
STATUS_0 Register
Address: 10h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
-
-
-
-
-
-
R/RC R/RC R/RC R/RC
-
-
-
-
-
-
OC
OC
OC
OC
Bit name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HS1
LS1
HS2
LS2
Reset value
0
0
0
0
OCx
Description
Remark
During an overcurrent event in one of the HS or LS, the belonging overcurrent
status bit STATUS_0.OCx is set and the dedicated output is switched off. (The
global multi bit UOV_OC is set, also). When the overcurrent recovery bit is
enabled, the output will be reactivated automatically after a programmable
delay time (CONTROL_3.OCRF). If the overcurrent recovery bit is not set the
microcontroller has to clear the OC failure bit and to reactivate the output stage
again.
0
No overcurrent detected
Overcurrent detected
Overcurrent
Detection
1
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NCV7710B
STATUS_1 Register
Address: 11h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
-
-
-
-
-
-
R/RC R/RC R/RC R/RC
ULD ULD ULD ULD
-
-
-
-
-
-
Bit name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HS1
LS1
HS2
LS2
Reset value
0
0
0
0
ULDx
Description
Remark
For each output stage an underload status bit ULD is available. The underload
detection is done in “on- mode”. If the load current is below the undercurrent
detection threshold for at least td_uld , the corresponding underload bit ULDx is
set.
If an ULD event occurs the global status bit ULD will be set. With setting
CONFIG.NO_ULD_OUTn the global ULD failure bit is deactivated in general.
0
No underload detected
Underload detected
Underload
Detection
1
STATUS_2 Register
Address: 12h
Bit
D15
D14
D13
D12
D11
D10
D9
-
D8
-
D7
-
D6
-
D5
-
D4
-
D3
D2
D1
-
D0
-
Access type
Bit name
-
-
-
-
-
-
R/RC R/RC
VSUV VSOV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
VSUV
Description
Remark
In case of an Vs undervoltage event, the output stages will be deactivated
immediately and the corresponding failure flag will be set. By default the
output stages will be reactivated automatically after Vs is recovered unless
the control bit CONTROL_3.OVUVR is set. If this is the case (OVUVR=1)
the bit VSUV has to be cleared after an UV event.
0
1
No undervoltage detected
Undervoltage detected
Vs Undervoltage
Vs Overvoltage
VSOV
Description
Remark
In case of an Vs overvoltage event, the output stages will be deactivated
immediately and the corresponding failure flag will be set. By default the
output stages will be reactivated automatically after Vs is recovered unless
the control bit CONTROL_3.OVUVR is set. If this is the case (OVUVR=1)
the bit VSOV has to be cleared after an OV event.
0
No overvoltage detected
1
Overvoltage detected
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19
NCV7710B
CONFIG Register
Address: 3Fh
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
-
-
-
-
-
-
-
-
-
-
-
-
RW
-
RW
RW
NO_ULD PWM
OUTn SWAP
Bit name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NO_TW
0
0
0
Reset value
0
0
NO_TW
Description
Remark
No Thermal
0
1
default
default
default
Thermal warning flag active
No thermal warning flag active
The global thermal warning bit TW can be
deactivated.
Warning Flag
NO_ULD OUTn
Description
Remark
Global
Undeload
Flag OUTn
By setting CONFIG.NO_ULD_OUTn the
global ULD failure bit is deactivated in
general.
0
1
Global underload flag active
No global underload flag active
PWM_SWAP
Description
OUT2 mapped to PWM2
OUT2 mapped to PWM1
Remark
OUT2 PWM
Mapping
0
1
By setting PWM_SWAP bit, both outputs are
mapped to PWM1
ORDERING INFORMATION
Device
†
Package
Shipping
NCV7710DQBR2G
SSOP36- EP
(Pb- Free)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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20
NCV7710B
PACKAGE DIMENSIONS
SSOP36 EP
CASE 940AB
ISSUE A
NOTES:
0.20 C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
4X
DETAIL B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
A
X
36
19
X = A or B
e/2
E1
E
DETAIL B
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICAT-
ED AREA.
36X
0.25 C
PIN 1
REFERENCE
MILLIMETERS
1
18
DIM MIN
MAX
2.65
0.10
2.60
0.30
0.32
e
A
A1
A2
b
c
D
- - -
- - -
2.15
0.18
0.23
36X b
B
M
S
S
0.25
T A
B
NOTE 6
TOP VIEW
h
DETAIL A
A
A2
10.30 BSC
H
D2
E
E1
E2
e
5.70
5.90
10.30 BSC
7.50 BSC
3.90 4.10
0.50 BSC
c
h
0.10 C
h
L
L2
M
M1
0.25
0.50
0.75
0.90
A1
SEATING
PLANE
END VIEW
M1
36X
C
SIDE VIEW
D2
0.25 BSC
0
5
8
15
_
_
_
_
GAUGE
PLANE
M
E2
L2
SEATING
PLANE
C
36X
L
DETAIL A
BOTTOM VIEW
SOLDERING FOOTPRINT
36X
1.06
5.90
4.10
10.76
1
36X
0.36
0.50
PITCH
DIMENSIONS: MILLIMETERS
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21
NCV7710B
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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