NCV7726DQBR2G [ONSEMI]
12 沟道半桥驱动器;
| 型号： | NCV7726DQBR2G |
| 厂家： | 
ONSEMI |
| 描述： | 12 沟道半桥驱动器 驱动 驱动器 |
| 文件： | 总26页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7726B
Half-Bridge Driver
The NCV7726B is a twelve channel half−bridge driver with
protection features designed specifically for automotive and industrial
motion control applications. The product has independent controls and
diagnostics, and the drivers can be operated in forward, reverse, brake,
and high impedance states. The device is controlled via a 16 bit SPI
interface and is daisy chain compatible.
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Features
MARKING
DIAGRAM
• Low Quiescent Current Sleep Mode
• High−Side and Low−Side Drivers
Connected in Half−Bridge Configurations
• Integrated Freewheeling Protection (LS and HS)
• 500 mA Typical, 1.1 A Peak Current
NCV7726B
AWLYWWG
SSOP24 NB EP
CASE 940AK
• R
= 0.85 W (typ)
DS(on)
• 5 MHz SPI Communication
NCV7726B = Specific Device Code
• 16 Bit Frame Error Detection
A
= Assembly Location
= Wafer Lot
• Daisy Chain Compatible with Multiple of 8 bit Devices
• Compliance with 3.3 V and 5 V Systems
• Undervoltage and Overvoltage Lockout
• Per Channel Fault Reporting
WL
Y
= Year
WW
G
= Work Week
= Pb−Free Package
• Overcurrent Protection
• Overtemperature Protection
• Underload Detection (HS and LS)
• Exposed Pad Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of
this data sheet.
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This is a Pb−Free Device
Typical Applications
• Automotive
• Industrial
• DC Motor Management for HVAC Application
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2019 − Rev. 0
NCV7726B/D
NCV7726B
High−side
Driver
NCV7726B
OUT1
Low−side
Driver
VS1
VS2
1 μF
MRA4003T3
13.2 V
HS
OUT2
OUT3
LS
HS
VCC
Voltage
Regulator
Power On
Reset
10 nF
LS
HS
EN
Control
Logic
OUT4
OUT5
Watchdog
LS
HS
Protection:
LS
HS
Under Load
Over Temperature
Under−voltage
Over−voltage
OUT6
OUT7
Over Current
LS
HS
SO
SI
16 − Bit
Serial
Data
SCLK
CSB
LS
HS
uC
Interface
OUT8
OUT9
LS
HS
LS
HS
OUT10
OUT11
LS
HS
LS
High−side
Driver
OUT12
Low−side
Driver
GND
Figure 1. Typical Application
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2
NCV7726B
VS1
DRIVE 1
VS
VS
EN
ENABLE
BIAS
High Side
Driver
Charge
Pump
VS1
Wave Shaping
VCC
Fault
Reporting
Control
Logic
OUT1
POR
Wave Shaping
VS
Low Side
Driver
SO
SI
HS + LS Under Load
Overcurrent
SPI and 16 Bit Logic Control
SCLK
CSB
Thermal Warning &
Shutdown
VS1
VS2
VS2
VS1
DRIVE 2
DRIVE 3
DRIVE 4
DRIVE 5
OUT2
OUT3
OUT4
OUT5
VS1, VS2
Overvoltage
Lockout
Undervoltage
Lockout
VS2
VS1
DRIVE 6
DRIVE 7
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
VS1
VS2
VS2
VS2
DRIVE 8
DRIVE 9
DRIVE 10
DRIVE 11
DRIVE 12
VS2
GND
GND
GND GND
VS2
Figure 2. Block Diagram
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3
NCV7726B
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
GND
OUT1
OUT5
OUT7
SI
GND
OUT2
OUT8
VS1
SCLK
CSB
VCC
SO
EPAD
OUT12
OUT11
VS2
8
EN
9
OUT9
OUT6
OUT4
GND
10
11
12
OUT10
OUT3
GND
Figure 3. Pinout – SSOP24 NB EP
PIN FUNCTION DESCRIPTION The pin−out for the Half−Bridge Driver in SSOP24 NB EP package is shown in the table below.
Pin#
SSOP24
Symbol
GND
OUT1
OUT5
OUT7
SI
Description
Ground. Must be connected to other GNDs externally.
1
2
3
4
5
6
7
8
Half−bridge output 1
Half−bridge output 5
Half−bridge output 7
16 bit serial communication input. 3.3V/5V (TTL) Compatible − internally pulled down.
Power supply input for Logic.
VCC
SO
16 bit serial communication output. 3.3V/5V Compliant
EN
Enable − active high; wakes the device from sleep mode. 3.3V/5V (TTL) Compatible − internally pulled
down.
9
OUT9
OUT6
OUT4
GND
Half−bridge output 9
10
11
12
13
14
15
16
17
18
19
Half−bridge output 6
Half−bridge output 4
Ground. Must be connected to other GNDs externally.
GND
Ground. Must be connected to other GNDs externally.
OUT3
OUT10
VS2
Half−bridge output 3
Half−bridge output 10
Power Supply input for outputs 3, 4, 6, 9, 10, 11 and 12. This pin must be connected to VS1 externally.
OUT11
OUT12
CSB
Half−bridge output 11
Half−bridge output 12
Chip select bar − active low; enables serial communication operation. 3.3V/5V (TTL) Compatible − in-
ternally pulled up.
20
21
SCLK
VS1
Serial communication clock input. 3.3V/5V (TTL) Compatible − internally pulled down.
Power Supply input for outputs 1, 2, 5, 7, 8. This pin must be connected to VS2 externally.
Half−bridge output 8
22
OUT8
23
OUT2
Half−bridge output 2
24
GND
Ground. Must be connected to other GNDs externally.
Connect to GND or leave unconnected.
EPAD
Exposed Pad
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4
NCV7726B
MAXIMUM RATINGS (Voltages are with respect to GND)
Rating
Symbol
Value
Unit
VSx Pin Voltage
(VS1, VS2)
V
(DC)
VSxdcMax
VSxac
−0.3 to 40
−1.0
(AC), t < 500 ms, Ivsx > −2 A
I/O Pin Voltage
(Vcc, SI, SCLK, CSB, SO, EN)
VioMax
−0.3 to 5.5
V
V
OUTx Pin Voltage
(DC)
(AC)
VoutxDc
VoutxAc
−0.3 to 40
−0.3 to 40
−1.0
(AC), t< 500 ms, IOUTx > −1.1 A
(AC), t< 500 ms, IOUTx < 1 A
1.0
OUTx Pin Current (OUT1, ..., OUT12)
Junction Temperature Range
IoutxImax
−2.0 to 2.0
−40 to 150
−55 to 150
260
A
T
J
°C
°C
°C
Storage Temperature Range
Tstr
Peak Reflow Soldering Temperature: Pb−free 60 to 150 seconds at 217°C
(Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ATTRIBUTES
Characteristic
Short Circuit Reliability Characterization
Symbol
Value
Unit
AECQ10x
Grade A
−
ESD Capability
Human Body Model per AEC−Q100−002
VSx, OUTx
All Other Pins
Vesd4k
Vesd2k
Vesd750
≥
≥
≥
4.0 kV
2.0 kV
750 V
Charged Device Model per AEC−Q100−011
Moisture Sensitivity Level
MSL
MSL2
−
Package Thermal Resistance – Still−air
Junction–to–Ambient
(Note 2)
(Note 2)
R
29.4
10.5
°C/W
°C/W
q
JA
Junction–to–Board
R
Y
JBOARD
2
2. Based on JESD51−7, 1.6 mm thick FR4, 2S2P PCB with 600 mm 2 oz. copper and 18 thermal vias to 80x80 mm 1 oz. internal spreader
planes. Simulated with each channel dissipating 0.2 W.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCCOp
VSxOp
IxOp
Min
3.15
5.5
−
Max
5.25
32
Unit
V
Digital Supply Input Voltage
Battery Supply Input Voltage (VS1 = VS2)
DC Output Current
V
0.5
A
Junction Temperature
TjOp
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NCV7726B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.)
J
CC
CC
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Supply Current (VS1 + VS2)
Sleep Mode
IqVSx85
IvsOp
VS1 = VS2 = 13.2V, V = 0 V
CC
−40°C to 85°C
−
−
1.0
2.5
2.5
5.0
mA
Supply Current (VS1 + VS2)
Active Mode
EN = V , 5.5V < VSx < 28 V
mA
CC
No Load, All Outputs Off
Supply Current (Vcc)
Sleep Mode
CSB = V , EN = SI = SCLK = 0 V
CC
IqV
−40°C to 85°C
−
1.0
2.5
mA
CC
EN = CSB = V , SI = SCLK = 0 V
CC
Active Mode
IV Op
CC
All Outputs Off
−
−
1.5
2.0
3.0
5.0
mA
Total Sleep Mode Current
IqTot
Sleep Mode, −40°C to 85°C
VS1 = VS2 = 13.2 V, No Load
mA
I(VS1) + I(VS2) + I(VCC)
VCC Power−on Reset Threshold
V
por
V
increasing
−
2.70
4.1
−
2.90
4.5
V
V
CC
CC
VSx Undervoltage Detection Threshold
VSxuv
VSx decreasing
VSx increasing
3.5
100
VSx Undervoltage Detection
Hysteresis
VSxuHys
450
mV
VSx Overvoltage Detection Threshold
VSx Overvoltage Detection Hysteresis
DRIVER OUTPUT CHARACTERISTICS
VsXov
32
1
36
40
4
V
V
VSxoHys
2.5
Output High R
(source)
R
HS
DSon
Iout = −500 mA, Vs = 13.2 V
CC
−
−
0.85
0.85
1.9
1.9
W
W
DS(on)
V
= 3.15 V
Output Low R
(sink)
R
LS
Iout = 500 mA, Vs = 13.2 V
DS(on)
DSon
V
CC
= 3.15 V
Source Leakage Current
Sink Leakage Current
V
= 5 V, OUT(1−12) = 0 V, EN = 0/5 V
CC
IsrcLkg13.2 VSx = 13.2 V
IsrcLkg28 VSx = 28 V
−1.0
−2.0
−
−
−
−
mA
mA
V
CC
= 5 V, EN = 0/5 V
IsnkLkg13.2 OUT(1−12) = VSx = 13.2 V
−
−
−
−
1.0
2.0
mA
mA
IsnkLkg28
OUT(1−12) = VSx = 28 V
Overcurrent Shutdown Threshold
(Source)
IsdSrc
V
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
−2.0
−1.5
−1.1
A
CC
CC
Overcurrent Shutdown Threshold
(Sink)
IsdSnk
V
1.1
1.5
2.0
A
Over Current Delay Timer
TdOc
10
25
50
ms
Underload Detection Threshold
(Low Side)
IuldLS
V
V
V
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
−
2.5
5.5
mA
CC
CC
CC
Underload Detection Threshold
(High Side)
IuldHS
−5.5
−2.5
−
mA
Underload Detection Delay Time
Body Diode Forward Voltage
TdUld
200
350
0.9
600
1.3
ms
IbdFwd
If = 500 mA
−
V
DRIVER OUTPUT SWITCHING CHARACTERISTICS
High Side Turn On Time
High Side Turn Off Time
Low Side Turn On Time
Low Side Turn Off Time
ThsOn
ThsOff
TlsOn
TlsOff
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
= 70 W
= 70 W
= 70 W
= 70 W
−
−
−
−
7.5
3.0
6.5
2.0
13
6.0
13
ms
ms
ms
ms
load
load
load
load
5.0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Not production tested.
4. This is the minimum time the user must wait between SPI commands.
5. This is the minimum time the user must wait between consecutive SRR requests.
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NCV7726B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.)
J
CC
CC
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
DRIVER OUTPUT SWITCHING CHARACTERISTICS
High Side Rise Time
High Side Fall Time
Low Side Rise Time
Low Side Fall Time
ThsTr
ThsTf
TlsTr
TlsTf
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
−
−
4.0
2.0
1.0
1.0
−
8.0
4.0
3.0
3.0
−
ms
ms
ms
ms
ms
load
load
load
load
load
−
−
High Side Off to Low Side On
Non−Overlap Time
ThsOffLsOn Vs = 13.2 V, R
1.5
Low Side Off to High Side On
Non−Overlap Time
TlsOffHsOn Vs = 13.2 V, R
= 70 W
1.5
−
−
ms
load
THERMAL RESPONSE
Thermal Warning
Twr
TwHy
Tsd
(Note 3)
(Note 3)
(Note 3)
(Note 3)
120
−
140
20
170
−
°C
°C
°C
°C
Thermal Warning Hysteresis
Thermal Shutdown
150
−
175
20
200
−
Thermal Shutdown Hysteresis
LOGIC INPUTS − EN, SI, SCLK, CSB
TsdHy
Input Threshold
High
Low
VthInH
VthInL
2.0
−
−
−
−
0.6
V
V
Input Hysteresis − SI, SCLK, CSB
Input Hysteresis − EN
VthInHys
VthENHys
Rpdx
150
400
125
125
−
mV
mV
kW
kW
pF
150
50
50
−
800
200
250
15
Pull−down Resistance − EN, SI, SCLK
Pull−up Resistance − CSB
Input Capacitance
EN = SI = SCLK = V
CSB = 0 V
CC
RpuCSB
Cinx
(Note 3)
LOGIC OUTPUT − SO
Output High
VsoH
ISOURCE = −1 mA
V
CC
0.6
–
−
−
V
Output Low
VsoL
ISINK = 1.6 mA
CSB = 5 V
−
−5
−
−
−
−
0.4
5
V
Tri−state Leakage
Tri−state Output Capacitance
ItriStLkg
ItriStCout
mA
pF
CSB = V , 0 V < V < 5.25 V
15
CC
CC
(Note 3)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Not production tested.
4. This is the minimum time the user must wait between SPI commands.
5. This is the minimum time the user must wait between consecutive SRR requests.
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NCV7726B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.)
J
CC
CC
Characteristic
Symbol
Conditions
Timing
Min
Typ
Max
Unit
Charts #
SERIAL PERIPHERAL INTERFACE
SCLK Frequency
Fclk
−
−
−
−
5.0
MHz
ns
SCLK Clock Period
TpClk
V
CC
V
CC
= 5 V
= 3.3 V
200
500
−
−
−
−
SCLK High Time
TclkH
TclkL
1
2
85
85
85
50
50
100
5.0
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
SCLK Low Time
SCLK Setup Time
SI Setup Time
TclkSup
TsiSup
TsiH
3, 4
11
12
5, 6
7
−
−
−
−
SI Hold Time
−
−
CSB Setup Time
TcsbSup
TcsbH
TenSo
TdisSo
TsoR/F
TsoV
−
−
CSB High Time
(Note 4)
−
−
SO enable after CSB falling edge
SO disable after CSB rising edge
SO Rise/Fall Time
SO Valid Time
8
−
200
200
25
100
9
−
−
Cload = 40 pF (Note 3)
−
−
10
50
Cload = 40 pF (Note 3)
SCLK ↑ to SO 50%
10
−
EN Low Valid Time
EN High to SPI Valid
TenL
V
= 5V; EN H→L 50%
−
10
−
−
ms
CC
to OUTx turning off 50%
TenHspiV
Tsrr
−
−
−
−
−
100
ms
ms
SRR Delay Between Consecutive
Frames
(Note 5)
150
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Not production tested.
4. This is the minimum time the user must wait between SPI commands.
5. This is the minimum time the user must wait between consecutive SRR requests.
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NCV7726B
CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
10%
LS Turn OFF
HS Turn ON
TlsOffHsOn
90%
10%
ThsTr
90%
ThsOn
CSB
LS Turn On
HS Turn Off
TlsTf
90%
TlsOn
10%
ThsOffLsOn
90%
10%
ThsTf
90%
ThsOff
CSB
Figure 4. Detailed Driver Timing
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NCV7726B
4
7
CSB
5
SCLK
3
1
2
6
CSB
SO
9
8
SI
12
SCLK
SO
11
10
Figure 5. Detailed SPI Timing
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NCV7726B
TYPICAL CHARACTERISTICS
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.30
VSx = 13.2 V
VSx = 13.2 V
2.25
2.20
2.15
2.10
150°C
125°C
V
V
= 5.25 V
= 5.00 V
CC
CC
25°C
−40°C
V
CC
= 3.15 V
2.05
2.00
0.5
0
−50
0
50
TEMPERATURE (°C)
100
150
150
150
3.0
3.5
4.0
4.5
5.0
5.5
V
, VOLTAGE (V)
CC
Figure 6. IqTot vs. Temperature
Figure 7. I(VCC) Active Mode vs. V(VCC)
2.0
1.8
1.05
1.00
0.95
0.90
0.85
VSx = 13.2 V
1.6
1.4
1.2
1.0
LSx
HSx
LSx
HSx
0.80
0.75
I = 0.5 A
f
0.8
0.6
−50
0
50
100
−50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
Figure 8. RDS(on) vs. Temperature
Figure 9. Body Diode Voltage vs. Temperature
2.0
1.5
1.0
0.5
0
0.02
0
LSx
−0.02
−0.04
VSx = 13.2 V
−0.06
−0.08
−0.10
V
CC
= 5.0 V
LSx
−0.5
−1.0
HSx
−0.12
−0.14
−1.5
−2.0
HSx
150
−50
0
50
TEMPERATURE (°C)
100
−50
0
50
100
200
TEMPERATURE (°C)
Figure 10. Over Current vs. Temperature
Figure 11. Leakage vs. Temperature
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NCV7726B
DETAILED OPERATING DESCRIPTION
SPI Communication
General Overview
The NCV7726B is comprised of twenty four NMOS
power drivers. The drivers are arranged as twelve
half−bridge output channels, allowing for six independent
full−bridge configured loads. Output control and status
reporting is handled via the SPI (Serial Peripheral Interface)
communications port.
Each output is characterized for a typical 0.5 A DC load
and has a maximum 2.0 A surge capability (at VSx =
13.2 V). Maximum allowable junction temperature is 150°C
and may constrain the maximum load current and/or limit
the number of drivers active at once.
An active−high enable function (EN) allows global
control of the outputs and provides a low quiescent current
sleep mode when the device is not being utilized. An internal
pull−down resistor is provided on the input to ensure the
device enters sleep mode if the input signal is lost.
16−bit full duplex SPI communication has been
implemented for device configuration, driver control, and
reading the status data. In addition to the 16−bit status data,
a pseudo−bit (PRE_15) can also be retrieved from the SO
output.
The device must be enabled (EN = H) for SPI
communication. The SPI inputs are TTL compatible and the
SO output high level is defined by the applied V . The
CC
active−low CSB input has a pull−up resistor and the
remaining inputs have pull−down resistors to bias them to
known states when SPI communication is inactive.
The latched thermal shutdown (TSD) status bit PRE_15
is available on SO until the first rising SCLK edge after CSB
goes low. The following conditions must be met for a valid
TSD read to be captured:
1. SCLK and SI are low before the CSB cycle;
2. CSB transitions from high to low;
After EN transitions from low to high, the V POR cycle
CC
will proceed and bring the device into normal operation. The
device configuration registers can then be programmed via
SPI. Bringing EN low clears all registers (no configuration
or status data is stored), disables the drivers, and enters sleep
mode.
3. CSB setup time (TcsbSup: Figure 5, #5) is
satisfied.
Figure 12 shows the SPI communication frame format,
and Tables 1 and 2 define the command input and diagnostic
status output bits.
CSB
B[12:7] → HBEN[6:1]
B[12:7] " HBEN[12:7]
B[6:1] → HBCNF[6:1]
B[6:1] " HBCNF[12:7]
SRR
HBSEL
ULDSC
OVLO
SI
SCLK
SO
15
14
13
0
B[12:7] → HBST[6:4]
B[12:7] " HBST[12:10]
B[6:1] → HBST[3:1]
B[6:1] " HBST[9:7]
TSD
OCS
PSF
ULD
TW
PRE_15
PSEUDO−BIT
Figure 12. SPI Communication Frame Format
Communication is implemented as follows and is also
illustrated in Figures 12 and 15:
5. Current SO data is simultaneously shifted out on
every rising edge of SCLK, starting with the MSB
(OCS).
6. CSB goes high to end the frame and SO becomes
tri−state.
7. The last 16 bits clocked into SI are transferred to
the device’s data register if no frame error is
detected, otherwise the entire frame is ignored and
the previous input data is preserved.
1. SI and SCLK are set to low before the CSB cycle.
2. CSB goes low to begin a serial data frame;
pseudo−bit PRE_15 is immediately available at
SO.
3. SI data is shifted in on every rising edge of SCLK,
starting with the most significant bit (MSB), SRR.
4. SI data is recognized on every falling edge of the
SCLK.
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12
NCV7726B
Table 1. SPI COMMAND INPUT DEFINITIONS
Channels 12 – 7 (Input Bit # 14 = 1)
Bit#
15
Name
SRR
Function
Status*
1 = Reset
Scope
Status Register Reset**
Channel Group Select
Status Reset per HBSEL
1 = HB [12:7] | 0 = HB [6:1]
14
HBSEL
ULDSC
1 = HB [12:7]
1 = Enabled
13
Underload Shutdown Control
Enabled per HBSEL;
Per Half−Bridge Operation
12
11
10
9
HBEN12
HBEN11
HBEN10
HBEN9
Enable Half−Bridge 12
Enable Half−Bridge 11
Enable Half−Bridge 10
Enable Half−Bridge 9
0 = Hi−Z
Per Half−Bridge
1 = Enabled
8
HBEN8
Enable Half−Bridge 8
7
HBEN7
Enable Half−Bridge 7
6
HBCNF12
HBCNF11
HBCNF10
HBCNF9
HBCNF8
HBCNF7
OVLO
Configure Half−Bridge 12
Configure Half−Bridge 11
Configure Half−Bridge 10
Configure Half−Bridge 9
Configure Half−Bridge 8
Configure Half−Bridge 7
VSx Overvoltage Lockout
5
0 = LS On, HS Off
1 = LS Off, HS On
4
Per Half−Bridge
3
2
1
0
1 = Enabled
Global Lockout
Channels 6 – 1 (Input Bit # 14 = 0)
Bit#
15
Name
SRR
Function
Status*
1 = Reset
Scope
Status Register Reset**
Channel Group Select
Status Reset per HBSEL
1 = HB [12:7] | 0 = HB [6:1]
14
HBSEL
ULDSC
0 = HB [6:1]
1 = Enabled
13
Underload Shutdown Control
Enabled per HBSEL;
Per Half−Bridge Operation
12
11
10
9
HBEN6
HBEN5
HBEN4
HBEN3
HBEN2
HBEN1
HBCNF6
HBCNF5
HBCNF4
HBCNF3
HBCNF2
HBCNF1
OVLO
Enable Half−Bridge 6
Enable Half−Bridge 5
Enable Half−Bridge 4
Enable Half−Bridge 3
Enable Half−Bridge 2
Enable Half−Bridge 1
Configure Half−Bridge 6
Configure Half−Bridge 5
Configure Half−Bridge 4
Configure Half−Bridge 3
Configure Half−Bridge 2
Configure Half−Bridge 1
VSx Overvoltage Lockout
0 = Hi−Z
Per Half−Bridge
1 = Enabled
8
7
6
5
0 = LS On, HS Off
1 = LS Off, HS On
4
Per Half−Bridge
3
2
1
0
1 = Enabled
Global Lockout
*All command input bits are set to 0 at V power−on reset.
CC
**Latched faults are cleared and outputs can be re−programmed if no fault exists after SRR asserted.
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13
NCV7726B
Table 2. SPI STATUS OUTPUT DEFINITIONS
Channels 12 – 7 (If Previous Input Bit # 14 = 1)
Bit#
Name
Function
Status*
Scope
PRE_15
TSD
Latched Thermal Shutdown
1 = Fault
Global Notification;
Per Half−Bridge Operation
15
14
13
OCS
PSF
Latched Overcurrent
Shutdown
1 = Fault
1 = Fault
1 = Fault
Notification per HBSEL;
Per Half−Bridge Operation
VS1 and/or VS2
Undervoltage or Overvoltage
Global Notification and
Global Operation
ULD
Underload Detect
Notification per HBSEL;
Per Half−Bridge Operation
12
11
10
9
HBST12 [1:0]
Half−Bridge 12 Output Status
HBST11 [1:0]
HBST10 [1:0]
HBST9 [1:0]
HBST8 [1:0]
HBST7 [1:0]
TW
Half−Bridge 11 Output Status
Half−Bridge 10 Output Status
Half−Bridge 9 Output Status
Half−Bridge 8 Output Status
Half−Bridge 7 Output Status
Thermal Warning
8
0x00b − Output Disabled
0x01b − OCS
7
Per Half−Bridge
0x10b − ULD
6
0x11b − Output Enabled
5
4
3
2
1
0
1 = Fault
Global Notification;
Per Half−Bridge Operation
*All status output bits are set to 0 at Vcc power−on reset (POR).
HBSTx[1:0] bits are priority encoded to provide the status information of each of the half−bridge outputs. Figure 13 shows the priority encod-
ing state diagram for the HBSTx[1:0] bits.
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14
NCV7726B
Table 2. SPI STATUS OUTPUT DEFINITIONS
Channels 6 – 1 (If Previous Input Bit # 14 = 0)
Bit#
Name
Function
Status*
Scope
PRE_15
TSD
Latched Thermal Shutdown
1 = Fault
Global Notification;
Per Half−Bridge Operation
15
14
13
OCS
PSF
Latched Overcurrent
Shutdown
1 = Fault
1 = Fault
1 = Fault
Notification per HBSEL;
Per Half−Bridge Operation
VS1 and/or VS2
Undervoltage or Overvoltage
Global Notification and
Global Operation
ULD
Underload Detect
Notification per HBSEL;
Per Half−Bridge Operation
12
11
10
9
HBST6 [1:0]
Half−Bridge 6 Output Status
HBST5 [1:0]
HBST4 [1:0]
HBST3 [1:0]
HBST2 [1:0]
HBST1 [1:0]
TW
Half−Bridge 5 Output Status
Half−Bridge 4 Output Status
Half−Bridge 3 Output Status
Half−Bridge 2 Output Status
Half−Bridge 1 Output Status
Thermal Warning
8
0x00b − Output Disabled
0x01b − OCS
7
Per Half−Bridge
0x10b − ULD
6
0x11b − Output Enabled
5
4
3
2
1
0
1 = Fault
Global Notification;
Per Half−Bridge Operation
*All status output bits are set to 0 at Vcc power−on reset (POR).
HBSTx[1:0] bits are priority encoded to provide the status information of each of the half−bridge outputs. Figure 13 shows the priority encod-
ing state diagram for the HBSTx[1:0] bits.
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15
NCV7726B
PSF, TSD
HBENx = ‘0’
Output Enabled
“11”
Under
Load
Power On Reset
HBENx = ‘1’
PSF Recovery*
TSD Recovery**
Output Disabled
“00”
ULD
“10”
Over
Current
(default)
PSF
TSD
Over
Current
OCS
“01”
PSF
TSD
SRR = ‘1’
Power On Reset
*PSF Recovery: VSx rising above the undervoltage threshold or falling below the overvoltage threshold (OVLO = 1)
**TSD Recovery: Sending SRR after junction temperature has fallen below the thermal shutdown threshold
Figure 13. SO HBSTx [1:0] Priority Encoding State Diagram
Priority Encoding
CSB and SCLK are parallel connected to every device in
the chain while SO and SI are series connected between each
device. The master’s MOSI is connected to the SI of the first
device and the first device’s SO is connected to the next
device’s SI. The SO of the final device in the chain is
connected to the master’s MISO.
The hardware configuration for the NCV7726B daisy
chained with an 8− bit SPI device is shown in Figure 14. A
24−bit frame made of 16−bit word ‘A’ and 8−bit word ‘B’ is
sent from the master. Command word B is sent first followed
by word A. The master simultaneously receives status word
B first followed by word A. The progression of data from the
MCU through the sequential devices is illustrated in
Figure 14.
Compliance with the illustrated frame format is required
for proper daisy chain operation. Situations should be
avoided where an incorrect multiple of 8 bits is sent to the
devices, but the frame length does not cause a frame error in
the devices. For example, the word order could be
inadvertently interleaved or reversed. Invalid data is
accepted by the NCV7726B in such scenarios and possibly
by other devices in the chain, depending on their frame error
implementation. Data is received as a command by the
device at the beginning of the chain, but the device at the end
of the chain may receive status data from the preceding
device as a command.
If an under load event precedes an over current event on
the same half−bridge, the device will report HBSTx = ‘10’
and then HBSTx = ‘01’ as shown in Figure 13. An over
current event preceding an under load event only reports
HBSTx = ‘01’ since there is no direct path from the OCS
state to the ULD state. Thus an over current shutdown fault
must be cleared before an underload fault is reported on the
same half−bridge.
Frame Error Detection
The NCV7726B employs frame error detection to help
ensure input data integrity. SCLK is compared to an n x 8 bit
counter and a valid frame (CSB H−L−H cycle) has integer
multiples of 8 SCLK cycles. For the first 16 bits shifted into
SI, SCLK is compared to a modulo16 counter (n = 2), and
SCLK is compared to a modulo 8 counter (n = 1, 2, ...m)
thereafter. This variable modulus facilitates daisy chain
operation with devices using different word lengths.
The last 16 bits clocked into SI are transferred to the
NCV7726B’s data register if no frame error is detected,
otherwise the entire frame is ignored and the previous input
data is preserved.
Daisy Chain Operation
Daisy chain operation is possible with multiple 16−bit and
8−bit devices that have a compatible SPI protocol. The clock
phase and clock polarity with respect to the data for all the
devices in the chain must be the same as the NCV7726B.
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16
NCV7726B
CMD [x, n] = Command Word to Device ‘x’, Length ‘n’
STA [x, n] = Status Word from Device ‘x’, Length ‘n’
NCV7726B
8−bit Device
MCU
16−bit Device
CSB
CSB
CSB
SCLK
MOSI
SCLK
SI
SCLK
SI
MISO
SO
SO
STA [B, 8]
+
STA [A, 16]
CMD [B, 8]
+
CMD [A, 16]
STA [A, 16]
+
CMD [B, 8]
Device A
Master
Device B
Figure 14. Daisy Chain Configuration
24bit Frame
Word B − 8 bits
Word A − 16 bits
CSB
SCLK
SI
7
6
1
0
15
8
7
0
MSB
LSB
LSB
MSB
LSB
SI data is recognized on the falling SCLK. edge
SO
TSD
MSB
MSB
LSB
SO data is shifted out on the rising SCLK edge.
Modulo 16 counter begins on the first rising SCLK edge after CSB goes low.
Modulo 16 counter ends − 16 bit word length valid.
Modulo 8 counter begins on the next rising SCLK edge.
Modulo 8 counter ends − 8 bit word length valid. valid n*8 bit frame.
Figure 15. Daisy Chain – 24 bit Frame Format
TSD Bit in Daisy Chain Operation
The TSD status automatically propagates through the
chain from the SO output of the previous device to the SI
input of the next. This is shown in Figures 17 and 18, first
without a TSD fault in either device (Figure 17), and then
subsequently with a latched TSD fault (TSD = 1) in device
“A” propagating through to device “B” (Figure 18).
The SO path is designed to allow TSD status retrieval in
a daisy chain configuration using NCV7726B or other
devices with identical SPI functionality. The TSD status bit
is OR’d with SI and then multiplexed with the device’s usual
status data (Figure 16).
CSB is held high and SI and SCLK are held low by the
master before the start of the SPI frame. TSD status is
immediately available as bit PRE_15 at SO (SO = TSD)
when CSB goes low to begin the frame. The usual status data
(SO = STA) becomes available after the first rising SCLK
edge.
Since the TSD status of any device propagates
automatically through the entire chain, it is not possible to
determine which device (or devices) has a fault (TSD = 1).
The usual status data from each device will need to be
examined to determine where a fault (or faults) may exist.
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17
NCV7726B
SI
M
U
X
TSD
SO
SO
SI
SPI
SEL
Figure 16. TSD SPI Link
NCV7726B
NCV7726B
or NCV7723B
MCU
CSB
CSB
CSB
1³0
0
SCLK
MOSI
SCLK
SCLK
SI
Z³
Z³
0
0
0
MISO
SI
SO
SO
Device A
No TSD
Master
Device B
No TSD
Figure 17. Daisy Chain Without TSD Fault
NCV7726B
NCV7726B
or NCV7723B
MCU
CSB
CSB
CSB
1³0
0
SCLK
MOSI
SCLK
SI
SCLK
SI
Z³
Z³
0
1
1
MISO
SO
SO
Device A
Master
Device B
No TSD
Latched TSD
Figure 18. Daisy Chain With TSD Fault
Power Up/Down Control
Output drivers will remain if OVLO = 0 during an
overvoltage condition.
The V supply input powers the device’s logic core. A
CC
V
CC
power−on reset (POR) function provides controlled
Driver Control
power−up/down. V POR initializes the command input
CC
The NCV7726B has the flexibility to control each
half−bridge driver channel via SPI. Actual driver output
state is determined by the command input and the current
fault status bits.
The channels are divided into two groups and each group
is selected by the HBSEL input bit (see Table 1). High−side
(HSx) and low−side (LSx) drivers of the same channel
cannot be active at the same time, and non−overlap delays
are imposed when switching between HSx and LSx drivers
in the same channel, preventing current shoot−through.
After the device has powered up and the drivers are
allowed to turn on, the drivers remain on until commanded
off via SPI or until a fault condition occurs.
and status output registers to their default states (0x00), and
ensures that the bridge output and SO drivers maintain Hi−Z
as power is applied. SPI communication and normal device
operation can proceed once V
threshold and EN remains high.
The VS1 and VS2 supply inputs power their respective
output drivers (refer to Figure 2 and the PIN FUNCTION
DESCRIPTION). The VSx inputs are monitored to ensure
that the supply stays within the recommended operating
range. If the VSx supply moves into either of the VS
undervoltage or overvoltage regions, the output drivers are
switched to Hi−Z but command and status data is preserved.
rises above the POR
CC
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18
NCV7726B
DIAGNOSTICS, PROTECTIONS, STATUS REPORTING AND RESET
Overview
intervention for output recovery and status memory clear.
Diagnostics resulting in output lockout and non−latched
status (VSOV or VSUV) may recover and clear
automatically. Output configurations can be changed during
output lockout. Outputs assume the new configurations or
resume the previous configurations when an auto−recover
fault is resolved. Table 4 shows output states during faults
and output recovery modes, and Table 5 shows the status
memory and memory clear modes.
The NCV7726B employs diagnostics designed to prevent
destructive overstress during a fault condition. Diagnostics
are classified as either supervisory or protection functions
(Table 3). Supervisory functions provide status information
about device conditions. Protection functions provide status
information and activate fault management behaviors.
Diagnostics resulting in output shutdown and latched
status may depend on a qualifier and may require user
Table 3. DIAGNOSTIC CLASSES AND FUNCTIONS
Name
TSD
Class
Function
Thermal Shutdown
Protection
Protection
Protection
Protection
Supervisory
Supervisory
OCS
Overcurrent Shutdown
Under/overvoltage Lockout (OVLO = 1)
Underload Shutdown
PSF
ULD
HBSTx[1:0]
TW
Half−Bridge X Output Status
Thermal Warning
Table 4. OUTPUT STATE VS. FAULT AND OUTPUT RECOVERY
OUTx
State
OUTx
Recovery
OUTx
Recovery Scope
Fault
TSD
Qualifier
−
→Z
→Z
Send SRR
Per HBSEL
Per HBSEL
All Outputs
−
OCS
−
Send SRR
PSF – VSOV
OVLO = 1
OVLO = 0
−
→Z→Y | Y
Auto*
n
n+1
Unaffected
−
PSF – VSUV
ULD
→Z→Y | Y
Auto*
All Outputs
Per HBSEL
−
n
n+1
ULDSC = 1
ULDSC = 0
−
→Z
Send SRR
Unaffected
Unaffected
−
−
TW
−
*OUTx returns to its previous state (Y ) or new state (Yn+1) if fault is removed.
n
Table 5. STATUS MEMORY VS. FAULT AND MEMORY CLEAR
Status
Memory
Memory
Clear
Memory
Clear Scope
Fault
TSD
Qualifier
−
Latched
Latched
Send SRR
Send SRR
Auto*
Per HBSEL
Per HBSEL
Global
OCS
−
PSF – VSOV
PSF – VSUV
ULD
OVLO = X
Non−Latched
Non−Latched
Latched
−
Auto*
Global
ULDSC = X
Send SRR
Auto*
Per HBSEL
Global
TW
−
Non−Latched
*Status memory returns to its no−fault state if fault is removed.
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19
NCV7726B
Status Information Retrieval
Diagnostics Details
Current status information as selected by HBSEL is
retrieved during each SPI frame. To preserve device
configuration and output states, the previous SI data pattern
must be sent during the status retrieval frame.
Status information is prevented from being updated
during a SPI frame but new status becomes available after
CSB goes high at the end of the frame provided the frame did
not contain an SRR request. Status information includes
both global and per channel fault notification. To determine
the channel(s) affected after detecting a global fault,
examine driver output status and input configuration.
The following sections describe individual diagnostics
and behaviors. In each description and illustration, a SPI
frame is assumed to always be valid and the SI data pattern
sent for HBCNFx and HBENx is the same as the previous
frame. Actual results can depend on asynchronous fault
events and SPI clock frequency and frame rate.
Undervoltage Lockout
Global Notification, Global Operation
Undervoltage detection and lockout control is provided
by monitoring the VS1, VS2 and V
supply inputs.
CC
Undervoltage hysteresis is provided to ensure clean
detection transitions. Undervoltage timing is shown in
Figure 19.
Undervoltage at either VSx input turns off all outputs and
sets the power supply fail (PSF) status bit. The outputs return
to their previously programmed state and the PSF status bit
is cleared when VSx rises above the hysteresis voltage level.
SPI communication is available and programmed output
Status Register Reset − SRR
Sending SRR = 1 clears status memory and re−activates
faulted outputs for channels as selected by HBSEL. The
previous SI data pattern must be sent with SRR to preserve
device configuration and output states. At the rising edge of
CSB, the SRR function is activated and an internal timer
(Tsrr) is started. Tsrr is the minimum time the user must wait
between consecutive SRR requests. If a fault is still present
when SRR is sent, protection will be re−engaged and
shutdown will recur. The status registers can also be reset by
toggling the EN pin or by VCC power−on reset.
enable and configuration states are maintained if proper V
CC
is present during VSx undervoltage. Output enable and
configuration states can also be programmed during VSx
undervoltage if proper VCC is present, and state changes
will take effect as VSx rises above the undervoltage
threshold level.
V
CC
undervoltage turns all outputs off and clears the
command input and status output registers.
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
HS
OUTx
HS
OUTx
HS
SI
No
No
No
SO
X
PSF
PSF
Z
?
0x00
0x00
Fault
Fault
Fault
No
Fault
No
Fault
Status
No Fault
?
Output
State
ALL
Z
ALL
Z
OUTx GND
OUTx VS
?
OUTx GND
VSx
Vcc
VSUV
VccUV
t
Figure 19. Undervoltage Timing
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20
NCV7726B
Overvoltage Lockout
programmed state and the PSF status bit is cleared when
VSx falls below the hysteresis voltage level. Output enable
and configuration states can also be programmed during an
overvoltage lockout event but will not change state until
VSx falls below the overvoltage threshold level.
To reduce stress, it is recommended to operate the device
with OVLO bit asserted to ensure that the drivers turn off
during a load dump scenario. If OVLO = 0 during an
overvoltage condition, outputs will remain on and the PSF
status bit will be set.
Global Notification, Global Operation
Overvoltage detection and lockout control is provided by
monitoring the VS1 and VS2 supply inputs. Overvoltage
hysteresis is provided to ensure clean detection transitions.
Overvoltage timing is shown in Figure 20.
Overvoltage at either VSx input turns off all outputs if the
overvoltage lockout input bit is set (OVLO = 1, HBSEL =
X), and sets the power supply fail (PSF) status bit (see
Tables 4 and 5). The outputs return to their previously
OUTx ON
OVLO=0
OUTx
ON
OUTx
ON
OUTx ON
OVLO=1
OUTx
ON
OUTx
OFF
SI
SO
No
Fault
No
Fault
No
Fault
X
PSF
PSF
PSF
PSF
No
Fault
No
Fault
No
Fault
No
Fault
Status
?
?
Output
State
OUTx
ON
ALL
Z
OUTx
ON
OUTx Z
VSOV
VSOV
VSx
t
Figure 20. Overvoltage Timing
Overcurrent Shutdown
global overcurrent (OCS) status bit is set. The channel’s
corresponding HBSTx[1:0] bits are also set to “01” to
indicate an OCS fault. Note that OCS fault reporting has
priority over other faults as shown in Figure 13. The global
OCS bit and individual channel bits are cleared and channels
are re−activated by sending SRR = 1 (HBSEL = X).
A persistent overcurrent cause should be resolved prior to
re−activation to avoid repetitive stress on the drivers.
Global and per Channel Notification per HBSEL
Per Half−Bridge Operation
Overcurrent detection and shutdown control is provided
by monitoring each HS and LS driver. Overcurrent timing is
shown in Figure 21. Overcurrent in either driver starts a
channel’s overcurrent delay timer (TdOc). If overcurrent
exists after the delay, both drivers are latched off and the
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21
NCV7726B
OUTx ON
SRR=0
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx
ON
OUTx
ON
SI
No
Fault
No
Fault
No
SO
OCS
OCS
OCS
OCS
Fault
No
Fault
No
Fault
Status
OCS
Output
State
OUTx
ON
OUTx
ON
OUTx Z
OUTx Z
TdOc
TdOc
Output
Current
IsdSxx
t
Figure 21. Overcurrent Timing
Underload Shutdown
drivers are latched off and the global underload (ULD) status
bit is set along with the corresponding per channelstatus bits
HBSTx[1:0] set to “10”. Drivers will remain on if the
ULDSC input bit is 0 (see Table 4 and 5). The global ULD
bit and per channel HBSTx bits are cleared and channels are
re−activated by sending SRR = 1 (HBSEL = X).
Note: underload may result from a fault (e.g. open−load)
condition or normal circuit behavior (e.g. L/R tau). In motor
applications it is often desirable to actively brake the motor
by turning on both HS or LS drivers in two half−bridge
channels which may result in an underload condition as
current decays.
Global and per Channel Notification per HBSEL
Shutdown Control per HBSEL
Per Half−Bridge Operation
Underload detection and shutdown control is provided by
monitoring each half bridge driver. Underload timing is
shown in Figure 22. Underload at any driver starts the global
underload delay timer. If underload occurs in another
channel after the global timer has been started, the delay for
any subsequent underload will be the remainder of the timer.
If underload exists after the delay and if the underload
shutdown (ULDSC) command bit is set, both HS and LS
LSx
ON
LSx ON
LSx
ON
LSx ON
SRR=1
LSx ON
LSx ON
SRR=1
SI
SO
ULDSC=0
ULDSC=1
No
Fault
No
Fault
No
Fault
ULD
ULD
ULD
ULD
No
Fault
Status
No Fault
No Fault
ULD
Output
State
OUTx
Z
OUTx
ON
OUTx GND
TdUld
IuldLS
OUTx GND
TdUld
TdUld
Output
Current
t
Figure 22. Underload Timing
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22
NCV7726B
Thermal Warning and Thermal Shutdown
The TW status bit is set when a half−bridge’s sensor
temperature exceeds the warning level (T > Twr), and the
bit is automatically cleared when sensor temperature falls
J
Global Notification, Per Half−Bridge Operation
Thermal warning (TW) and thermal shutdown (TSD)
detection and control are provided for each half−bridge by
monitoring the driver pair’s thermal sensor. Thermal
hysteresis is provided for each of the warning and shutdown
functions to ensure clean detection transitions. Software
polling of the TW bit allows for avoidance of thermal
shutdown since TW notification precedes TSD notification.
Thermal warning and shutdown timing is shown in
Figure 23.
below the warning hysteresis level (T < TwHy). A
J
channel’s output state is unaffected by TW.
When sensor temperature exceeds the shutdown level (T
J
> Tsd), the channel’s HS and LS drivers are latched off, the
TW bit is/remains set, and the TSD (PRE_15) bit is set. The
TSD bit is cleared and all affected channels are re−activated
(T < TsdHy) by sending SRR = 1. The channel group select
J
(HBSEL) input bit determines which channels are affected
by SRR.
OUTx
ON
OUTx
ON
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx ON
SRR=1
SI
No
Fault
TSD
TW
No
SO
TW
TW
TW
TW
TW
TW
Fault
No
Fault
No
Fault
TSD
TW
Status
TW
Output
State
OUTx
ON
OUTx Z
OUTx ON
TJ
TSD
TsdHy
TWR
TwHy
t
Figure 23. Thermal Warning and Shutdown Timing
The latched thermal shutdown (TSD) information is available on SO after CSB goes low until the first rising SCLK edge.
The following procedures must be met for a true TSD reading:
1. SCLK and SI are low before the CSB cycle. Violating these conditions will results in an undetermined SPI behavior
or/and an incorrect TSD reading.
2. CSB transitioning from high to low.
3. CSB setup time (TcsbSup) is satisfied and the data is captured before the first SCLK rising edge.
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23
NCV7726B
THERMAL PERFORMANCE ESTIMATES
Figure 24. Transient R(t) vs. Pulse Time for 2 oz Spreader
ORDERING INFORMATION
Device
†
Package
Shipping
NCV7726DQBR2G
SSOP24 EP
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
SCALE 1:1
DATE 24 APR 2012
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
A2
h
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.70
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
5.28
5.58
D2
6.00 BSC
3.90 BSC
2.44 2.64
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
GENERIC
MARKING DIAGRAM*
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXXXXXXXG
AWLYYWW
5.63
XXXX = Specific Device Code
24X
1.15
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
2.84
6.40
(Note: Microdot may be in either location)
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79998E
SSOP24 NB EP
PAGE 1 OF 1
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相关型号：
NCV77320DB0R2G
Inductive Position Sensor interface; analog, SPI and SENT output; ISO26262 ASIL B (D); Automotive; Industrial
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