NCV8130 [ONSEMI]
Very Low Dropout Bias Rail CMOS Voltage Regulator;
| 型号： | NCV8130 |
| 厂家： | 
ONSEMI |
| 描述： | Very Low Dropout Bias Rail CMOS Voltage Regulator |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV8130
300 mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCV8130 is a 300 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (V ). The device
BIAS
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provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
T
MARKING
DIAGRAM
NCV8130 features low I consumption. The XDFN6 1.2 mm x
Q
1.2 mm package is optimized for use in space constrained
applications.
XDFN6
CASE 711AT
XX M
Features
• Input Voltage Range: 0.8 V to 5.5 V
• Bias Voltage Range: 2.4 V to 5.5 V
• Fixed Output Voltage Device
• Output Voltage Range: 0.8 V to 2.1 V
XX = Specific Device Code
M
= Date Code
PIN CONNECTIONS
•
1.5% Accuracy over Temperature, 0.5% V
@ 25°C
OUT
• Ultra−Low Dropout: 150 mV Maximum at 300 mA
• Very Low Bias Input Current of Typ. 80 mA
• Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
• Logic Level Enable Input for ON/OFF Control
• Output Active Discharge Option Available
• Stable with a 1 mF Ceramic Capacitor
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable; Device Temperature Grade 1: −40°C to
+125°C Ambient Operating Temperature Range
OUT
NC
IN
1
2
3
6
5
4
Thermal
Pad
GND
BIAS
EN
(Top VIew)
• These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
Typical Applications
page 9 of this data sheet.
• Automotive, Consumer and Industrial Equipment Point of Load
Regulation
• Battery−powered Equipment
• FPGA, DSP and Logic Power Supplies
• Switching Power Supply Post Regulation
• Cameras, DVRs, STB and Camcorders
V
BIAS
2.7 V
NCV8130
100 nF
BIAS
IN
OUT
V
OUT
1.0 V @ 300 mA
V
1.3 V
IN
1 mF
1 mF
EN
GND
V
EN
Figure 1. Typical Application Schematics
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2017 − Rev. 0
NCV8130/D
NCV8130
CURRENT
LIMIT
OUT
IN
ENABLE
BLOCK
EN
UVLO
BIAS
150 W
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
*Active
DISCHARGE
GND
*Active output discharge function is present only in NCV8130AMXyyyTCG devices.
yyy denotes the particular output voltage option.
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
OUT
N/C
Description
1
2
Regulated Output Voltage pin
Not internally connected (Note 1)
3
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode.
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit.
Ground pin
4
BIAS
GND
IN
5
6
Input Voltage Supply pin
Pad
Should be soldered to the ground plane for increased thermal performance.
1. True no connect. Printed circuit board traces are allowable
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2
NCV8130
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage (Note 2)
V
IN
−0.3 to 6
Output Voltage
V
OUT
−0.3 to (V +0.3) ≤ 6
V
IN
Chip Enable and Bias Input
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
V
V
−0.3 to 6
unlimited
150
V
EN, BIAS
t
s
SC
T
J
°C
°C
V
T
−55 to 150
2000
STG
ESD Capability, Human Body Model (Note 3)
ESD Capability, Machine Model (Note 3)
ESD
HBM
ESD
200
V
MM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Machine Model tested per AEC−Q100−003
Latchup Current Maximum Rating ≤ 150 mA per AEC−Q100−004.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
Max
5.5
Unit
V
Input Voltage
V
IN
(V
OUT
+ V
)
DO_IN
Bias Voltage
V
BIAS
(V
OUT
+ 1.35) ≥ 2.4
5.5
V
Junction Temperature
T
J
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, XDFN6 1.2 mm x 1.2 mm Thermal Resistance, Junction−to−Air
RqJA
170
°C/W
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3
NCV8130
ELECTRICAL CHARACTERISTICS
−40°C ≤ T ≤ 125°C; V
= 2.7 V or (V
+ 1.6 V), whichever is greater, V = V
= 1 mF (effective capacitance) (Note 4). Typical values are at T = +25°C. Min/Max
OUT J
+ 0.3 V, I
= 1 mA, V = 1 V, unless
J
BIAS
OUT
= 0.1 mF, C
IN
OUT(NOM)
OUT EN
otherwise noted. C = 1 mF, C
IN
BIAS
values are for −40°C ≤ T ≤ 125°C unless otherwise noted. (Note 5)
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Operating Input
Voltage Range
V
IN
V +V
OUT DO
5.5
V
Operating Bias Voltage
Range
V
(V
+1.35)
≥2.4
5.5
V
V
BIAS
OUT
Undervoltage Lock−out
V
Rising
UVLO
1.6
0.2
BIAS
Hysteresis
Output Voltage
Accuracy
−40°C ≤ T ≤ 125°C, V
+ 0.3 V ≤ V
≤
V
OUT
−1.5
+1.5
%
J
OUT(NOM)
IN
5.0 V, 2.7 V or (V
+ 1.6 V), whichever is
OUT(NOM)
greater < V
< 5.5 V, 1 mA < I
< 300 mA
BIAS
OUT
Output Voltage
Accuracy
V
OUT
0.5
%
V
V
Line Regulation
V
+ 0.3 V ≤ V ≤ 5.0 V
Line
Line
0.01
0.01
%/V
%/V
IN
OUT(NOM)
IN
Reg
Line Regulation 2.7 V or (V
+ 1.6 V), whichever is
OUT(NOM)
BIAS
Reg
greater < V
5.5 V
BIAS <
Load Regulation
I
I
I
= 1 mA to 300 mA
= 300 mA (Note 6)
Load
1.5
75
mV
mV
V
OUT
OUT
OUT
Reg
V
V
Dropout Voltage
V
V
175
1.4
IN
DO
Dropout Voltage
= 300 mA, V = V
(Notes 6, 7)
1.1
550
80
BIAS
IN
BIAS
DO
CL
Output Current Limit
V
V
= 90% V
= 2.7 V
I
400
950
110
mA
mA
OUT
BIAS
OUT(NOM)
Bias Pin Operating
Current
I
BIAS
Bias Pin Disable
Current
V
V
≤ 0.4 V
≤ 0.4 V
I
0.5
0.5
1.5
1.5
mA
mA
V
EN
EN
BIAS(DIS)
Vinput Pin Disable
Current
I
VIN(DIS)
EN Pin Threshold
Voltage
EN Input Voltage “H”
EN Input Voltage “L”
V
EN(H)
0.9
V
EN(L)
0.4
1.5
EN Pull Down Current
Turn−On Time
V
EN
= 5.5 V
I
0.3
mA
ms
EN
C
V
= 1 mF, From assertion of V to
= 98% V
t
150
OUT
OUT
EN
ON
, V
= 1.0 V
OUT(NOM) OUT(NOM)
Power Supply
Rejection Ratio
V
to V
, f = 1 kHz, I
+0.5 V
= 300 mA,
PSRR(V )
IN
65
80
40
dB
dB
IN
OUT
OUT
OUT
VIN ≥ V
V
to V
OUT
, f = 1 kHz, I
= 300 mA,
= 1.0 V,
PSRR(V
)
BIAS
VIN ≥ V
OUT
OUT
BIAS
+0.5 V
Output Noise Voltage
V
IN
= V
+0.5 V, V
V
N
mV
RMS
OUT
OUT(NOM)
f = 10 Hz to 100 kHz
Thermal Shutdown
Threshold
Temperature increasing
Temperature decreasing
160
140
150
°C
Output Discharge
Pull−Down
V
EN
≤ 0.4 V, V
= 0.5 V,
R
DISCH
W
OUT
NCV8130A options only
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
6. Dropout voltage is characterized when V
falls 3% below V
.
OUT
OUT(NOM)
7. For output voltages below 0.9 V, V
dropout voltage does not apply due to a minimum Bias operating voltage of 2.4 V.
BIAS
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4
NCV8130
APPLICATIONS INFORMATION
2.6 V − 4.2 V
VBAT
NCV8130
EN
DC/DC
GND
1.0 V
1.3 V V
OUT(NOM)
BIAS
OUT
1.3 V
LX
FB
IN
IN
EN
LOAD
GND
Processor
I/O
I/O
To other circuits
Figure 3. Typical Application: Low−Voltage Post−Regulator with ON/OFF functionality
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5
NCV8130
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.3 V, V
= 2.7 V, V = V
, V
= 1.0 V, I
= 300 mA,
J
IN
OUT(TYP)
BIAS
EN
BIAS
OUT(NOM)
OUT
C
= 1 mF, C
= 0.1 mF, and C = 1 mF (effective capacitance), unless otherwise noted.
OUT
IN
BIAS
300
100
90
80
70
60
50
40
30
20
I
= 300 mA
OUT
+125°C
250
200
150
100
+85°C
+25°C
−40°C
+125°C
+85°C
+25°C
−40°C
50
0
10
0
0
50
100
150
200
250
300
0.5 1.0
1.5
2.0
2.5
− V
3.0
3.5
4.0 4.5
I
, OUTPUT CURRENT (mA)
V
(V)
OUT
BIAS
OUT
Figure 4. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 5. VIN Dropout Voltage vs. (VBIAS
−
V
OUT) and Temperature TJ
200
180
1400
1300
1200
1100
1000
I
= 100 mA
OUT
−40°C
160
140
120
100
80
+25°C
+125°C
+125°C
+85°C
+85°C
60
+25°C
−40°C
40
900
800
20
0
0.5 1.0
1.5
2.0
2.5
− V
3.0
3.5
4.0
4.5
0
50
100
150
200
250
300
V
BIAS
(V)
I
OUT
, OUTPUT CURRENT (mA)
OUT
Figure 6. VIN Dropout Voltage vs. (VBIAS
VOUT) and Temperature TJ
−
Figure 7. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
140
200
180
120
100
80
160
140
120
100
80
+125°C
+85°C
+125°C
+85°C
60
+25°C
−40°C
60
40
+25°C
40
−40°C
20
0
20
0
0
50
100
150
200
250
300
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
I
, OUTPUT CURRENT (mA)
V
BIAS
OUT
Figure 8. BIAS Pin Current vs. IOUT and
Temperature TJ
Figure 9. BIAS Pin Current vs. VBIAS and
Temperature TJ
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6
NCV8130
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.3 V, V
= 2.7 V, V = V
, V
= 1.0 V, I
= 300 mA,
J
IN
OUT(TYP)
BIAS
EN
BIAS
OUT(NOM)
OUT
C
= 1 mF, C
= 0.1 mF, and C
= 1 mF (effective capacitance), unless otherwise noted.
IN
BIAS
OUT
800
700
600
500
400
300
200
+125°C
+85°C
+25°C
−40°C
100
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
− V (V)
V
BIAS
OUT
Figure 10. Current Limit vs. (VBIAS − VOUT
)
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7
NCV8130
APPLICATIONS INFORMATION
The NCV8130 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from V voltage. All the low current internal
best performance all the capacitors should be connected to
the NCV8130 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
IN
controll circuitry is powered from the V
voltage.
BIAS
The use of an NMOS pass transistor offers several
advantages in applications. Unlike a PMOS topology
devices, the output capacitor has reduced impact on loop
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
stability. V to V
operating voltage difference can be
IN
OUT
very low compared with standard PMOS regulators in very
low V applications.
IN
The NCV8130 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
NCV8130 is a Fixed Voltage linear regulator.
Dropout Voltage
Because of two power supply inputs V and V
and
then the pin should be connected to V or V
.
IN
BIAS
IN
BIAS
one V
regulator output, there are two Dropout voltages
OUT
Current Limitation
specified.
The first, the V Dropout voltage is the voltage
difference (V – V
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
IN
) when V
starts to decrease by
IN
OUT
OUT
percents specified in the Electrical Characteristics table.
is high enough, specific value is published in the
V
BIAS
Thermal Protection
Electrical Characteristics table.
The second, V dropout voltage is the voltage
difference (V
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
BIAS
– V
) when V and V
pins are
BIAS
OUT
IN
BIAS
joined together and V
starts to decrease.
OUT
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from 1 mF
to 10 mF. The device is also stable with multiple capacitors
in parallel, having the total effective capacitance in the
specified range.
In applications where no low input supplies impedance
available (PCB inductance in V and/or V
example), the recommended C = 1 mF and C
or greater. Ceramic capacitors are recommended. For the
Power Dissipation
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation, junction temperature
should be limited to +125°C.
inputs as
IN
BIAS
= 0.1 mF
IN
BIAS
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8
NCV8130
ORDERING INFORMATION
Nominal
Output
Voltage
†
Device
NCV8130BMX080TCG
NCV8130BMX100TCG
NCV8130BMX110TCG
NCV8130BMX120TCG
NCV8130BMX130TCG
NCV8130BMX150TCG
NCV8130BMX180TCG
Marking
Option
Package
Shipping
0.80 V
1.00 V
1.10 V
1.20 V
1.30 V
1.50 V
1.80 V
NL
NF
NG
NA
NC
ND
NE
XDFN6
(Pb−Free)
Non−Active Discharge
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON sales representative.
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9
NCV8130
PACKAGE DIMENSIONS
XDFN6 1.20x1.20, 0.40P
CASE 711AT
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINALS.
D
A
B
4. COPLANARITY APPLIES TO THE PAD AS
WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
E
DIM
A
MIN
0.30
0.00
0.13
1.15
0.84
1.15
0.20
TYP
0.37
0.03
0.18
1.20
0.94
1.20
MAX
0.45
0.05
0.23
1.25
1.04
1.25
0.40
A1
b
D
L
D2
E
TOP VIEW
DETAIL A
0.30
0.40 BSC
E2
e
OPTIONAL
A
CONSTRUCTION
L
0.15
0.00
0.20
0.05
0.25
0.10
0.05
0.05
C
C
L1
A1
RECOMMENDED
MOUNTING FOOTPRINT*
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
6X
0.37
1.08
PACKAGE
OUTLINE
6X
L1
E2
1
3
1.40
0.40
1
6X
L
0.40
PITCH
6X
0.24
DIMENSIONS: MILLIMETERS
6
4
DETAIL A
6X b
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
e
M
0.10
C A B
BOTTOM VIEW
NOTE 3
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◊
NCV8130/D
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