NCV8135AMTW040TBG
更新时间：2024-11-08 23:22:56
品牌：ONSEMI
描述：500 mA, Very Low Dropout Bias Rail CMOS Voltage Regulator
概述
规格参数
数据手册NCV8135AMTW040TBG 概述
500 mA, Very Low Dropout Bias Rail CMOS Voltage Regulator 线性稳压器IC
NCV8135AMTW040TBG 规格参数
| 是否无铅： | 不含铅 | 生命周期： | Active |
| 包装说明： | HVSON, SOLCC6,.08,25 | Reach Compliance Code： | compliant |
| Factory Lead Time： | 28 weeks 6 days | 风险等级： | 5.69 |
| 可调性： | FIXED | 最大回动电压 1： | 0.1 V |
| 标称回动电压 1： | 0.053 V | 最大绝对输入电压： | 6 V |
| 最大输入电压： | 5 V | 最小输入电压： | 0.7 V |
| JESD-30 代码： | S-PDSO-N6 | JESD-609代码： | e3 |
| 长度： | 2 mm | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 输出次数： | 1 |
| 端子数量： | 6 | 工作温度TJ-Max： | 125 °C |
| 工作温度TJ-Min： | -40 °C | 最大输出电流 1： | 0.5 A |
| 最大输出电压 1： | 0.404 V | 最小输出电压 1： | 0.396 V |
| 标称输出电压 1： | 0.4 V | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | HVSON | 封装等效代码： | SOLCC6,.08,25 |
| 封装形状： | SQUARE | 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE |
| 包装方法： | TR | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 调节器类型： | FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR | 筛选级别： | AEC-Q100 |
| 座面最大高度： | 0.8 mm | 表面贴装： | YES |
| 技术： | CMOS | 端子面层： | Tin (Sn) |
| 端子形式： | NO LEAD | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 最大电压容差： | 1% | 宽度： | 2 mm |
| Base Number Matches： | 1 |
NCV8135AMTW040TBG 数据手册
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PDF下载NCV8135
500 mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCV8135 is a 500 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (V ). The device
BIAS
www.onsemi.com
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
T
MARKING
NCV8135 features low I consumption. The NCV8135 is offered in
DIAGRAM
Q
WDFN6 2 mm x 2 mm package, wettable flanks option available for
Enhanced Optical Inspection.
1
XX M
WDFN6
CASE 511BR
Features
XX = Specific Device Code
• Input Voltage Range: 0.4 V to 5.5 V
• Bias Voltage Range: 2.5 V to 5.5 V
• Fixed Output Voltage Versions Available
M
= Date Code
•
1% Accuracy over Temperature, 0.5% V
@ 25°C
OUT
PIN CONNECTIONS
• Ultra−Low Dropout: Typ. 53 mV at 500 mA
• Very Low Bias Input Current of Typ. 35 mA
• Logic Level Enable Input for ON/OFF Control
• Output Active Discharge Option Available
• Stable with a 10 mF Ceramic Capacitor
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
IN
OUT
1
6
Thermal
Pad
GND
BIAS
SNS
EN
2
5
4
3
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
(Top View)
Compliant
Typical Applications
• Automotive, Consumer and Industrial Equipment Point of Load
Regulation
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
• Battery−powered Equipment
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
V
IN
NCV8135
4.7 mF
IN
V
OUT
SNS
OUT
0.4 V up to 500 mA
BIAS
EN
V
BIAS
10 mF
0.1 mF
GND
V
EN
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2019 − Rev. 1
NCV8135/D
NCV8135
CURRENT
LIMIT
OUT
IN
ENABLE
BLOCK
150 W
EN
*Active
DISCHARGE
BIAS
UVLO
VOLTAGE
REFERENCE
+
THERMAL
LIMIT
−
SNS
GND
*Active output discharge function is present only in NCV8135A option devices.
Figure 2. Simplified Schematic Block Diagram
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2
NCV8135
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
VIN
Description
1
2
3
Input Voltage Supply pin
Ground pin
GND
VBIAS
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
4
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
5
6
SNS
VOUT
Pad
Output voltage Sensing Input. Connect to Output voltage node on the PCB.
Regulated Output Voltage pin
Pad
Should be soldered to the ground plane for increased thermal performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage (Note 1)
V
IN
−0.3 to 6
Output Voltage
V
OUT
−0.3 to (V +0.3) ≤ 6
V
IN
Chip Enable, Bias and SNS Input
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
V
V
V
−0.3 to 6
unlimited
125
V
EN, BIAS, SNS
t
s
SC
T
J
°C
°C
V
T
−55 to 150
2000
STG
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
HBM
ESD
200
V
MM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Machine Model tested per AEC−Q100−003
Latchup Current Maximum Rating 100 mA per AEC−Q100−004.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, WDFN6 2 mm x 2 mm
RqJA
97
°C/W
Thermal Resistance, Junction−to−Air (Note 3)
3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted
at the center of a high K (2s2p) 3 in x 3 in multilayer board with 1−ounce internal planes and 1−ounce copper on top and bottom. Top copper
layer has a dedicated 25 sq mm copper area.
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3
NCV8135
ELECTRICAL CHARACTERISTICS −40°C ≤ T ≤ 125°C; V
= 2.7 V or (V
+ 1.6 V), whichever is greater, V = V
OUT(NOM)
+
J
BIAS
OUT
IN
0.3 V, I
= 1 mA, V = 1 V, C = 4.7 mF, C
= 10 mF, C
= 1 mF, unless otherwise noted. Typical values are at T = +25°C.
OUT
EN
IN
OUT
BIAS J
Min/Max values are for −40°C ≤ T ≤ 125°C unless otherwise noted. (Note 4)
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Operating Input Voltage
Range
V
IN
V
+
5.5
V
OUT
DO
V
Operating Bias Voltage
Range
V
(V
+
5.5
V
V
BIAS
OUT
1.50) ≥ 2.5
Undervoltage Lock−out
V
Rising
UVLO
1.6
0.2
BIAS
Hysteresis
Output Voltage Accuracy
V
V
0.5
%
%
OUT
Output Voltage Accuracy −40°C ≤ T ≤ 125°C, V
+ 0.3 V ≤ V
IN
−1.0
+1.0
J
OUT(NOM)
OUT
≤ V
+ 1.0 V, 2.7 V or (V
+
OUT(NOM)
1.6 V), whichever is greater < V
OUT(NOM)
< 5.5 V,
BIAS
1 mA < I
< 500 mA
OUT
V
V
Line Regulation
V
+ 0.3 V ≤ V ≤ 5.0 V
Line
Line
0.01
0.01
%/V
%/V
IN
OUT(NOM)
IN
Reg
Line Regulation
2.7 V or (V
greater < V
+ 1.6 V), whichever is
OUT(NOM)
BIAS
Reg
< 5.5 V
BIAS
Load Regulation
I
I
I
= 1 mA to 500 mA
= 500 mA (Note 5)
Load
0.5
53
mV
mV
V
OUT
OUT
OUT
Reg
V
V
Dropout Voltage
V
V
100
1.5
IN
DO
Dropout Voltage
= 500 mA, V = V
(Notes 5, 6)
1.1
BIAS
IN
BIAS
DO
CL
Output Current Limit
V
= 90% V
I
600
820
0.01
1200
0.5
mA
mA
OUT
OUT(NOM)
SNS Pin Operating
Current
I
SNS
Bias Pin Quiescent
Current
V
BIAS
= 2.7 V, I
= 0 mA
I
35
55
mA
OUT
BIASQ
Bias Pin Disable Current
V
V
≤ 0.4 V
≤ 0.4 V
I
0.2
1
1
mA
mA
EN
BIAS(DIS)
Vinput Pin Disable
Current
I
0.01
EN
VIN(DIS)
EN Pin Threshold Voltage
V
EN Input Voltage “H”
EN Input Voltage “L”
V
0.9
EN(H)
V
0.4
1
EN(L)
EN Pull Down Current
V
EN
= 5.5 V
I
0.3
mA
ms
EN
Turn−On Time
From assertion of V to V
=
t
EN
OUT
V
V
ON
98% V
= 0.4 V
= 1.2 V
150
275
OUT(NOM)
OUT(NOM)
OUT(NOM)
Power Supply Rejection
Ratio
V
V
to V
, f = 1 kHz, I
= 10 mA,
PSRR(V )
IN
73
dB
dB
IN
IN
OUT
OUT
OUT
≥ V
+0.5 V, V
= 0.4 V
OUT(NOM)
V
V
to V
, f = 1 kHz, I
= 10 mA,
= 0.4 V
PSRR(V
)
90
BIAS
OUT
OUT
BIAS
≥ V
+0.5 V, V
IN
IN
OUT
OUT(NOM)
Output Noise Voltage
V
= V
+0.5 V, f = 10 Hz to 100 kHz
V
N
mV
RMS
OUT
V
V
= 0.4 V
= 1.2 V
28.7
40.3
OUT(NOM)
OUT(NOM)
Thermal Shutdown
Threshold
°C
Temperature increasing
Temperature decreasing
160
140
150
Output Discharge
Pull−Down
V
EN
≤ 0.4 V, V
= 0.5 V, NCV8135A options
R
DISCH
W
OUT
only
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when V
falls 3% below V
.
OUT
OUT(NOM)
6. For output voltages below 0.9 V, V
dropout voltage does not apply due to a minimum Bias operating voltage of 2.5 V.
BIAS
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4
NCV8135
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.3 V, V
= 2.7 V, V = 1.0 V, V
= 0.4 V, I
= 500 mA,
J
IN
OUT(NOM)
BIAS
EN
OUT(NOM)
OUT
C
= 1 mF, C
= 0.1 mF, and C = 10 mF (effective capacitance value), unless otherwise noted.
OUT
IN
BIAS
25
100
90
80
70
60
50
40
30
20
I
= 100 mA
OUT
20
+125°C
+125°C
+85°C
+85°C
15
10
+25°C
−40°C
+25°C
−40°C
5
0
10
0
0
100
200
300
400
500
1.5
2.0
2.5
3.0
3.5
4.0 4.5
(V)
5.0 5.5
I , OUTPUT CURRENT (mA)
OUT
V
− V
BIAS OUT
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 4. VIN Dropout Voltage vs. (VBIAS
OUT) and Temperature TJ
−
V
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
I
= 300 mA
I
= 500 mA
OUT
OUT
+125°C
+85°C
+125°C
+85°C
+25°C
+25°C
−40°C
−40°C
1.5
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
1.5
2.0
2.5
3.0
3.5
4.0 4.5
5.0 5.5
V
BIAS
− V
V
− V
(V)
OUT
BIAS
OUT
Figure 5. VIN Dropout Voltage vs. (VBIAS
OUT) and Temperature TJ
−
Figure 6. VIN Dropout Voltage vs. (VBIAS
OUT) and Temperature TJ
−
V
V
V
OUT
V
OUT
t
R
= t = 1 ms
F
t = t = 1 ms
R F
I
I
OUT
OUT
50 ms/div
50 ms/div
Figure 7. Load Transient Response,
Figure 8. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 10 mF
IOUT = 50 mA to 500 mA, COUT = 22 mF
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5
NCV8135
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.3 V, V
= 2.7 V, V = 1.0 V, V
= 0.4 V, I
= 500 mA,
J
IN
OUT(NOM)
BIAS
EN
OUT(NOM)
OUT
C
= 1 mF, C
= 0.1 mF, and C
= 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
V
OUT
V
OUT
t
R
= t = 1 ms
F
t = t = 1 ms
R F
I
I
OUT
OUT
500 ms/div
500 ms/div
Figure 9. Load Transient Response,
OUT = 1 mA to 500 mA, COUT = 10 mF
Figure 10. Load Transient Response,
OUT = 1 mA to 500 mA, COUT = 22 mF
I
I
V
OUT
V
OUT
t
R
= t = 1 ms
F
t = t = 1 ms
R F
I
I
OUT
OUT
500 ms/div
500 ms/div
Figure 11. Load Transient Response,
OUT = 1 mA to 20 mA, COUT = 10 mF
Figure 12. Load Transient Response,
OUT = 1 mA to 20 mA, COUT = 22 mF
I
I
V
V
ENABLE
ENABLE
V
OUT
V
OUT
I
OUT
100 ms/div
100 ms/div
Figure 13. Enable Transient Response,
OUT = 0 mA, COUT = 10 mF
Figure 14. Enable Transient Response, Output
I
Resistive Load 500 mA, COUT = 22 mF
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6
NCV8135
TYPICAL CHARACTERISTICS
At T = +25°C, V = V
+ 0.3 V, V
= 2.7 V, V = 1.0 V, V
= 0.4 V, I
= 500 mA,
J
IN
OUT(NOM)
BIAS
EN
OUT(NOM)
OUT
C
= 1 mF, C
= 0.1 mF, and C
= 10 mF (effective capacitance value), unless otherwise noted.
IN
BIAS
OUT
V
OUT
V
OUT
t
R
= t = 5 ms
F
t
R
= t = 5 ms
F
V
IN
V
IN
50 ms/div
50 ms/div
Figure 15. VIN Line Transient Response,
IN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
OUT = 10 mF
Figure 16. VIN Line Transient Response,
IN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
OUT = 22 mF
V
V
C
C
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10 mA, C
= 22 mF
V
= 0.9 V, V
= 2.7 V, C
= MLCC 1206
OUT
IN
BIAS
OUT
10 mA, C
= 10 mF
OUT
10 mA, C
= 10 mF
OUT
10 mA, C
= 22 mF
OUT
100 mA, C
= 10 mF
OUT
100 mA, C
100
= 10 mF
OUT
100 mA, C
= 22 mF
OUT
100 mA, C
= 22 mF
OUT
V
= 0.9 V, V
100
= 2.7 V, C
= MLCC 1206
IN
BIAS
OUT
10
10
10
10
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. VIN Power Supply Rejection Ratio
vs. Frequency
Figure 18. VBIAS Power Supply Rejection Ratio
vs. Frequency
10000
1000
100
10
500 mA 22 mF
100 mA 22 mF
10 mA 22 mF
1 mA 22 mF
RMS Output Noise Voltage (mV)
I
OUT
C
10 Hz − 100 kHz 100 Hz − 100 kHz
OUT
1 mA 10 mF
27.54
27.28
35.49
44.87
54.04
28.67
28.19
36.23
45.44
54.54
1 mA
1 mA
10 mF
22 mF
22 mF
22 mF
22 mF
10 mA
100 mA
500 mA
V
IN
= 0.9 V, V
100
= 2.7 V, C
= MLCC 1206
OUT
BIAS
1
10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Output Voltage Noise Spectral
Density
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7
NCV8135
APPLICATIONS INFORMATION
The NCV8135 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from V voltage. All the low current internal
the NCV8135 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
IN
control circuitry is powered from the V
voltage.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
BIAS
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability. Vin
to Vout operating voltage difference can be very low compared
with standard PMOS regulators in very low Vin applications.
When enabled from Enable (EN) input, the NCV8135
offers smooth monotonic start-up. The controlled voltage
rising limits the inrush current.
Enable Operation
The Enable (EN) input is equipped with internal
hysteresis.
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. To get the full functionality of
Dropout Voltage
Because of two power supply inputs V and V
and
soft−start, it is recommended to turn on the V and V
IN
BIAS
IN BIAS
one V
regulator output, there are two Dropout voltages
supply voltages first and activate the Enable pin no sooner
than when V and V are on their nominal levels. If the
enable function is not to be used then the pin should be
OUT
specified.
The first, the V Dropout voltage is the voltage
IN
BIAS
IN
difference (V – V
) when V
OUT
starts to decrease by
connected to V or V
.
IN
OUT
IN
BIAS
percent specified in the Electrical Characteristics table.
is high enough; specific value is published in the
Current Limitation
V
BIAS
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Electrical Characteristics table.
The second, V dropout voltage is the voltage
BIAS
difference (V
– V
) when V and V
pins are
BIAS
OUT
IN
BIAS
joined together and V
starts to decrease.
OUT
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated, the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Activation of the thermal protection circuit indicates
excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to
+125°C maximum.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
10 mF to 22 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in V and/or V
inputs as
IN
BIAS
example), the recommended C = 1 mF and C
= 0.1 mF
IN
BIAS
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
ORDERING INFORMATION
Device
Marking
KA
Voltage
0.4 V
0.4 V
1.2 V
0.4 V
0.4 V
1.2 V
0.75 V
Option
Package
Shipping†
NCV8135AMT040TBG
NCV8135BMT040TBG
NCV8135AMT120TBG
NCV8135AMTW040TBG
NCV8135BMTW040TBG
NCV8135AMTW120TBG
Output Active Discharge
Non−Active Discharge
Output Active Discharge
Output Active Discharge
Non−Active Discharge
Output Active Discharge
Output Active Discharge
WDFN6
(Non−Wettable Flank)
(Pb−Free)
KC
KE
K2
3000 / Tape & Reel
K3
WDFN6
(Wettable Flank)
(Pb−Free)
K4
NCV8135AMTW075TBG
(In Development)
KL
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
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8
NCV8135
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
A3
EXPOSED Cu
MOLD CMPD
D
A
B
A1
ALTERNATE B−1
ALTERNATE B−2
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
DETAIL B
PIN ONE
ALTERNATE
REFERENCE
E
CONSTRUCTIONS
0.10
C
L
L
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
0.10
C
L1
TOP VIEW
A1
A3
b
ALTERNATE A−1
ALTERNATE A−2
0.20 REF
0.25
1.50
0.35
DETAIL A
A3
DETAIL B
D
2.00 BSC
0.05
C
C
ALTERNATE
D2
E
1.70
CONSTRUCTIONS
2.00 BSC
A
E2
e
0.90
1.10
0.65 BSC
L
0.20
---
0.40
0.15
0.05
6X
A1
L1
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
RECOMMENDED
MOUNTING FOOTPRINT
DETAIL A
L
1
3
6X
0.45
1.72
E2
6
4
1.12
2.30
6X b
M
M
0.10
0.05
C
C
A
B
e
NOTE 3
BOTTOM VIEW
PACKAGE
OUTLINE
1
0.65
PITCH
6X
0.40
DIMENSIONS: MILLIMETERS
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NCV8135/D
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