NCV8501PDW80R2_技术文档

NCV8501 Series

Micropower 150 mA LDO

Linear Regulators

with ENABLE, DELAY,

RESET, and Monitor FLAG

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The NCV8501 is a family of precision micropower voltage

regulators. Their output current capability is 150 mA. The family has

output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V.

The output voltage is accurate within ±2.0% with a maximum

dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature

drawing only 90 mA with a 100 mA load. This part is ideal for any and

all battery operated microprocessor equipment.

Microprocessor control logic includes an active RESET (with

DELAY), and a FLAG monitor which can be used to provide an early

warning signal to the microprocessor of a potential impending RESET

signal. The use of the FLAG monitor allows the microprocessor to

finish any signal processing before the RESET shuts the

microprocessor down.

The active RESET circuit operates correctly at an output voltage as

low as 1.0 V. The RESET function is activated during the power up

sequence or during normal operation if the output voltage drops

outside the regulation limits.

The regulator is protected against reverse battery, short circuit, and

thermal overload conditions. The device can withstand load dump

transients making it suitable for use in automotive environments. The

device has also been optimized for EMC conditions.

SO−8

D SUFFIX

CASE 751

8

1

SOIC 16 LEAD

WIDE BODY

EXPOSED PAD

PDW SUFFIX

CASE 751R

16

1

MARKING DIAGRAMS

SO−8

SOW−16

E PAD

8

1

16

8501x

ALYW

8501x

AWLYYWW

1

Features

x

= Voltage Ratings as Indicated Below:

• Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V

• ±2.0% Output

• Low 90 mA Quiescent Current

• Fixed or Adjustable Output Voltage

• Active RESET

• ENABLE

• 150 mA Output Current Capability

• Fault Protection

A = Adjustable

2 = 2.5 V

3 = 3.3 V

5 = 5.0 V

8 = 8.0 V

1 = 10 V

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

♦ +60 V Peak Transient Voltage

♦ −15 V Reverse Voltage

♦ Short Circuit

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

♦ Thermal Overload

• Early Warning through FLAG/MON Leads

• NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

• Pb−Free Packages are Available

Semiconductor Components Industries, LLC, 2004

1

Publication Order Number:

September, 2004 − Rev. 19

NCV8501/D

NCV8501 Series

PIN CONNECTIONS, ADJUSTABLE OUTPUT

SO−8

SOW−16 E PAD

1

8

1

16

V

IN

V

OUT

V

ADJ

FLAG

V

NC

GND

NC

MON

ENABLE

NC

V

OUT

NC

ADJ

FLAG

GND

NC

V

IN

NC

MON

ENABLE

PIN CONNECTIONS, FIXED OUTPUT

SO−8

SOW−16 E PAD

1

8

1

16

V

OUT

FLAG

RESET

NC

GND

NC

IN

V

MON

ENABLE

DELAY

FLAG

RESET

GND

OUT

NC

V

MON

DELAY

ENABLE

IN

V

BAT

V

IN

V

OUT

V

DD

10 mF

NCV8501

R

RST

FLG

10 k

DELAY

MON

C

DELAY

V

ADJ

(Adjustable

Output Only)

ENABLE

FLAG

RESET

I/O

GND

Figure 1. Application Diagram

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2

NCV8501 Series

MAXIMUM RATINGS*

Rating

Value

−15 to 45

60

Unit

V

IN

(dc)

Peak Transient Voltage (46 V Load Dump @ V = 14 V)

V

IN

Operating Voltage

45

V

OUT

(dc)

16

V

Voltage Range (RESET, FLAG)

Input Voltage Range (MON)

−0.3 to 10

−0.3 to 10**

2.0

V

Input Voltage Range (ENABLE)

ESD Susceptibility (Human Body Model)

V

kV

°C

Junction Temperature, T

−40 to +150

−55 to 150

J

Storage Temperature, T

S

Package Thermal Resistance, SO−8:

Junction−to−Case, R

Junction−to−Ambient, R

45

165

°C/W

q

JC

q

JA

Package Thermal Resistance, SOW−16 E PAD:

Lead Temperature Soldering:

Junction−to−Case, R

Junction−to−Ambient, R

15

56

35

°C/W

q

JC

q

JA

Junction−to−Pin, R

(Note 1)

q

JP

Reflow: (SMD styles only) (Note 2)

240 peak

260 Peak (Pb−Free)

(Note 3)

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

*During the voltage range which exceeds the maximum tested voltage of V , operation is assured, but not specified. Wider limits may apply.

IN

Thermal dissipation must be observed closely.

**Reference Figure 14 for switched−battery ENABLE application.

1. Measured to pin 16.

2. 150 second maximum above 183°C, Pb−Free − 150 second maximum above 217°C.

3. −5°C / +0°C allowable conditions, applies to both Pb and Pb−Free devices.

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3

NCV8501 Series

ELECTRICAL CHARACTERISTICS (I

= 1.0 mA, ENABLE = 5.0 V, −40°C ≤ T ≤ 125°C; V dependent on voltage option

OUT

J

IN

(Note 4); unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Output Stage

Output Voltage for 2.5 V Option

6.5 V < V < 16 V, 100 mA ≤ I

≤ 150 mA

2.450

2.425

2.5

2.550

2.575

V

IN

OUT

5.5 V < V < 26 V, 100 mA ≤ I

IN

Output Voltage for 3.3 V Option

Output Voltage for 5.0 V Option

7.3 V < V < 16 V, 100 mA ≤ I

≤ 150 mA

3.234

3.201

3.3

3.366

3.399

V

IN

OUT

5.5 V < V < 26 V, 100 mA ≤ I

IN

9.0 V < V < 16 V, 100 mA ≤ I

≤ 150 mA

4.90

4.85

5.0

5.10

5.15

V

IN

OUT

6.0 V < V < 26 V, 100 mA ≤ I

IN

Output Voltage for 8.0 V Option

Output Voltage for 10 V Option

9.0 V < V < 26 V, 100 mA ≤ I

≤ 150 mA

7.76

9.7

8.0

10

8.24

10.3

V

IN

OUT

11 V < V < 26 V, 100 mA ≤ I

IN

OUT

Output Voltage for Adjustable Option

V

OUT

= V

(Unity Gain)

ADJ

6.5 V < V < 16 V, 100 mA < I

< 150 mA

1.254

1.242

1.280

1.306

1.318

V

IN

OUT

5.5 V < V < 26 V, 100 mA < I

IN

OUT

Dropout Voltage (V − V

(5.0 V, 8.0 V, 10 V, and

)

I

= 150 mA

= 1.0 mA

−

400

100

600

150

mV

IN

OUT

Adj. > 5.0 V Options Only)

Load Regulation

V

= 14 V, 5.0 mA ≤ I

≤ 150 mA

−30

−

5.0

15

30

60

mV

IN

OUT

Line Regulation

[V

(Typ) + 1.0] < V < 26 V, I = 1.0 mA

OUT OUT

IN

Quiescent Current, Low Load

2.5 V Option

3.3 V Option

5.0 V Option

8.0 V Option

I

= 100 mA, V = 12 V, MON = V

OUT IN OUT

−

90

125

150

75

mA

90

100

50

10 V Option

Adjustable Option

Quiescent Current, Medium Load

All Options

I

= 75 mA, V = 14 V, MON = V

OUT

−

4.0

12

6.0

19

30

mA

OUT

IN

Quiescent Current, High Load

All Options

I

= 150 mA, V = 14 V, MON = V

OUT IN OUT

Quiescent Current, (I )

ENABLE = 0 V, V = 12 V

IN

Q

Sleep Mode

Current Limit

−

151

40

300

190

180

−

mA

°C

Short Circuit Output Current

Thermal Shutdown

V

= 0 V

OUT

(Guaranteed by Design)

150

Reset Function (RESET)

RESET Threshold for 2.5 V Option

5.5 V ≤ V ≤ 26 V (Note 5)

IN

HIGH (V

LOW (V

)

V

OUT

V

OUT

Increasing

Decreasing

2.28

2.25

2.350

2.300

0.98 ×

V

RH

)

V

OUT

RL

0.97 ×

V

OUT

RESET Threshold for 3.3 V Option

5.5 V ≤ V ≤ 26 V (Note 5)

IN

HIGH (V

LOW (V

)

V

OUT

V

OUT

Increasing

Decreasing

3.00

2.97

3.102

3.036

0.98 ×

V

RH

)

V

OUT

RL

0.97 ×

V

OUT

RESET Threshold for 5.0 V Option

HIGH (V

LOW (V

)

V

OUT

V

OUT

Increasing

Decreasing

4.55

4.50

4.70

4.60

0.98 ×

V

RH

)

V

OUT

RL

0.97 ×

V

OUT

4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.

5. For V ≤ 5.5 V, a RESET = Low may occur with the output in regulation.

IN

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NCV8501 Series

ELECTRICAL CHARACTERISTICS (I

= 1.0 mA, ENABLE = 5.0 V, −40°C ≤ T ≤ 125°C; V dependent on voltage option

OUT

J

IN

(Note 4); unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Reset Function (RESET)

RESET Threshold for 8.0 V Option

HIGH (V

LOW (V

)

V

Increasing

Decreasing

6.86

6.80

7.52

7.36

0.98 ×

V

RH

OUT

)

V

OUT

RL

0.97 ×

V

OUT

RESET Threshold for 10 V Option

HIGH (V

LOW (V

)

V

OUT

V

OUT

Increasing

Decreasing

8.60

8.50

9.40

9.20

0.98 ×

V

RH

)

V

OUT

RL

0.97 ×

V

OUT

Output Voltage

Low (V

)

1.0 V ≤ V

≤ V , R

= 10 k

−

0.1

1.8

−

0.4

2.2

0.1

3.5

−

V

RLO

OUT

RL

RESET

DELAY Switching Threshold (V

DELAY Low Voltage

)

DT

−

1.4

−

V

OUT

< RESET Threshold Low(min)

V

DELAY Charge Current

DELAY Discharge Current

DELAY = 1.0 V, V

> V

1.5

5.0

2.5

−

mA

OUT

RH

DELAY = 1.0 V, V

= 1.5 V

FLAG/Monitor

Monitor Threshold

Hysteresis

Increasing and Decreasing

1.10

20

1.20

50

1.31

100

0.5

V

mV

mA

V

−

Input Current

MON = 2.0 V

−0.5

−

0.1

Output Saturation Voltage

MON = 0 V, I

= 1.0 mA

0.4

FLAG

Voltage Adjust (Adjustable Output only)

Input Current

ENABLE

V

ADJ

= 1.28 V

−0.5

−

0.5

mA

Input Threshold

Low

High

−

0.5

−

V

3.0

Input Current

ENABLE = 5.0 V

−

1.0

5.0

mA

4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.

5. For V ≤ 5.5 V, a RESET = Low may occur with the output in regulation.

IN

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5

NCV8501 Series

PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT

Package Pin Number

SOW−16

E PAD

SO−8

Pin Symbol

Function

1

2

3

4

7

8

9

V

Input Voltage.

IN

MON

ENABLE

NC

Monitor. Input for early warning comparator. If not needed connect to V

ENABLE control for the IC. A high powers the device up.

No connection.

OUT.

3−6, 10−12,

14, 15

5

6

7

8

13

16

1

GND

Ground. All GND leads must be connected to Ground

Open collector output from early warning comparator.

.

FLAG

V

ADJ

Voltage Adjust. A resistor divider from V

to this lead sets the output voltage.

OUT

2

V

OUT

±2.0%, 150 mA output.

PACKAGE PIN DESCRIPTION, FIXED OUTPUT

Package Pin Number

SOW−16

E PAD

SO−8

Pin Symbol

Function

1

2

3

4

5

6

7

8

−

7

8

V

Input Voltage.

IN

MON

ENABLE

DELAY

GND

Monitor. Input for early warning comparator. If not needed connect to V

ENABLE control for the IC. A high powers the device up.

Timing capacitor for RESET function.

OUT.

9

10

13

16

1

Ground. All GND leads must be connected to Ground

.

RESET

FLAG

Active reset (accurate to V

≥ 1.0 V)

OUT

Open collector output from early warning comparator.

±2.0%, 150 mA output.

2

V

OUT

3−6, 11, 12,

14, 15

NC

No connection.

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NCV8501 Series

TYPICAL PERFORMANCE CHARACTERISTICS

5.01

5.00

4.99

4.98

3.35

V

= 3.3 V

= 14 V

= 5.0 mA

OUT

V

= 5.0 V

= 14 V

= 5.0 mA

OUT

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

IN

I

OUT

I

OUT

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 2. Output Voltage vs. Temperature

Figure 3. Output Voltage vs. Temperature

1.2

14

12

10

8

V

= 12 V

V

IN

= 12 V

IN

1.0

0.8

0.6

0.4

0.2

0

+125°C

+25°C

−40°C

6

−40°C

4

2

0

5

10

I

15

(mA)

20

25

0

15 30 45 60 75 90 105 120 135 140

(mA)

I

OUT

Figure 4. Quiescent Current vs. Output Current

Figure 5. Quiescent Current vs. Output Current

7

6

5

4

3

2

1

0

120

T = 25°C

100

80

60

49

20

0

I

= 100 mA

OUT

I

= 100 mA

OUT

I

= 50 mA

= 10 mA

OUT

6

8

10 12 14 16 18 20 22 24 26

(V)

6

8

10 12 14 16 18 20 22 24 26

(V)

V

IN

Figure 6. Quiescent Current vs. Input Voltage

Figure 7. Quiescent Current vs. Input Voltage

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NCV8501 Series

TYPICAL PERFORMANCE CHARACTERISTICS

450

400

350

300

250

200

150

100

50

16

14

12

10

V

= 12 V

IN

+125°C

+25°C

−40°C

8

6

4

2

0

V

OUT

= 5.0 V, 8.0 V, or 10 V

0

25

50

75

100

125

150

−40 −25 −10

5

20 35 50 65 80 95 110 125

I

(mA)

Temperature (°C)

OUT

Figure 8. Dropout Voltage vs. Output Current

Figure 9. Sleep Mode I_Qvs. Temperature

1000

100

10

1000

C

= 10 mF

Unstable Region

Vout

100

10

C

= 0.1 mF

Vout

10 V

8 V

5 V

2.5 V

3.3 V

1.0

Stable Region

0.1

C

= 10 mF

VOUT

0.01

0

10

20 30 40 50 60 70 80 90 100

OUTPUT CURRENT (mA)

0

10 20 30 40 50 60 70 80 90 100 110

OUTPUT CURRENT (mA)

Figure 10. Output Stability with Output

Voltage Change

Figure 11. Output Stability with Output

Capacitor Change

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NCV8501 Series

V

OUT

V

IN

Current Source

(Circuit Bias)

ENABLE

I

BIAS

Current Limit

Sense

+

−

I

BIAS

+

V

BG

−

Error Amplifier

V

BG

RESET

+

Fixed Voltage only

1.8 V

−

Thermal

Protection

3.0 mA

V

ADJ

Bandgap

Reference

20 k

Adjustable

Version only

Delay

MON

I

V

BG

BIAS

GND

V

BG

I

BIAS

FLAG

+

−

Figure 12. Block Diagram

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9

NCV8501 Series

CIRCUIT DESCRIPTION

REGULATOR CONTROL FUNCTIONS

The NCV8501 contains the microprocessor compatible

control function RESET (Figure 13).

The DELAY lead provides source current (typically 2.5 mA)

to the external DELAY capacitor during the following

proceedings:

1. During Power Up (once the regulation threshold

has been verified).

2. After a reset event has occurred and the device is

back in regulation. The DELAY capacitor is

discharged when the regulation (RESET threshold)

has been violated. This is a latched incident. The

capacitor will fully discharge and wait for the

device to regulate before going through the delay

time event again.

V

IN

RESET

V

OUT

Threshold

DELAY

RESET

DELAY

Threshold

(V

)

DT

FLAG/Monitor Function

T

d

An on−chip comparator is provided to perform an early

warning to the microprocessor of a possible reset signal. The

reset signal typically turns the microprocessor off

instantaneously. This can cause unpredictable results with

the microprocessor. The signal received from the FLAG pin

will allow the microprocessor time to complete its present

task before shutting down. This function is performed by a

comparator referenced to the bandgap reference. The actual

trip point can be programmed externally using a resistor

divider to the input monitor (MON) (Figure 15). The typical

threshold is 1.20 V on the MON pin.

Figure 13. Reset and Delay Circuit Wave Forms

RESET Function

A RESET signal (low voltage) is generated as the IC

powers up until V is within 6.0% of the regulated output

OUT

voltage, or when V

drops out of regulation,and is lower

OUT

than 8.0% below the regulated output voltage. Hysteresis is

included in the function to minimize oscillations.

The RESET output is an open collector NPN transistor,

controlled by a low voltage detection circuit. The circuit is

functionally independent of the rest of the IC thereby

guaranteeing that the RESET signal is valid for V

as 1.0 V.

as low

OUT

V

BAT

V

OUT

V

CC

V

IN

mP

ENABLE Function

NCV8501

C

OUT

The part stays in a low I sleep mode when the ENABLE

I/O

Q

MON

FLAG

pin is held low. The part has an internal pull down if the pin

is left floating. This is intended for failure modes only. An

external connection (active pulldown, resistor, or switch) for

normal operation is recommended.

R

RESET

ADJ

RESET

GND

DELAY

The integrity of the ENABLE pin allows it to be tied

directly to the battery line through an external resistor. It will

withstand load dump potentials in this configuration.

Figure 15. FLAG/Monitor Function

Voltage Adjust

Figure 16 shows the device setup for a user configurable

output voltage. The feedback to the V pin is taken from

V

BAT

V

OUT

V

IN

ADJ

a voltage divider referenced to the output voltage. The loop

is balanced around the Unity Gain threshold (1.28 V

typical).

NCV8501

10 k

ENABLE

GND

≈5.0 V

V

OUT

C

OUT

15 k

NCV8501

Figure 14. ENABLE Function

V

ADJ

1.28 V

5.1 k

DELAY Function

The reset delay circuit provides a programmable (by

external capacitor) delay on the RESET output lead.

Figure 16. Adjustable Output Voltage

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10

NCV8501 Series

APPLICATION NOTES

V

IN

V

OUT

C

0.1 mF

*

IN

C

10 mF

**

NCV8501

OUT

R

NCV8501

RST

MJD31C

V

IN

V

OUT

RESET

5.0 V

>1 Amp

V

ADJ

R1

294 k

C2

0.1 mF

V

BAT

C1

47 mF

*C required if regulator is located far from the power supply filter

IN

R2

100 k

**C

required for stability. Capacitor must operate at minimum

temperature expected

OUT

Figure 19. Test and Application Circuit Showing

Output Compensation

Figure 17. Additional Output Current

Adding Capability

SETTING THE DELAY TIME

The delay time is controlled by the Reset Delay Low

Voltage, Delay Switching Threshold, and the Delay Charge

Current. The delay follows the equation:

Figure 17 shows how the adjustable version of parts can

be used with an external pass transistor for additional current

capability. The setup as shown will provide greater than 1

Amp of output current.

[

C

]

(V * Reset Delay Low Voltage)

DELAY dt

t

+

DELAY

Delay Charge Current

FLAG MONITOR

Figure 18 shows the FLAG Monitor waveforms as a result

of the circuit depicted in Figure 15. As the output voltage

), the Monitor threshold is crossed. This causes

the voltage on the FLAG output to go low sending a warning

signal to the microprocessor that a RESET signal may occur

Example:

Using C

Assume reset Delay Low Voltage = 0.

Use the typical value for V = 1.8 V.

= 33 nF.

DELAY

falls (V

OUT

dt

Use the typical value for Delay Charge Current = 2.5 mA.

[

]

33 nF(1.8 * 0)

in a short period of time. T

is the time the

WARNING

t

+

+ 23.8 ms

DELAY

2.5 mA

microprocessor has to complete the function it is currently

working on and get ready for the RESET shutdown signal.

STABILITY CONSIDERATIONS

V

OUT

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: start−up

delay, load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints. A tantalum or

aluminum electrolytic capacitor is best, since a film or

ceramic capacitor with almost zero ESR can cause

instability. The aluminum electrolytic capacitor is the least

expensive solution, but, if the circuit operates at low

temperatures (−25°C to −40°C), both the value and ESR of

the capacitor will vary considerably. The capacitor

manufacturers data sheet usually provides this information.

MON

FLAG Monitor

Ref. Voltage

RESET

FLAG

The value for the output capacitor C

shown in Figure 19

OUT

should work for most applications, however it is not

necessarily the optimized solution.

T

WARNING

Figure 18. FLAG Monitor Circuit Waveform

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11

NCV8501 Series

100

CALCULATING POWER DISSIPATION IN A

SINGLE OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output

regulator (Figure 20) is:

90

80

70

60

P

+ [V

* V

]I

OUT(min) OUT(max)

D(max)

IN(max)

(eq. 1)

) V

I

IN(max) Q

where:

V

I

is the maximum input voltage,

is the minimum output voltage,

is the maximum output current for the

IN(max)

OUT(min)

OUT(max)

50

40

application, and

0

200

400

Copper Area (mm )

600

800

I

is the quiescent current the regulator consumes at

Q

2

.

OUT(max)

Once the value of P

is known, the maximum

can be calculated:

D(max)

Figure 21. 16 Lead SOW (Exposed Pad), qJA as a

Function of the Pad Copper Area (2 oz. Cu

Thickness), Board Material = 0.0625, G−10/R−4

permissible value of R

qJA

T

150°C *

A

(eq. 2)

R

+

QJA

P

D

The value of R

can then be compared with those in the

qJA

package section of the data sheet. Those packages with

’s less than the calculated value in Equation 2 will keep

the die temperature below 150°C.

In some cases, none of the packages will be sufficient to

dissipate the heat generated by the IC, and an external

heatsink will be required.

HEATSINKS

R

qJA

A heatsink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

I

IN

OUT

determine the value of R

:

qJA

SMART

REGULATOR

V

IN

V

OUT

(eq. 3)

R

+ R

) R

qCS qSA

qJA

qJC

where:

Control

R

qJC

R

qCS

R

qSA

= the junction−to−case thermal resistance,

= the case−to−heatsink thermal resistance, and

= the heatsink−to−ambient thermal resistance.

}

Features

I

Q

R

qJC

appears in the package section of the data sheet. Like

R

, it too is a function of package type. R

and R

are

qJA

qCS

qSA

Figure 20. Single Output Regulator with Key

Performance Parameters Labeled

functions of the package type, heatsink and the interface

between them. These values appear in heatsink data sheets

of heatsink manufacturers.

http://onsemi.com

12

NCV8501 Series

ORDERING INFORMATION

Device

Output Voltage

Package

Shipping†

NCV8501DADJ

Adjustable

SO−8

98 Units/Rail

NCV8501DADJG

SO−8

(Pb−Free)

Adjustable

98 Units/Rail

NCV8501DADJR2

NCV8501DADJR2G

SO−8

2500 Tape & Reel

SO−8

(Pb−Free)

NCV8501PDWADJ

NCV8501PDWADJR2

NCV8501D25

47 Units/Rail

1000 Tape & Reel

98 Units/Rail

Adjustable

SOW−16 Exposed Pad

SO−8

2.5 V

NCV8501D25G

SO−8

(Pb−Free)

98 Units/Rail

NCV8501D25R2

SO−8

2500 Tape & Reel

NCV8501D25R2G

SO−8

(Pb−Free)

NCV8501PDW25

NCV8501PDW25R2

NCV8501D33

47 Units/Rail

1000 Tape & Reel

98 Units/Rail

2.5 V

SOW−16 Exposed Pad

SO−8

3.3 V

NCV8501D33G

SO−8

(Pb−Free)

98 Units/Rail

NCV8501D33R2

SO−8

2500 Tape & Reel

NCV8501D33R2G

SO−8

(Pb−Free)

NCV8501PDW33

NCV8501PDW33R2

NCV8501D50

47 Units/Rail

1000 Tape & Reel

98 Units/Rail

3.3 V

SOW−16 Exposed Pad

SO−8

5.0 V

NCV8501D50G

SO−8

(Pb−Free)

98 Units/Rail

NCV8501D50R2

SO−8

2500 Tape & Reel

NCV8501D50R2G

SO−8

(Pb−Free)

NCV8501PDW50

NCV8501PDW50R2

NCV8501D80

47 Units/Rail

1000 Tape & Reel

98 Units/Rail

5.0 V

SOW−16 Exposed Pad

SO−8

8.0 V

NCV8501D80G

SO−8

(Pb−Free)

98 Units/Rail

NCV8501D80R2

SO−8

2500 Tape & Reel

NCV8501D80R2G

SO−8

(Pb−Free)

NCV8501PDW80

NCV8501PDW80R2

NCV8501D100

47 Units/Rail

1000 Tape & Reel

98 Units/Rail

8.0 V

SOW−16 Exposed Pad

SO−8

10 V

NCV8501D100G

SO−8

(Pb−free)

98 Units/Rail

NCV8501D100R2

NCV8501D100R2G

SO−8

2500 Tape & Reel

SO−8

(Pb−Free)

NCV8501PDW100

47 Units/Rail

10 V

SOW−16 Exposed Pad

NCV8501PDW100R2

1000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

http://onsemi.com

13

NCV8501 Series

PACKAGE DIMENSIONS

SO−8 NB

D SUFFIX

CASE 751−07

ISSUE AB

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

−Z−

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

4.0

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

14

NCV8501 Series

PACKAGE DIMENSIONS

SOIC 16 LEAD WIDE BODY

EXPOSED PAD

PDW SUFFIX

CASE 751R−02

ISSUE A

−U−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

A

M

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

16

1

9

P

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.

B

M

W

0.25 (0.010)

R x 45

_

8

−W−

MILLIMETERS

INCHES

MIN

G

14 PL

DIM MIN

MAX

10.45

7.60

2.65

0.49

0.90

MAX

0.411

0.299

0.104

0.019

0.035

PIN 1 I.D.

DETAIL E

A

B

C

D

F

10.15

7.40

2.35

0.35

0.50

0.400

0.292

0.093

0.014

0.020

TOP SIDE

G

H

J

1.27 BSC

0.050 BSC

3.76

0.25

0.10

4.58

0

3.86

0.32

0.25

4.78

7

0.148

0.010

0.004

0.180

0

0.152

0.012

0.009

0.188

7

K

L

C

M

P

R

_

F

−T−

10.05

0.25

10.55

0.75

0.395

0.010

0.415

0.029

0.10 (0.004)

T

SEATING

PLANE

K

D16 PL

M

S

0.25 (0.010)

T

U

W

J

DETAIL E

H

1

8

9

EXPOSED PAD

L

16

BACK SIDE

http://onsemi.com

15

NCV8501 Series

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

NCV8501/D

http://onsemi.com

16


型号：	NCV8501PDW80R2
厂家：	ONSEMI
描述：	Micropower 150 mA LDO Linear Regulators with ENABLE, DELAY, RESET, and Monitor FLAG 微150毫安LDO线性稳压器与启用，延迟，复位和监视器标志稳压器监视器
文件：	总16页 (文件大小：122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV8501PDW80R2 [ONSEMI]

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