NCV8711BMTW330TBG [ONSEMI]
LDO Regulator, 100 mA, 18V, 1 A IQ, with PG;
| 型号： | NCV8711BMTW330TBG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator, 100 mA, 18V, 1 A IQ, with PG |
| 文件： | 总12页 (文件大小：1044K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LDO Regulator, 100 mA,
18ꢀV, 1 mA IQ, with PG
NCV8711
The NCV8711 device is based on unique combination of features −
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCV8711 is CMOS LDO regulator
designed for up to 18 V input voltage and 100 mA output current.
Quiescent current of only 1 mA makes this device ideal solution for
battery− powered, always−on systems. Several fixed output voltage
versions are available as well as the adjustable version.
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5
The device (version B) implements power good circuit (PG) which
indicates that output voltage is in regulation. This signal could be used
for power sequencing or as a microcontroller reset.
1
TSOP−5
CASE 483
WDFNW6 (2x2)
CASE 511DW
Internal short circuit and over temperature protections saves the
device against overload conditions.
MARKING DIAGRAMS
5
Features
XX MG
• Operating Input Voltage Range: 2.7 V to 18 V
• Output Voltage: 1.2 V to 17 V
G
1
• Capable of Sourcing 140 mA Peak Output Current
• Very Low Quiescent Current: 1 mA typ.
• Low Dropout: 215 mV typ. at 100 mA
• Output Voltage Accuracy 1%
XX= Specific Device
Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
• Power Good Output (Version B)
1
• Stable with Small 1 mF Ceramic Capacitors
• Built−in Soft Start Circuit to Suppress Inrush Current
• Over−Current and Thermal Shutdown Protections
• Available in Small TSOP−5 and WDFNW6 (2x2) Packages
• These Devices are Pb−Free and are RoHS Compliant
XX M
XX = Specific Device Code
M
= Date Code
PIN ASSIGNMENTS
Typical Applications
• Body Control Modules
• LED Lighting
TSOP−5
IN
GND
EN
5
1
2
OUT
• On Board Charger
• General Purpose Automotive
4
NC/ADJ/PG
3
CASE 483
WDFNW6 (2x2)
6
5
4
IN
OUT
1
2
3
EP
NC/ADJ
GND
NC/PG
EN
CASE511DW
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
June, 2020 − Rev. 1
NCV8711/D
NCV8711
TYPICAL APPLICATION SCHEMATICS
VOUT=5V
VIN=6−18V
VOUT=5.0V
VIN=6−18V
IN
OUT
NCV8711AADJ
TSOP−5 / WDFN−6
EN
IN
OUT
NCV8711A 5.0V
TSOP−5 / WDFN−6
EN NC
COUT
1mF
CIN
1mF
COUT
1mF
CIN
1mF
R1
CFF
1nF
2M4
ON
ON
OFF
1.2V
ADJ
GND
GND
OFF
R2
750k
Figure 1. Fixed Output Voltage Application (No PG)
Figure 2. Adjustable Output Voltage Application (No PG)
VIN=6−18V
VOUT=5V
VIN=6−18V
VOUT=5.0V
IN
IN
OUT
OUT
CIN
1mF
COUT
1mF
COUT
1mF
CIN
1mF
R1
CFF
1nF
NCV8711B ADJ
Only WDFN−6
ADJ
NCV8711B 5.0V
TSOP−5 / WDFN−6
2M4
RPG
100k
1.2V
NC
RPG
100k
ON
OFF
ON
EN
EN
PG
PG
PG
R2
750k
GND
GND
OFF
PG
Figure 3. Fixed Output Voltage Application with PG
Figure 4. Adjustable Output Voltage Application with PG
R1
R2
@ ǒ1 ) Ǔ
VOUT + VADJ
) IADJ @ R1
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2
NCV8711
SIMPLIFIED BLOCK DIAGRAMS
IN
OUT
UVLO Comparator
UVLO
1.95 V
V
1.2V
V
REF
CCEN
V−REFERENCE
AND SOFT−START
EA
R
R
ADJ1
ADJ2
V
=1.2V
FB
EN
ADJ
Enable
EN Comparator
GND
THERMAL
SHUTDOWN
0.9 V
PG
NC
PG Comparator
DEGLITCH
DELAY TMR
93% of V
REF
Blue objects are valid for ADJ version
Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Note:
Figure 5. Internal Block Diagram
PIN DESCRIPTION
Pin No. TSOP−5 Pin No. WDFNW6
Pin Name
Description
1
2
5
3
6
3
1
4
IN
Power supply input pin.
Ground pin.
GND
OUT
EN
LDO output pin.
Enable input pin (high − enabled, low − disabled). If this pin is connected to IN pin
or if it is left unconnected (pull−up resistor is not required) the device is enabled.
4 (Note 1)
4 (Note 1)
2
5
ADJ
PG
Adjust input pin. Connect it to the output resistor divider or directly to the OUT pin.
Power good output pin. Could be left unconnected or could be connected to GND
if not needed. High level for power ok, low level for fail.
4 (Note 1)
NA
2, 5
EP
NC
Not internally connected. This pin can be tied to the ground plane to improve
thermal dissipation.
EPAD
Connect the exposed pad to GND.
1. Pin function depends on device version.
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3
NCV8711
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
VIN Voltage (Note 2)
VOUT Voltage
EN Voltage
V
IN
−0.3 to 22
V
−0.3 to [(V + 0.3) or 22 V; whichever is lower]
V
OUT
IN
V
−0.3 to (V + 0.3)
V
EN
IN
ADJ Voltage
V
−0.3 to 5.5
V
FB/ADJ
PG Voltage
V
PG
−0.3 to (V + 0.3)
V
IN
Output Current
PG Current
I
Internally limited
mA
mA
°C
°C
V
OUT
I
3
150
PG
Maximum Junction Temperature
T
J(MAX)
Storage Temperature
T
−55 to 150
2000
STG
ESD Capability, Human Body Model (Note 3)
ESD Capability, Charged Device Model (Note 3)
ESD
HBM
CDM
ESD
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114 (AEC−Q100−002)
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101 (AEC−Q100−011D)
THERMAL CHARACTERISTICS (Note 4)
Characteristic
Thermal Resistance, Junction−to−Air
Symbol
WDFNW6 2x2
TSOP−5
147
82
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
63
204
15
47
4
thJA
Thermal Resistance, Junction−to−Case (top)
R
thJCt
Thermal Resistance, Junction−to−Case (bottom)
Thermal Resistance, Junction−to−Board (top)
R
N/A
113
thJCb
R
thJBt
Thermal Characterization Parameter, Junction−to−Case (top)
Thermal Characterization Parameter, Junction−to−Board [FEM]
Psi
22
JCt
Psi
46
113
JB
2
4. Measured according to JEDEC board specification (board 1S2P, Cu layer thickness 1 oz, Cu area 650 mm , no airflow). Detailed description
of the board can be found in JESD51−7.
ELECTRICAL CHARACTERISTICS (V = V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = C = 1.0 mF
OUT
(effective capacitance – Note 5), T = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6)
IN
OUT−NOM
IN
EN
OUT
IN
J
Parameter
Recommended Input Voltage
Output Voltage Accuracy
Test Conditions
Symbol
Min
2.7
−1
−1
−
Typ
Max
18
Unit
V
V
IN
−
−
T = −40°C to +85°C
V
OUT
1
%
J
T = −40°C to +125°C
−
2
J
ADJ Reference Voltage
ADJ Input Current
ADJ version only
V
ADJ
1.2
0.01
−
−
V
V
ADJ
= 1.2 V
I
−0.1
−
0.1
0.2
0.4
2.5
3.0
450
1.5
450
450
355
mA
ADJ
Line Regulation
V
IN
= V
+ 1 V to 18 V and V ≥ 2.7 V DV
%V
OUT−NOM
IN
O(DVI)
OUT
OUT
Load Regulation
I
= 0.1 mA to 100 mA
DV
−
−
%V
OUT
O(DIO)
Quiescent Current (version A)
Quiescent Current (version B)
Ground Current
V
= V
+ 1 V to 18 V, I
= 0 mA
= 0 mA
I
Q
−
1.3
1.8
325
0.35
250
250
215
mA
IN
IN
OUT−NOM
OUT−NOM
OUT
V
= V
+ 1 V to 18 V, I
−
OUT
I
= 100 mA
I
−
mA
mA
OUT
GND
Shutdown Current (Note 10)
Output Current Limit
Short Circuit Current
Dropout Voltage (Note 7)
V
V
V
= 0 V, I
= 0 mA, V = 18 V
I
SHDN
−
EN
OUT
IN
= V
− 100 mV
I
OLIM
140
140
−
mA
mA
mV
OUT
OUT
OUT−NOM
= 0 V
= 100 mA
I
OSC
I
V
DO
OUT
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4
NCV8711
ELECTRICAL CHARACTERISTICS (V = V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = C = 1.0 mF
OUT
IN
OUT−NOM
IN
EN
OUT
IN
(effective capacitance – Note 5), T = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6) (continued)
J
Parameter
Test Conditions
+ 2 V
OUT−NOM
Symbol
Min
−
Typ
80
Max
−
Unit
Power Supply Ripple Rejection
V
= V
10 Hz
10 kHz
100 kHz
1 MHz
= 5.0 V
PSRR
dB
IN
I
= 10 mA
OUT
−
70
−
−
42
−
−
48
−
Output Noise
f = 10 Hz to 100 kHz, V
V
N
−
240
0.9
0.1
0.3
0.05
250
600
1.95
0.2
93
−
mV
RMS
OUT−NOM
EN Threshold
V
EN
V
EN
V
EN
V
EN
V
V
rising
falling
V
V
0.7
0.01
0.01
−1
100
300
1.6
0.05
90
0.1
75
120
−
1.05
0.2
1
V
V
EN−TH
EN−HY
EN−PU
EN Hysteresis
EN Internal Pull−up Current
EN Input Leakage Current
Start−up time (Note 8)
= 1 V, V = 5.5 V
I
mA
mA
ms
IN
= 18 V, V = 18 V
I
t
1
IN
EN−LK
≤ 3.3 V
500
1000
2.6
0.3
96
4
OUT−NOM
OUT−NOM
START
> 3.3 V
Internal UVLO Threshold
Ramp V up until output is turned on
V
V
V
V
IN
IUL−TH
Internal UVLO Hysteresis
Ramp V down until output is turned off
IN
IUL−HY
PG Threshold (Note 9)
V
OUT
V
OUT
falling
rising
V
V
%
%
ms
ms
V
PG−TH
PG−HY
PG−DG
PG Hysteresis (Note 9)
2
PG Deglitch Time (Note 9)
PG Delay Time (Note 9)
t
160
320
0.2
0.01
165
20
270
600
0.4
1
t
PG−DLY
PG Output Low Level Voltage (Note 9)
PG Output Leakage Current (Note 9)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
I
= 1 mA
V
PG
PG−OL
V
PG
= 18 V
I
−
mA
°C
°C
PG−LK
Temperature rising from T = +25°C
T
SD
−
−
J
Temperature falling from T
T
SDH
−
−
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of V
.
OUT−NOM
9. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
10.Shutdown current includes EN Internal Pull−up Current.
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5
NCV8711
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
V = (VOUT-NOM+ 1 V) to 18 V, V ≥ 2.7 V
IN IN
High limit
High limit
IOUT = 1 to 100 mA
Version-B
(with PG)
VOUT-NOM= 5 V
VOUT-NOM= 15 V
Version-A
(non PG)
VOUT-NOM= 1.2 V
Low limit
V = 18 V
IN
-1.5%
-2.0%
0.9
0.7
IOUT= 0 mA
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100 120
JUNCTION TEMPERATURE, T ( C)
°
JUNCTION TEMPERATURE, T ( C)
°
J
J
Figure 6. Output Voltage vs. Temperature
Figure 7. Quiescent Current vs. Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.10
High limit
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
High limit
Note:
Shutdown current is measured at IN pin
and includes EN pin pull-up current.
Low limit
V
IN = 18 V
EN = 0 V
V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, TJ ( C)
°
JUNCTION TEMPERATURE, T ( C)
°
J
Figure 8. Shutdown Current vs. Temperature
Figure 9. Enable Threshold Voltage vs.
Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.10
0.08
0.06
0.04
High limit
High limit
0.02
0.00
VEN = 1 V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE ( C)
°
TEMPERATURE (°C)
Figure 10. Enable Internal Pull−Up Current vs.
Temperature
Figure 11. ADJ Input Current vs. Temperature
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6
NCV8711
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
400
High limit
350
300
250
200
150
100
50
VOUT = VOUT-NOM - 100 mV
IOUT = 100 mA
All output voltage versions
0
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, T ( C)
°
J
Figure 12. Dropout Voltage vs. Temperature
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NCV8711
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C
= 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT−NOM
IN
EN
OUT
OUT
J
Figure 13. PSRR − FIX−3.3 V, COUT = 1 mF,
OUT = 100 mA
Figure 14. PSRR − FIX−3.3 V, VIN = 4.3 V, IOUT
100 mA
=
I
Figure 15. PSRR − FIX−3.3 V, VIN = 8.3 V, IOUT
100 mA
=
Figure 16. Noise – FIX − 5.0 V, IOUT = 10 mA,
Different COUT
Figure 17. Noise – ADJ−set−5.0 V with
Different CFF and FIX − 5.0 V
Figure 18. Noise – FIX, IOUT = 10 mA,
C
OUT = 1 mF, Different VOUT
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8
NCV8711
ORDERING INFORMATION
Part Number
Marking
GGA
GGC
GGD
GGE
GA
Voltage Option (V
)
Version
Package
Shipping
OUT−NOM
NCV8711ASNADJT1G
NCV8711ASN300T1G
NCV8711ASN330T1G
NCV8711ASN500T1G
NCV8711BMTWADJTBG
NCV8711BMTW300TBG
NCV8711BMTW330TBG
NCV8711BMTW500TBG
ADJ
3.0 V
3.3 V
5.0 V
ADJ
TSOP−5
(Pb−Free)
Without PG
3000 / Tape & Reel
GC
3.0 V
3.3 V
5.0 V
WDFNW6
(Pb−Free)
With PG
3000 / Tape & Reel
GD
GE
NOTE: To order other package, voltage version or PG / non PG variant, please contact your ON Semiconductor sales representative.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW6 2x2, 0.65P
CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXMG
G
M
= Month Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79327G
WDFNW6 2x2, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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