NCV887100D1R2G [ONSEMI]
Automotive Grade Non-Synchronous Boost Controller;
| 型号： | NCV887100D1R2G |
| 厂家： | 
ONSEMI |
| 描述： | Automotive Grade Non-Synchronous Boost Controller 开关 光电二极管 |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV8871
Automotive Grade
Non-Synchronous Boost
Controller
The NCV8871 is an adjustable output non−synchronous boost
controller which drives an external N−channel MOSFET. The device
uses peak current mode control with internal slope compensation. The
IC incorporates an internal regulator that supplies charge to the gate
driver.
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MARKING
DIAGRAM
Protection features include internally−set soft−start, undervoltage
lockout, cycle−by−cycle current limiting, hiccup−mode short−circuit
protection and thermal shutdown.
Additional features include low quiescent current sleep mode and
externally−synchronizable switching frequency.
8
SOIC−8
D SUFFIX
CASE 751
8871xx
ALYW
G
8
1
1
8871xx = Specific Device Code
xx = 00, 01, 02, 03, 04
Features
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Peak Current Mode Control with Internal Slope Compensation
• 1.2 V 2% Reference voltage
• Fixed Frequency Operation
• Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump
• Input Undervoltage Lockout (UVLO)
• Internal Soft−Start
PIN CONNECTIONS
• Low Quiescent Current in Sleep Mode
• Cycle−by−Cycle Current Limit Protection
• Hiccup−Mode Overcurrent Protection (OCP)
• Hiccup−Mode Short−Circuit Protection (SCP)
• Thermal Shutdown (TSD)
1
2
3
4
8
7
6
5
EN/SYNC
ISNS
VFB
VC
GND
VIN
GDRV
VDRV
• This is a Pb−Free Device
(Top View)
ORDERING INFORMATION
†
Device
Package
Shipping
NCV887100D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887101D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887102D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887103D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887104D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
September, 2012 − Rev. 3
NCV8871/D
NCV8871
V
g
VIN
6
TEMP
C
L
g
VDRV
C
VDRV
DRV
FAULT
LOGIC
D
5
4
V
o
CLK
EN/
EN/SYNC
VC
Q
OSC
GDRV
1
7
DRIVE
LOGIC
SYNC
SC
ISNS
GND
2
3
C
o
CL
R
SNS
CSA
+
R
SCP
F1
R
C
C
VFB
8
C
Gm
R
F2
SS
V
ref
Figure 1. Simplified Block Diagram and Application Schematic
PACKAGE PIN DESCRIPTIONS
Pin
Symbol
Pin No.
Function
1
EN/SYNC
Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled
into sleep mode when this pin is brought low for longer than the enable time−out period.
2
ISNS
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3
4
GND
Ground reference.
GDRV
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance.
5
6
7
8
VDRV
VIN
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to ground.
Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-
tion to a diode from the output voltage to VDRV and/or VIN.
VC
Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
VFB
Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.
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NCV8871
ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating
Value
−0.3 to 40
45
Unit
V
Dc Supply Voltage (VIN)
Peak Transient Voltage (Load Dump on VIN)
Dc Supply Voltage (VDRV, GDRV)
V
12
V
Peak Transient Voltage (VFB)
−0.3 to 6
−0.3 to 3.6
−0.3 to 6
−0.7 to 45
−40 to 150
−65 to 150
265 peak
V
Dc Voltage (VC, VFB, ISNS)
V
Dc Voltage (EN/SYNC)
V
Dc Voltage Stress (VIN − VDRV)*
V
Operating Junction Temperature
°C
°C
°C
Storage Temperature Range
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.
PACKAGE CAPABILITIES
Characteristic
Value
Unit
ESD Capability (All Pins)
Moisture Sensitivity Level
Human Body Model
Machine Model
w2.0
kV
V
w200
1
−
Package Thermal Resistance
Junction−to−Ambient, R
(Note 1)
100
°C/W
q
JA
2
1. 1 in , 1 oz copper area used for heatsinking.
Device Variations
The NCV8871 features several variants to better fit a
multitude of applications. The table below shows the typical
values of parameters for the parts that are currently
available.
TYPICAL VALUES
Part No.
D
f
t
S
V
I
I
V
DRV
SCE
Y
max
s
ss
a
cl
src
sink
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
88%
86%
91%
93%
93%
170 kHz
1000 kHz
1000 kHz
340 kHz
340 kHz
7.4 ms
1.25 ms
1.25 ms
3.7 ms
3.7 ms
53 mV/ms
16 mV/ms
53 mV/ms
53 mV/ms
53 mV/ms
400 mV
400 mV
400 mV
200 mV
200 mV
800 mA
575 mA
800 mA
575 mA
800 mA
600 mA
350 mA
600 mA
350 mA
600 mA
10.5 V
6.3 V
6.3 V
8.4 V
8.4 V
Y
N
Y
N
DEFINITIONS
Symbol
Characteristic
Symbol
Characteristic
Switching Frequency
Current Limit Trip Voltage
Drive Voltage
Symbol
Characteristic
D
Maximum Duty Cycle
f
s
t
ss
Soft−Start Time
max
S
Slope Compensating Ramp
Gate Drive Sinking Current
V
cl
I
src
Gate Drive Sourcing Current
Short Circuit Enable
a
I
V
DRV
SCE
sink
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NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C, 3.2 V < V < 40 V, unless otherwise specified) Min/Max values are
J
IN
guaranteed by test, design or statistical correlation.
Characteristic Symbol
GENERAL
Conditions
Min
Typ
Max
Unit
Quiescent Current, Sleep Mode
Quiescent Current, Sleep Mode
Quiescent Current, No switching
I
I
V
= 13.2 V, EN = 0, T = 25°C
−
−
−
−
2.0
2.0
1.5
3.0
−
mA
mA
q,sleep
q,sleep
IN
J
V
IN
= 13.2 V, EN = 0, −40°C < T < 125°C
6.0
2.5
6.0
J
I
I
Into VIN pin, EN = 1, No switching
Into VIN pin, EN = 1, Switching
mA
mA
q,off
q,on
Quiescent Current, Switching,
normal operation
OSCILLATOR
Minimum pulse width
Maximum duty cycle
t
90
115
140
ns
%
on,min
D
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
86
84
89
91
91
88
86
91
93
93
90
88
93
95
95
max
Switching frequency
f
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
153
900
900
306
306
170
1000
1000
340
187
1100
1100
374
kHz
ms
s
340
374
Soft−start time
t
ss
From start of switching with V = 0 until
FB
reference voltage = V
NCV887100
REF
6.0
1.0
1.0
3.0
3.0
7.4
1.25
1.25
3.7
8.8
1.5
1.5
4.4
4.4
NCV887101
NCV887102
NCV887103
NCV887104
3.7
Soft−start delay
t
From EN → 1 until start of switching with
= 0
ms
ss,dly
V
−
240
280
FB
Slope compensating ramp
S
a
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
46
13
46
46
46
53
16
53
53
53
60
19
60
60
60
mV/ms
ENABLE/SYNCHRONIZATION
EN/SYNC pull−down current
EN/SYNC input high voltage
EN/SYNC input low voltage
EN/SYNC time−out ratio
I
V
= 5 V
−
2.0
0
5.0
−
10
mA
V
EN/SYNC
EN/SYNC
V
s,ih
5.0
800
350
V
s,il
−
mV
%
%t
en
From SYNC falling edge, to oscillator con-
trol (EN high) or shutdown (EN low), Per-
cent of typical switching period
−
−
SYNC minimum frequency ratio
SYNC maximum frequency
Synchronization delay
%f
Percent of f
−
1.1
−
−
−
80
−
%
MHz
ns
sync,min
s
f
sync,max
t
From SYNC falling edge to GDRV falling
edge
50
100
s,dly
Synchronization duty cycle
CURRENT SENSE AMPLIFIER
Low−frequency gain
D
25
−
75
%
sync
A
Input−to−output gain at dc, ISNS v 1 V
0.9
2.5
−
1.0
−
1.1
−
V/V
MHz
mA
csa
Bandwidth
BW
csa
sns,bias
Gain of A
− 3 dB
csa
ISNS input bias current
I
Out of ISNS pin
30
50
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NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C, 3.2 V < V < 40 V, unless otherwise specified) Min/Max values are
J
IN
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
CURRENT SENSE AMPLIFIER
Current limit threshold voltage
V
cl
Voltage on ISNS pin
mV
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
360
360
360
180
180
400
400
400
200
200
440
440
440
220
220
Current limit,
t
CL tripped until GDRV falling edge,
ISNS cl
−
125
−
80
150
−
125
175
125
ns
%
cl
Response time
V
= V + 40 mV
Overcurrent protection,
Threshold voltage
%V
Percent of V
cl
ocp
Overcurrent protection,
Response Time
t
From overcurrent event, Until switching
stops, V = V + 40 mV
ns
ocp
ISNS
OCP
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance
g
V
– V =
ref
20 mV
0.8
2.0
−
1.2
−
1.5
−
mS
MW
mA
V
m,vea
FB
VEA output resistance
VFB input bias current
Reference voltage
R
o,vea
I
Current out of VFB pin
0.5
1.200
−
2.0
1.224
−
vfb,bias
V
ref
1.176
2.5
−
VEA maximum output voltage
VEA minimum output voltage
VEA sourcing current
VEA sinking current
GATE DRIVER
V
V
c,max
V
−
0.3
−
V
c,min
I
VEA output current, Vc = 2.0 V
VEA output current, Vc = 0.7 V
80
100
100
mA
mA
src,vea
I
80
−
snk,vea
Sourcing current
I
src
V
≥ 6 V, V
− V = 2 V
GDRV
mA
DRV
DRV
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
600
400
600
400
600
800
575
800
575
800
−
−
−
−
−
Sinking current
I
V
≥ 2 V
mA
sink
GDRV
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
500
250
500
250
500
600
350
600
350
600
−
−
−
−
−
Driving voltage dropout
Driving voltage source current
Backdrive diode voltage drop
Driving voltage
V
V
V
V
− V
− V
, Iv
= 25 mA
−
35
−
0.3
45
−
0.6
−
V
mA
V
drv,do
IN
DRV
DRV
I
= 1 V
drv
IN
DRV
V
− V , I = 5 mA
IN d,bd
0.7
d,bd
DRV
DRV
V
I
= 0.1 − 25 mA
V
VDRV
NCV887100
NCV887101
NCV887102
NCV887103
NCV887104
10
6.0
6.0
8.0
8.0
10.5
6.3
6.3
8.4
8.4
11
6.6
6.6
8.8
8.8
UVLO
Undervoltage lock−out,
V
V
V
falling
rising
3.0
50
3.1
3.2
V
uvlo
IN
Threshold voltage
Undervoltage lock−out,
Hysteresis
V
125
200
mV
uvlo,hys
IN
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NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C, 3.2 V < V < 40 V, unless otherwise specified) Min/Max values are
J
IN
guaranteed by test, design or statistical correlation.
Characteristic
SHORT CIRCUIT PROTECTION
Startup blanking period
Hiccup−mode period
Symbol
Conditions
Min
Typ
Max
Unit
%t
%t
From start of soft−start, Percent of t
100
70
120
85
150
100
%
%
scp,dly
ss
From shutdown to start of soft−start,
Percent of t
hcp,dly
ss
Short circuit threshold voltage
Short circuit delay
%V
V
as percent of V
60
67
35
75
%
scp
FB
ref
t
From V < V to stop switching
scp
−
100
ns
scp
FB
THERMAL SHUTDOWN
Thermal shutdown threshold
Thermal shutdown hysteresis
Thermal shutdown delay
T
T rising
160
10
−
170
15
−
180
20
°C
°C
ns
sd
J
T
T falling
J
sd,hys
sd,dly
t
From T > T to stop switching
100
J
sd
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NCV8871
TYPICAL PERFORMANCE CHARACTERISTICS
7
6
5
4
3
2
1
0
5.5
5.0
4.5
4.0
3.5
T = 25°C
J
T = 25°C,
J
V
IN
= 13.2 V
0
10
20
30
40
0
200
400
600
800
1000
V
IN
, INPUT VOLTAGE (V)
f , SWITCHING FREQUENCY (kHz)
s
Figure 2. Sleep Current vs. Input Voltage
Figure 3. Quiescent Current vs. Switching
Frequency
3.30
6
V
= 13.2 V
IN
V
= 13.2 V
IN
f = 170 kHz
s
5
4
3
2
1
0
3.25
3.20
3.15
3.10
3.05
3.00
−50
0
50
100
150
200
−40
10
60
110
160
T , JUNCTION TEMPERATURE (°C)
Figure 5. Quiescent Current vs. Temperature
J
T , JUNCTION TEMPERATURE (°C)
Figure 4. Sleep Current vs. Temperature
J
125
1.010
1.005
1.000
0.995
0.990
123
121
119
117
115
−40
10
60
110
160
−40
10
60
110
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 6. Minimum On Time vs. Temperature
Figure 7. Normalized Current Limit vs.
Temperature
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NCV8871
TYPICAL PERFORMANCE CHARACTERISTICS
1.205
1.203
1.201
1.199
1.197
1.195
7
T = 25°C
J
6
5
4
3
2
1
0
0
1
2
3
4
5
6
−40
10
60
110
160
V
enable
, VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. Reference Voltage vs. Temperature
Figure 9. Enable Pulldown Current vs. Voltage
8.0
7.5
7.0
6.5
6.0
5.5
5.0
−40
10
60
110
160
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. Enable Pulldown Current vs.
Temperature
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NCV8871
THEORY OF OPERATION
VIN
VOUT
L
GDRV
Oscillator
S
R
Q
Gate
Drive
PWM Comparator
−
CO
RL
+
ISNS
+
+
CSA
−
Slope
Compensation
VFB
Voltage Error
−
+
VEA
NCV8871
Compensation
Figure 11. Current Mode Control Schematic
Current Mode Control
If the voltage across the current sense resistor exceeds the
over current threshold voltage the device enters over current
hiccup mode. The device will remain off for the hiccup time
and then go through the soft−start procedure.
The NCV8871 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
Short Circuit Protection
If the short circuit enable bit is set (SCE = Y) the device
will attempt to protect the power MOSFET from damage.
When the output voltage falls below the short circuit trip
voltage, after the initial short circuit blanking time, the
device enters short circuit latch off. The device will remain
off for the hiccup time and then go through the soft−start.
EN/SYNC
The Enable/Synchronization pin has three modes. When
a dc logic high (CMOS/TTL compatible) voltage is applied
to this pin the NCV8871 operates at the programmed
frequency. When a dc logic low voltage is applied to this pin
the NCV8871 enters a low quiescent current sleep mode.
The NCV8871 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
When a square wave of at least %f
of the free running
sync,min
switching frequency is applied to this pin, the switcher
operates at the same frequency as the square wave. If the
signal is slower than this, it will be interpreted as enabling
and disabling the part. The falling edge of the square wave
corresponds to the start of the switching cycle. If device is
disabled, it must be disabled for 7 clock cycles before being
re−enabled.
Current Limit
The NCV8871 features two current limit protections,
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
= V / I
.
CL limit
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NCV8871
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV8871 features a soft start which charges a
capacitor with a fixed current to ramp up the reference voltage.
This fixed current is based on the switching frequency, so
that if the NCV8871 is synchronized to twice the default
switching frequency the soft start will last half as long.
If the calculated D
is higher the D
of the NCV8871,
max
max
the conversion will not be possible. It is important for a boost
converter to have a restricted D , because while the ideal
max
conversion ration of a boost converter goes up to infinity as
D approaches 1, a real converter’s conversion ratio starts to
decrease as losses overtake the increased power transfer. If
the converter is in this range it will not be able to regulate
properly.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
If the following equation is not satisfied, the device will
skip pulses at high V :
IN
D
fs
min w ton(min)
APPLICATION INFORMATION
Where: f : switching frequency [Hz]
Design Methodology
s
This section details an overview of the component selection
process for the NCV8871 in continuous conduction mode
boost. It is intended to assist with the design process but does
not remove all engineering design work. Many of the
equations make heavy use of the small ripple approximation.
This process entails the following steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
t
: minimum on time [s]
on(min)
2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
VCL
RS
+
ICL
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
Where: R : sense resistor [W]
S
V : current limit threshold voltage [V]
CL
I
: desire current limit [A]
CL
9. Select Diode
3. Select Output Inductor
1. Define Operational Parameters
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 10% of the inductor current
Before beginning the design, define the operating
parameters of the application. These include:
V
V
V
: minimum input voltage [V]
IN(min)
maximum input voltage [V]
IN(max):
: output voltage [V]
OUT
I
I
: maximum output current [A]
: desired typical cycle-by-cycle current limit [A]
OUT(max)
at the maximum load at the worst case V , but operation
IN
CL
should be verified empirically. The worst case V is half of
IN
V
, or whatever V is closest to half of V . After
OUT
IN IN
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
choosing a peak current ripple value, calculate the inductor
value as follows:
VIN(max)
2
VIN(WC) DWC
D
D
min + 1 *
max + 1 *
VOUT
L +
DIL,max fsVOUT
VIN(min)
VOUT
Where: V
: V value as close as possible to
IN
IN(WC)
half of V
[V]
OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
D
DI
: duty cycle at V
WC
IN(WC)
: maximum peak to peak ripple [A]
L,max
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10
NCV8871
7. Select Compensator Components
The maximum average inductor current can be calculated
as follows:
Current Mode control method employed by the NCV8871
allows the use of a simple, Type II compensation to optimize
the dynamic response according to system requirements.
V
OUTIOUT(max)
IL,avg
+
VIN(min)
8. Select MOSFET(s)
The Peak Inductor current can be calculated as follows:
2
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
VIN(min) Dmax
I
L,peak + IL,avg )
LfsVOUT
Where: I
: Peak inductor current value [A]
L,peak
Idrv
fs
Q
g(total) v
4. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
Where: Q
: Total Gate Charge of MOSFET(s) [C]
g(total)
I
: Drive voltage current [A]
drv
f : Switching Frequency [Hz]
s
The maximum RMS Current can be calculated as follows:
VOUT(ripple)
+
Ǹ
D
ID(max) + I
ǒV
Ǔ
IOUT(max) OUT * VIN(min)
out DȀ
I
OUT(max)VOUTRESR
)
ǒC fǓ2
VIN(min)
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
OUT
The capacitors need to survive an RMS ripple current as
follows:
V
Q(max) + VOUT(max)
V
OUT * VIN(min)
Ǹ
I
Cout(RMS) + IOUT
VIN(min)
9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
I
D(avg) + IOUT(max)
5. Select Input Capacitors
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
V
D(max) + VOUT(max)
2
The maximum power dissipation in the diode can be
calculated as follows:
VIN(WC) DWC
ICin(RMS)
+
Ǹ
LfsVOUT2 3
P
D + Vf(max) IOUT(max)
6. Select Feedback Resistors
Where: P : Power dissipation in the diode [W]
d
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
V
: Maximum forward voltage of the diode [V]
f(max)
Low Voltage Operation
pin. During regulation, the divided voltage will equal V .
ref
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
ǒ
refǓ
V
out * V
R
upper + Rlower
Vref
The total feedback resistance (R
+ R
) should be in
upper
lower
the range of 1 kW – 100 kW.
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11
NCV8871
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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