NCV891130PD33R2G [ONSEMI]
1.2 A，2 MHz 低 Iq 双模式步降稳压器，用于汽车;
| 型号： | NCV891130PD33R2G |
| 厂家： | 
ONSEMI |
| 描述： | 1.2 A，2 MHz 低 Iq 双模式步降稳压器，用于汽车 稳压器 |
| 文件： | 总15页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV891130
Step-Down Regulator -
Automotive, Low-Iq,
Dual-Mode
1.2 A, 2 MHz
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The NCV891130 is a Dual Mode regulator intended for Automotive,
battery−connected applications that must operate with up to a 45 V
input supply. Depending on the output load, it operates either as a PWM
Buck Converter or as a Low Drop−Out Linear Regulator, and is suitable
for systems with low noise and Low Quiescent Current requirements
often encountered in automotive driver information systems. A reset
pin (with fixed delay) simplifies interfacing with a microcontroller.
The NCV891130 also provides several protection features expected
in automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor – forming a
space−efficient switching regulator solution.
8
1
SOIC−8
EXPOSED PAD
CASE 751AC
MARKING DIAGRAM
8
891130XX
ALYW
G
Features
• 30 mA Iq in Light Load Condition
• 1.2 A Maximum Output Current in PWM Mode
• Internal N−channel Power Switch
1
With XX = 33 for 3.3 V Output
= 40 for 4.0 V Output
= 50 for 5.0 V Output
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
• V Operating Range 3.7 V to 36 V
IN
A
L
Y
W
G
• Withstands Load Dump to 45 V
• Logic Level Enable Pin can be Tied to Battery
• Fixed Output Voltage of 5.0 V, 4.0 V or 3.3 V
• 2 MHz Free−running Switching Frequency
•
2 % Output Voltage Accuracy
PIN CONNECTIONS
• NCV Prefix for Automotive Requiring Site and Control Changes
• These Devices are Pb−Free and are RoHS Compliant
1
8
7
6
5
VIN
SW
Typical Applications
• Audio
• Infotainment
• Instrumentation
• Safety−Vision Systems
2
3
4
DRV
BST
VOUT
EN
RSTB
GND
(Top View)
CDRV
DBST
NCV891130
L1
VOUT
COUT
VIN
VIN
SW
BST
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
CBST
CIN
RESET
DFW
DRV
RSTB
GND
VOUT
EN
EN
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2019 − Rev. 1
NCV891130/D
NCV891130
CDRV
SW
DBST
VIN
VIN
CIN
L1
VOUT
COUT
3.3 V
Reg
DFW
CBST
DRV
BST
VOUT
EN
Low
ON
PWM
Oscillator
LOGIC
OFF
Enable
+
+
S
+
−
comp
EN
1.2 A
detector
−
+
+
TSD
Soft−Start
RESET
VOLTAGES
MONITORS
RSTB
GND
RESET
Switcher Supply
ON
LINEAR
REGULATOR
ON OVLD
MODE
−
+
SELECTION
+
Logic
NCV891130
Figure 2. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
VIN
Description
1
2
3
4
5
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Output voltage to provide a regulated voltage to the Power Switch gate driver.
DRV
RSTB
GND
EN
Reset function. Open drain output, pulling down to ground when the output voltage is out of regulation.
Battery return, and output voltage ground reference.
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
6
7
VOUT
BST
SW
Output voltage feedback and LDO output. Feedback of output voltage used for regulation, as well as LDO
output in LDO mode.
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for minimum
switch Rdson and highest efficiency.
8
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
EPAD
Connect to Pin 4 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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2
NCV891130
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 45
45
Unit
V
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
V
−0.7 to 40
−3.0
V
Min Voltage SW − 20 ns
Min/Max Voltage EN
V
−0.3 to 40
−1.5 to 45
−0.3 to 43
−0.3 to 3.6
−0.3 to 6
−0.3 to 18
−0.3 to 3.6
30
V
Min/Max Voltage VIN to EN
Min/Max Voltage BST
V
V
Min/Max Voltage BST to SW
Min/Max Voltage on RSTB
Min/Max Voltage VOUT
Min/Max Voltage DRV
V
V
V
V
Thermal Resistance, SOIC8−EP Junction–to–Ambient (Note 1)
Storage Temperature range
R
°C/W
°C
°C
kV
θ
JA
J
−55 to +150
−40 to +150
2.0
Operating Junction Temperature Range
T
ESD withstand Voltage (Note 2)
Moisture Sensitivity
Human Body Model
VESD
MSL
Level 2
Peak Reflow Soldering Temperature (Note 3)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2
2
1. Value based on 4 layers of 645 mm (or 1 in ) of 1 oz copper thickness on FR4 PCB substrate.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. ELECTRICAL CHARACTERISTICS
V
= 4.5 to 28 V, V = 5 V, V
= V
+ 3 V, C
= 0.1 mF, for typical values T = 25°C, Min/Max values are valid for the temperature
IN
EN
BST
SW
DRV J
range −40°C v T v 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
J
Parameter
QUIESCENT CURRENT
Test Conditions
Symbol
Min
Typ
Max
Unit
Quiescent Current, enabled
Quiescent Current, shutdown
UNDERVOLTAGE LOCKOUT – VIN (UVLO)
UVLO Start Threshold
V
V
= 13.2 V, I
= 100 mA, 25°C
I
q
30
9
39
12
mA
mA
IN
OUT
= 13.2 V, V = 0 V, 25°C
I
qSD
IN
EN
V
V
rising
falling
V
V
4.1
3.1
0.4
4.5
3.7
1.4
V
V
V
IN
UVLSTT
UVLSTP
UVLOHY
UVLO Stop Threshold
IN
UVLO Hysteresis
V
SOFT−START (SS)
Soft−Start Completion Time
OUTPUT VOLTAGE
t
0.8
1.4
2.0
ms
V
SS
Output Voltage during regulation
100 mA < I
< 1.2 A
V
OUTreg
OUT
5.0 V option
4.0 V option
3.3 V option
4.9
3.92
3.234
5.0
4.0
3.3
5.1
4.08
3.366
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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3
NCV891130
Table 3. ELECTRICAL CHARACTERISTICS
V
= 4.5 to 28 V, V = 5 V, V
= V
+ 3 V, C
= 0.1 mF, for typical values T = 25°C, Min/Max values are valid for the temperature
IN
EN
BST
SW
DRV J
range −40°C v T v 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency
4.5 < V < 18 V
F
1.8
0.9
2.0
1.0
2.2
1.1
MHz
IN
SW
20 V <V < 28V
F
IN
SW(HV)
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
V
V
IN
V
IN
rising
falling
V
V
18.4
18
20
FLDUP
FLDDN
19.8
Frequency Foldback Hysteresis
V
FLDHY
0.2
0.3
0.4
40
MODE TRANSITION
Normal to Low−Iq mode Current Threshold 8 V < V < 28 V
I
3
mA
IN
NtoL
Mode Transition Duration
Switcher to Linear
ms
t
t
300
1
SWtoLIN
LINtoSW
Linear to Switcher
2
Minimum time in Normal Mode before
starting to monitor output current
t
500
ms
SWblank
Linear to switcher transition
at high Vin
V
OUT
= 3.3 V
V
V
19
3.6
28
4.5
LINtoSW(HV)
LINtoSW(LV)
at low Vin
V
PEAK CURRENT LIMIT
Current Limit Threshold
POWER SWITCH
I
2.1
2.35
180
2.6
A
LIM
ON Resistance
V
V
= V
+ 3.0 V
R
360
10
mW
mA
ns
BST
SW
DSON
Leakage current VIN to SW
Minimum ON Time
= 0, −40°C v T v 85°C
I
SW
J
LKSW
Measured at SW pin
t
45
30
70
ONMIN
Minimum OFF Time
Measured at SW pin
t
ns
OFFMIN
At F
At F
= 2 MHz (normal)
= 500 kHz (max duty cycle)
30
50
SW
SW
70
SLOPE COMPENSATION
Ramp Slope
(With respect to switch current)
4.5 < V < 18 V
S
1.45
0.65
2.0
1.0
2.8
1.3
A/ms
IN
ramp
20 V <V < 28V
S
IN
ramp(HV)
LOW POWER LINEAR REGULATOR
Line Regulation
I
= 5 mA, 6 V < V < 18 V
V
5
5
25
35
mV
mV
dB
OUT
IN
REG(line)
Load Regulation
V
= 13.2 V, 0.1 mA < I
< 50 mA
V
REG(load)
IN
OUT
Power Supply Rejection
Current Limit
V
= 0.5 Vp−p, F = 100 Hz
PSRR
65
OUT(ripple)
I
50
80
mA
mA
LIN(lim)
Output clamp current
V
= V
+ 10%
I
CL(OUT)
0.5
1.0
1.5
OUT
OUTreg(typ)
SHORT CIRCUIT DETECTOR
Switching frequency in short−circuit condi-
kHz
tion
Analog Foldback
Analog foldback – high V
Hiccup Mode
V
OUT
V
OUT
= 0 V, 4.5 V < V < 18 V
F
SWAF
450
225
24
550
275
32
650
325
40
IN
= 0 V, 20 V <V < 28 V
F
IN
IN
SWAFHV
F
SWHIC
RESET
Leakage current into RSTB pin
I
1
uA
RSTBlk
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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4
NCV891130
Table 3. ELECTRICAL CHARACTERISTICS
V
= 4.5 to 28 V, V = 5 V, V
= V
+ 3 V, C
= 0.1 mF, for typical values T = 25°C, Min/Max values are valid for the temperature
IN
EN
BST
SW
DRV J
range −40°C v T v 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
RESET
Output voltage threshold at which the RSTB
signal goes low
V
OUT
V
OUT
decreasing
V
V
RESET
REShys
5.0 V option
4.0 V option
3.3 V option
4.50
3.6
2.97
4.625
3.7
3.05
4.75
3.8
3.14
Hysteresis on RSTB threshold
increasing
V
mV
5.0 V option
4.0 V option
3.3 V option
25
20
17
60
50
40
100
80
66
Noise−filtering delay
From V
<V
to RSTB pin
t
filter
10
25
18
ms
ms
V
OUT
RESET
going low
Restart Delay time
From V
>V
RESET
+V
REShys
to
t
delay
14
16
OUT
high RSTB
Low RSTB voltage
R
= V
/1 mA, V
> 1 V
V
0.4
RSTBpullup
OUTreg
OUT
RSTBlow
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
V
3.1
2.7
2.5
50
3.3
2.9
2.8
3.5
3.05
3.0
V
V
DRV
DRV UVLO START Threshold
DRV UVLO STOP Threshold
DRV UVLO Hysteresis
DRV Current Limit
V
V
DRVSTT
DRVSTP
DRVHYS
DRVLIM
V
V
200
50
mV
mA
V
DRV
= 0 V
I
21
VIN OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
Overvoltage Start Threshold
Overvoltage Hysteresis
ENABLE (EN)
V
increasing
decreasing
V
V
36.5
36.0
0.25
37.7
37.3
0.40
39.0
38.8
0.50
V
V
V
IN
OVSTP
V
IN
OVSTT
V
OVHY
Logic low threshold voltage
Logic high threshold voltage
EN pin input current
V
0.8
0.2
V
V
ENlow
ENhigh
ENbias
V
2
1
I
mA
THERMAL SHUTDOWN
Activation Temperature
Reset temperature
TSD
155
135
5
190
185
20
°C
°C
°C
TSD
restart
HYS
Hysteresis
T
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCV891130
TYPICAL CHARACTERISTICS
80
70
60
50
40
30
20
1000
800
600
400
200
0
10
0
0
5
10
15
20
0
200
400
600
800
1000
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 3. No−load Input Current at TJ = 255C
Figure 4. Input Current at TJ = 255C vs. Output
vs. Input Voltage
Current
100
80
13
12
11
60
10
9
40
20
0
8
7
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Low−Iq Mode Quiescent Current vs.
Figure 6. Shutdown Mode Quiescent Current
vs. Junction Temperature
Junction Temperature
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
1.6
1.5
1.4
Switcher Mode
Low−Iq Mode
1.3
1.2
3.25
3.24
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Switching Mode Quiescent Current
vs. Junction Temperature
Figure 8. 3.3 V Output Voltage vs. Junction
Temperature
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NCV891130
TYPICAL CHARACTERISTICS
4.05
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
5.05
5.04
5.03
5.02
5.01
Switcher Mode
Switcher Mode
5.00
4.99
4.98
4.97
4.96
Low−Iq Mode
Low−Iq Mode
4.95
4.94
3.95
3.94
−50
0
50
100
150
150
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. 4.0 V Output Voltage vs. Junction
Temperature
Figure 10. 5.0 V Output Voltage vs. Junction
Temperature
2.2
2.1
57
56
55
54
2.0
1.9
1.8
53
52
−50
0
50
100
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Switching Frequency vs. Junction
Temperature
Figure 12. Minimum On Time vs. Junction
Temperature
2.5
2.4
2.3
4.7
4.6
4.5
4.4
2.2
2.1
4.3
4.2
−50
0
50
100
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Peak Current Limit vs. Junction
Temperature
Figure 14. Peak Current Limit vs. Junction
Temperature
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NCV891130
TYPICAL CHARACTERISTICS
4.6
4.4
4.2
4.0
3.8
3.6
3.4
40
Start−up Threshold
39
38
37
36
Overvoltage Threshold
Restart Threshold
UVLO Threshold
100
35
34
3.2
3.0
−50
0
50
150
150
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. UVLO Thresholds vs. Junction
Temperature
Figure 16. Input Overvoltage Thresholds vs.
Junction Temperature
1.60
1.55
1.50
3.5
3.4
3.3
3.2
I
= 0 mA
DRV
I
= 21 mA
DRV
1.45
1.40
3.1
3.0
−50
0
50
100
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Soft−start Duration vs. Junction
Figure 18. DRV Voltage vs. Junction
Temperature
Temperature
3.0
2.9
2.8
19.8
19.6
19.4
19.2
19.0
18.8
18.6
18.4
DRV Start−up Threshold
V
Rising
Falling
IN
V
IN
DRV UVLO Threshold
2.7
2.6
18.2
18.0
−50
0
50
100
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. DRV Voltage UVLO Tresholds vs.
Junction Temperature
Figure 20. Frequency Foldback Voltage
Tresholds vs. Junction Temperature
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NCV891130
TYPICAL CHARACTERISTICS
3.3
1.10
1.05
1.00
3.2
3.1
3.0
RSTB Toggles High (V
Rising)
Falling)
OUT
RSTB Toggles Low (V
OUT
0.95
0.90
2.9
2.8
−50
0
50
100
150
−50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
Figure 21. Foldback Frequency vs. Junction
Temperature
Figure 22. 3.3 V Version RESET Thresholds vs.
Junction Temperature
4.0
3.9
3.8
3.7
3.6
5.0
4.9
4.8
4.7
4.6
4.5
RSTB Toggles High (V
Rising)
Falling)
OUT
RSTB Toggles High (V
Rising)
Falling)
OUT
RSTB Toggles Low (V
OUT
RSTB Toggles Low (V
OUT
3.5
3.4
4.4
4.3
−50
0
50
TEMPERATURE (°C)
100
150
−50
0
50
TEMPERATURE (°C)
100
150
Figure 23. 4.0 V Version RESET Thresholds vs.
Junction Temperature
Figure 24. 5.0 V Version RESET Thresholds vs.
Junction Temperature
17.0
16.8
16.6
16.4
16.2
16.0
15.8
71
69
67
65
63
61
59
15.6
15.4
57
55
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. RESET Delay vs. Junction
Temperature
Figure 26. Low−Iq to Switcher Mode Transition
vs. Junction Temperature
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NCV891130
TYPICAL CHARACTERISTICS
30
20
30
20
10
0
10
0
5
10
15
18
5
10
15
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 27. Switcher to Low−Iq Mode Transition
(3.3 V Version, 2.2 mH) vs. Input Voltage
Figure 28. Switcher to Low−Iq Mode Transition
(5.0 V Version, 2.2 mH) vs. Input Voltage
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NCV891130
APPLICATION INFORMATION
Hybrid Low−Power Mode
A high−frequency switch−mode regulator is not very
efficient in light load conditions, making it difficult to
achieve low−Iq requirements for sleep−mode operation. To
remedy this, the NCV891130 includes a low−Iq linear
regulator that turns on at light load, while the PWM
regulator turns off, ensuring a high−efficiency low−power
operation. Another advantage of the low−power mode is the
tight regulation free of voltage ripple usually associated with
low−Iq switchers in light load conditions. In either mode, the
NCV891130 meets the 2% output voltage regulation
specification.
At initial start−up the NCV891130 will soft−start into
PWM converter mode regardless of output current. During
a 300 s period, the NCV891130 will assess the level of
output current. The NCV891130 will not make the
assessment if RSTB is low. If the output current is above the
V
, it will not transition to low−power mode even if the
FLDUP
output current becomes lower than I
At low input voltage, the NCV891130 stays in low−power
mode down to V if it entered this mode while in
normal battery range. However it may not enter low−power
mode below 8 V depending on the charge of the bootstrap
capacitor (see Bootstrap section for details).
.
NtoL
LINtoSW(LV)
Input Voltage
An Undervoltage Lockout (UVLO) circuit monitors the
input, and can inhibit switching and reset the Soft−start
circuit if there is insufficient voltage for proper regulation.
Depending on the output conditions (voltage option and
loading), the NCV891130 may lose regulation and run in
drop−out mode before reaching the UVLO threshold: refer
to the Minimum Vin calculation tool for details. When the
input voltage drops low enough that the part cannot regulate
because it reaches its maximum duty cycle, the switching
frequency is divided down by up to 4 (down to 500 kHz).
This helps lowering the minimum voltage at which the
regulator loses regulation.
I
threshold, the NCV891130 will stay in PWM mode.
NtoL
Otherwise, the NCV891130 will transition to low power
mode.
It will stay in this low−power mode until the output current
exceeds the I
limit: it then transitions back to PWM
LIN(lim)
An overvoltage monitoring circuit automatically
converter mode. This low−power mode to PWM mode
transition happens within 2 s. The transient response is not
affected by the mode change.
Once the NCV891130 has transitioned to switcher mode,
a 500 s blanking period will occur. After the blanking period,
the NCV891130 will reassess the output current level. If the
terminates switching if the input voltage exceeds V
(see Figure 29), but the NCV891130 can withstand input
voltages up to 45 V.
To avoid skipping switching pulses and entering an
uncontrolled mode of operation, the switching frequency is
reduced by a factor of 2 when the input voltage exceeds the
OVSTP
output current level is below the I
threshold, the
NtoL
V
IN
Frequency Foldback threshold (see Figure 29).
NCV891130 will enter low−Iq mode. If the NCV891130 is
in low−power mode and in normal battery range, it will
Frequency reduction is automatically terminated when the
input voltage drops back below the V Frequency Foldback
threshold. This also helps to limit the power lost in switching
and generating the drive voltage for the Power Switch.
IN
transition to switcher mode when V increases above
IN
V , regardless of the output current. Similarly, if
LINtoSW(HV)
the NCV891130 is in PWM mode and V is higher than
IN
FSW
(MHz)
2
Frequency
folds back
if drop−out
mode
1
3.5
18 20
36
39
45
VIN (V)
Figure 29. NCV891130 Switching Frequency Profile vs. Input Voltage
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11
NCV891130
Soft−Start
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. The recommended inductor
values are 2.2 or 3.3 mH, although higher values are possible.
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower until the output voltage
approaches regulation.
Current Limiting
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 30 shows – for a
2.2 mH inductor – how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV891130 can deliver to a load.
Slope Compensation
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
Figure 30. NCV891130 Load Current Capability with a 2.2 mH Inductor
Short Circuit Protection
The RSTB pin is also pulled low immediately in case of VIN
overvoltage, Thermal shutdown, VIN UVLO or DRV UVLO.
During severe output overloads or short circuits, the
NCV891130 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed.
In more severe short−circuit conditions where the inductor
current is still too high after the switching frequency has fully
folded back, the regulator enters a hiccup mode that further
reduces the power dissipation and protects the system.
Feedback Loop
All components of the feedback loop (output voltage
sensing, error amplifier and compensation) are integrated
inside the NCV891130, and are optimized to ensure
regulation and sufficient phase and gain margin for the
recommended conditions of operation.
Recommended conditions and components:
• Input: car battery
• Output: 3.3 V, 4 V or 5 V, with output current up to
RESET Function
1.2 A
The RSTB pin is pulled low when the output voltage falls
below 7.5% of the nominal regulation level, and floats when
the output is properly regulated. A pull−up resistor tied to the
output is needed to generate a logic high signal on this open
drain pin. The pin can be left unconnected when not used.
When the output voltage drops out of regulation, the pin
• Output capacitor: one to three parallel ceramic 10 mF
capacitors
• Inductor: 2.2 mH to 3.3 mH
With these operating conditions and components, the
open loop transfer function has a phase margin greater than
50°.
goes low after a short noise−filtering delay (t ). It stays low
for a 16 ms delay time after the output goes back to regulation,
filter
simplifying the connection to a micro−controller.
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12
NCV891130
Bootstrap
mode for input voltages below 8 V, and the 4 V version for
input voltages below 6.5 V (see typical characteristics
curves for details).
At the DRV pin an internal regulator provides a ground−
referenced voltage to an external capacitor (C ), to allow
fast recharge of the external bootstrap capacitor (C ) used
to supply power to the power switch gate driver. If the
voltage at the DRV pin goes below the DRV UVLO
Threshold V
DRV
BST
Enable
The NCV891130 is designed to accept either a logic level
signal or battery voltage as an Enable signal. However if
voltages above 40 V are expected, EN should be tied to VIN
through a 10 kW resistor in order to limit the current flowing
into the overvoltage protection of the pin.
EN low induces a shutdown mode which shuts off the
regulator and minimizes its supply current to 9 mA typical by
disabling all functions.
, switching is inhibited and the
DRVSTP
Soft−start circuit is reset, until the DRV pin voltage goes
back up above V
.
DRVSTT
The NCV891130 permanently monitors the bootstrap
capacitor, and always ensures it stays charged no matter
what the operating conditions are. As a result, the additional
charging current for the bootstrap capacitor may prevent the
regulator from entering Low−Iq mode at low input voltage.
Practically, the 5 V output version does not enter Low−Iq
Upon enabling, voltage is established at the DRV pin,
followed by a soft−start of the switching regulator output.
ORDERING INFORMATION
Device
Output
5.0 V
Package
Shipping
NCV891130PD50R2G
NCV891130PD40R2G
NCV891130PD33R2G
4.0 V
SOIC−8 EP
2500 / Tape & Reel
3.3 V
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE E
8
1
DATE 05 OCT 2022
SCALE 1:1
GENERIC
MARKING DIAGRAM*
8
*This information is generic. Please refer to
XXXXXX = Specific Device Code
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
XXXXX
AYWWG
G
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14029D
SOIC−8 EP
PAGE 1 OF 1
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