NCV97200MW33R2G [ONSEMI]
用于安全应用的汽车多输出功率管理集成电路 (PMIC);
| 型号： | NCV97200MW33R2G |
| 厂家： | 
ONSEMI |
| 描述： | 用于安全应用的汽车多输出功率管理集成电路 (PMIC) 集成电源管理电路 |
| 文件： | 总23页 (文件大小：859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Power Management (PMIC) -
Automotive, Multi-Output,
Safety Applications
QFNW20
MW SUFFIX
CASE 484AD
NCV97200
MARKING DIAGRAM
Description
1
The NCV97200 is a 2−output monolithic regulator consisting of
1 buck regulator and 1 boost regulator with supervisory functions
including window voltage monitoring on all outputs and a window
watchdog. This product is ideal for ADAS (Advanced Driver
Assistance Systems) applications and utilizes an independent voltage
reference and an adjustable independent oscillator to realize the
supervisory features.
A 40 V non−synchronous buck regulator converts the battery supply
voltage to a 3.3 V output, and delivers up to 3 A (peak). This output
rail may be used as the low voltage input voltage for the
non−synchronous secondary boost converter. The secondary boost is
fixed and is intended to supply a low current 5.0 V rail for In−Vehicle
Networking circuits (IVN).
97200
XX
ALYWG
G
97200 = Specific Device Code
XX
A
L
= 01 or 33
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Y
W
G
(Note: Microdot may be in either location)
All internal MOSFETs are N−channel devices, and a bootstrap
circuit is used to drive the buck high−side MOSFET. Both SMPS
outputs use peak current mode control with internal slope
compensation. The IC incorporates an internal regulator that supplies
charge to the low−voltage gate drivers.
SAFETY DESIGN – ASIL B
ASIL B Product developed in compliance with
ISO 26262 for which a complete safety
package is available.
The NCV97200 is a functional safety solution that reduces the time
required to develop safety systems that comply with the International
Standards Organization (ISO) 26262. The device includes a range of
integrated safety features such as dedicated feedback references,
output voltage monitoring, and window watchdog.
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 21 of this data sheet.
Features
Typical Applications
1 Enabled Buck Converter
Safety Applications
1 Boost Converter for IVN Supply
Wide Input of 4.1 to 40 V with Undervoltage Lockout (UVLO)
Fixed Frequency Operation at 2 MHz
Window Watchdog with Independent References
Cycle−by−cycle Current Limit Protection
External Frequency Synchronization
ADAS (Advanced Driver Assistance
Systems)
Body Electronics
Telematics
Pseudo−random Spread Spectrum for Improved EMI
Option for Switcher Shutdown upon Watchdog Fault
(controlled by part number)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and Halide Free
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
July, 2023 − Rev. 5
NCV97200/D
NCV97200
LINEAR
REGULATOR
VDRV1
BST1
SW1
VBAT
REGULATOR 1
3.3 VOLT
STEP DOWN
COMP1
VOUT1
RESET
LOGIC
OUTPUT
MONITOR
RSTB1
WDI
WINDOW
WATCHDOG
WATCHDOG
OSCILLATOR
WDT
EN
SW2
REGULATOR 2
5.0 VOLT
GND2
VOUT2
BOOST
RSTB2
OUTPUT
MONITOR
EN DELAY
TIMER
VOUT_PD
TSD
VIN_UVLO
VIN_OV
FAULT
LOGIC
VOLTAGE
MONITOR
RSTB_VM
FB_VM
SYNCO
VBAT
MAIN
OSCILLATOR
SPREAD
SPECTRUM
SYNCI
GND1
Figure 1. NCV97200 Block Diagram
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2
NCV97200
TYPICAL APPLICATION
L
1
V
V
OUT1
D
1
C
OUT1
L
2
D
2
OUT2
C
BST
C
OUT2
C
DRV
V
BAT
20
SW1
16
BST1 VDRV1 SW2
NCV97200
GND2
C
IN
VBAT
1
VOUT2
15
EN
VOUT1
FB_VM
RSTB2
SYNCI
SYNCO
R
RSTB2
VOUTPD
5
WDI
11
To
WDT COMP1 GND1 RSTB_VM RSTB1
10
mController
6
R
PD
R
RSTB1
C
WDT
R
COMP
R
RSTBVM
C
COMP
Figure 2. NCV97200 Typical Application
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3
NCV97200
Table 1. MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 40
45
Unit
V
Min/Max Voltage VBAT
Max Voltage VBAT to SW1 and VBAT to GND − peak voltage during load dump
Min/Max Voltage SW1
V
−0.7 to 40
−3.0
V
Min Voltage SW1, SW2 − 20 ns
V
Min/Max Voltage BST1, EN
−0.3 to 40
−0.3 to 7.2
−0.3 to 6
3.6
V
Min/Max Voltage SW2
V
Min/Max Voltage on WDI, SYNCI, SYNCO, VOUT2, RSTB1, RSTB2, RSTB_VM, VOUT_PD
Max Voltage BST1 to SW1
V
V
Min/Max Voltage FB_VM, VDRV1, COMP1, WDT, VOUT1
Thermal Resistance, 4x4 QFN Junction–to–Ambient (Note 1)
Storage Temperature range
−0.3 to 3.6
39
V
R
C/W
C
C
kV
JA
J
−55 to +150
−40 to +150
2.0
Operating Junction Temperature Range
ESD withstand Voltage (Human Body Model)
Moisture Sensitivity
T
V
ESD
MSL
Level 1
260
Peak Reflow Soldering Temperature
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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4
NCV97200
Table 2. PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
VBAT
EN
Description
1
2
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
High−voltage (battery), TTL−compatible, master enable signal. Grounding this input stops all outputs and
reduces Iq to a minimum (shutdown mode).
3
SYNCI
Synchronization input. Connecting an external clock to the SYNCI pin synchronizes switching to the rising
edge of the SYNCI voltage. If unused, the SYNCI pin should be grounded.
4
5
6
SYNCO
VOUT_PD
WDT
Synchronization output pin. If unused, the SYNCO pin should have no connection.
Internal pull−down circuit − active during Enable delay time. Connect to GND when not used.
Watchdog delay programming. Connect a capacitor between this pin and ground to adjust the watchdog
window time.
7
8
9
COMP1
GND1
Output of the error amplifier for switcher 1
Ground reference for the IC.
RSTB_VM
External voltage monitor reset output with adjustable delay. Goes low when the FB_VM for the external
supply is out of regulation. If unused, the RSTB_VM pin should have no connection.
10
RSTB1
Switcher 1 voltage monitor reset output with adjustable delay. Goes low when the output is out of regulation
and when a watchdog pulse is not received from the microcontroller. If unused, the RSTB1 pin should have
no connection.
11
12
13
WDI
CMOS compatible Watchdog pulse input from a CPU. To be valid, the time between rising edges of this
signal must be between the watchdog window time.
RSTB2
FB_VM
Switcher 2 voltage monitor reset output with adjustable delay. Goes low when the output is out of regulation.
If unused, the RSTB2 pin should have no connection.
Input for the external voltage monitor. Connect to external voltage reference through resistor divider.
If unused, the FB_VM pin should be grounded.
14
15
16
17
18
VOUT1
VOUT2
GND2
SW2
Output voltage sensing for switcher 1.
Output voltage sensing for switcher 2.
Ground connection for the source of the low−side switch of switcher 2.
Switching node of the switcher 2 boost regulator. Connect the output inductor to this pin.
VDRV1
Internal supply voltage for driving the low−voltage internal switch. Connect a 0.1 mF to 1.0 mF capacitor for
noise filtering purposes.
19
20
BST1
SW1
EP
Bootstrap input provides drive voltage higher than VBAT to the N−channel Power Switch for optimum switch
DS(on)
R
and highest efficiency.
Switching node of the switcher 1 buck regulator. Connect the output inductor and cathode of the freewheel-
ing diode to this pin.
Exposed
Pad
Must be connected to GND1 (electrical ground) and to a low thermal resistance path to the ambient tem-
perature environment.
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NCV97200
Table 3. ELECTRICAL CHARACTERISTICS
BAT
(V
= 4.5 V to 28 V, EN = 5 V, BSTx = SWx + 3.0 V, C
= 0.1 mF. Min/Max values are valid for the temperature range
DRV1
−40C T 150C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
QUIESCENT CURRENT
Symbol
Conditions
Min
Typ
Max
Unit
Quiescent Current, shutdown
UNDERVOLTAGE LOCKOUT – VBAT (UVLO)
VBAT UVLO Start Threshold
VBAT UVLO Stop Threshold
VBAT UVLO Hysteresis
ENABLE
I
V
BAT
= 13.2 V, T = 25C, V = 0 V
−
3
10
mA
qSD
J
EN
V
V
V
BAT
rising
falling
4.45
3.7
−
−
−
4.85
4.1
−
V
V
V
UV1ST
UV1SP
UV1HY
V
BAT
V
0.75
Delay Time
t
13.6
−
16
−
18.4
0.8
−
ms
V
ENDLY
Logic Low
V
ENLO
Logic High
V
2.0
−
−
V
ENHI
Enable Pin Input Current
Disable Response Time
I
V
= 5 V
15
2
20
mA
ms
EN
EN
t
Time EN Voltage must be < V
in
ENLO
−
10
DISABL
order to force restart
OUTPUT VOLTAGE
Switcher 1 Output
V
V
3.23
4.9
3.3
5.0
3.37
5.1
V
V
OUT1
Switcher 2 Output
OUT2
ERROR AMPLIFIER – SWITCHER 1
Transconductance
V
= 1.1 V
mmho
COMP
g
4.5 V < V
< 18 V
0.6
0.35
1.0
0.55
1.4
0.75
m
BAT
BAT
g
20 V < V
< 28 V
m(HV)
Output Resistance
R
−
1.4
−
MW
mA
OUT
SOURCE
COMP Source Current Limit
I
V
V
= 2.8 V, V
= 1.1 V
OUT1
COMP
4.5 V < V
< 18 V
50
25
75
40
100
55
BAT
BAT
20 V < V
< 28 V
COMP Sink Current Limit
I
= 3.8 V, V
= 1.1 V
< 18 V
< 28 V
mA
SINK
OUT1
COMP
4.5 V < V
50
25
75
40
100
55
BAT
BAT
20 V < V
Minimum COMP Voltage
Maximum COMP Voltage
OSCILLATOR
V
V
OUT1
V
OUT1
= 3.8 V
= 2.8 V
−
0.15
1.6
0.3
V
V
CMPMIN
V
1.3
−
CMPMAX
Base Switching Frequency − Switcher 1
f
4.5 < V
< 18 V
1.8
2.0
2.2
MHz
SW1
BAT
(see Spread Spectrum Section)
Switching Frequency − Switcher 1
Base Switching Frequency − Switcher 2
SYNCHRONIZATION INPUT (SYNCI)
SYNCI Pin Input Current
f
20 V < V < 28 V
0.9
1.8
1.0
2.0
1.1
2.2
MHz
MHz
SW1(HV)
BAT
f
(see Spread Spectrum Section)
SW2
I
V
SYNCI
= 5.0 V
30
2.0
−
50
−
70
−
mA
V
SYNCI
SYNCI Input High Input Voltage
SYNCI Input Low Input Voltage
SYNCI High Pulse Width
V
SYNCIH
V
−
0.8
−
V
SYNCIL
SYNCIH
t
V
SYNCI
> V
40
40
1.8
−
−
ns
SYNCIH
SYNCI Low Pulse Width
t
V
SYNCI
< V
−
−
ns
SYNCIL
SYNCIL
External Synchronization Frequency
Master Reassertion Time
f
−
2.6
−
MHz
ns
SYNCI
t
Time between last synchronized SW
rising edge and first unsynchronized
SW rising edge.
650
SYNCIMR
SYNCHRONIZATION OUTPUT (SYNCO)
SYNCO High Voltage
V
SYNCO load current = −1 mA
VDRV
−0.2 V
−
VDRV
V
SYNCO,H
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NCV97200
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V = 4.5 V to 28 V, EN = 5 V, BSTx = SWx + 3.0 V, C
= 0.1 mF. Min/Max values are valid for the temperature range
DRV1
BAT
−40C T 150C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
SYNCHRONIZATION OUTPUT (SYNCO)
SYNCO Low Voltage
SYNCO Duty Cycle
Symbol
Conditions
Min
Typ
Max
Unit
V
SYNCO load current = 1 mA
0
40
−
−
50
8
0.2
60
−
V
%
ns
ns
SYNCO,L
D
SYNCO
SYNCO Rise Time
t
SYNCO load capacitance = 40 pF
SYNCO load capacitance = 40 pF
SYNCO,R
SYNCO Fall Time
t
−
5
−
SYNCO,F
Phase
f
Rising edge lag with respect to SW1
rising edge
−
140
−
SO−SW1
VBAT OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
V
V
rising
falling
37
34
−
−
−
40
−
V
V
V
OV1SP
OV1ST
OV1HY
BAT
Overvoltage Start Threshold
V
V
BAT
Overvoltage Hysteresis
V
0.6
2.7
VBAT FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
V
rising
falling
18.4
18
−
−
20
V
V
FL1U
FL1D
BAT
BAT
V
V
19.8
Frequency Foldback Hysteresis
SOFT−START
V
FL1HY
0.2
0.3
0.4
Soft−Start Completion Time
t
t
0.8
1.6
1.4
2.8
2.0
4.0
ms
SS1
SS2
SLOPE COMPENSATION
Ramp Slope – Switcher 1
S
4.5 < V
< 18 V
BAT
1.8
0.8
−
−
3.4
1.6
A/ms
A/ms
ramp1
BAT
(With respect to switch current)
S
20 V < V
< 28 V
ramp1(HV)
Ramp Slope – Switcher 2
POWER SWITCH − SWITCHER 1
ON Resistance
S
ramp2
0.76
1.1
1.44
R
V
= V
+ 3.0 V, I = 500 mA
SW1
−
−
−
−
360
10
mW
mA
ns
DS1ON
BST1
SW1
Leakage current VBAT to SW1
Minimum ON Time
I
V
= 0 V, V
= 0 V, V
= 18 V
LKSW1
EN
SW1
BAT
t
Measured at SW1 pin
Measured at SW1 pin
45
30
−
70
ON1MIN
Minimum OFF Time
t
50
70
ns
OFF1MIN
POWER SWITCH − SWITCHER 2
ON Resistance
R
I
= 100 mA
= 5.0 V, V
−
−
−
−
1.0
5
W
mA
ns
ns
DS2ON
SW2
Switch Leakage Current
Minimum ON Time
I
V
EN
= 0 V, V
= 18 V
BAT
LKSW2
SW2
t
Measured at SW2 pin
Measured at SW2 pin
65
35
85
55
100
75
ON2MIN
Minimum OFF Time
t
OFF2MIN
PEAK CURRENT LIMITS
Current Limit Threshold – Switcher 1
Current Limit Threshold – Switcher 2
I
I
3.9
4.4
1.2
4.9
A
A
LIM1
0.96
1.44
LIM2
SHORT CIRCUIT FREQUENCY FOLDBACK – SWITCHER 1
Lowest Foldback Frequency
Lowest Foldback Frequency – High V
f
V
= 0 V, 4.5 V < V
< 18 V
< 28 V
450
225
550
275
650
325
kHz
SW1AF
OUT1
OUT1
BAT
BAT
f
V = 0 V, 20 V < V
IN
SW1AFHV
HICCUP MODE
Hiccup Frequency
f
f
V
= 0 V
24
24
−
32
32
40
40
−
kHz
kHz
ms
SW1HIC
OUT1
SW1 pin shorted to ground or VOUT1
SW2 pin connected to +3.3 V through
20 W. Zero volts at the VOUT2 pin.
SW2HIC
Switching Reactivation Delay
SW2
SW2 pin shorted to VOUT1
1.9
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NCV97200
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V = 4.5 V to 28 V, EN = 5 V, BSTx = SWx + 3.0 V, C
= 0.1 mF. Min/Max values are valid for the temperature range
DRV1
BAT
−40C T 150C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
WINDOW WATCHDOG
Symbol
Conditions
Min
Typ
Max
Unit
Watchdog Oscillator Frequency
f
C
= 1000 pF
= 100 pF
8.2
77
10.6
100
13.0
122
kHz
ms
WD
WDT
WDT
C
First Watchdog Timeout
t
Watchdog timeout after rising edge at
RSTB1
WD_timeout
C
= 1000 pF
2300
2070
240
2840
−
300
−
3700
4090
385
WDT
800 pF < C
< 1200 pF
WDT
C
= 100 pF
WDT
80 pF < C
< 120 pF
221
430
WDT
Watchdog Window Time
t
C
= 1000 pF
WDT
150
138
15.9
14.7
189
−
20
−
250
273
27
ms
ms
WD
800 pF < C
< 1200 pF
WDT
C
= 100 pF
WDT
80 pF < C
< 120 pF
28.7
WDT
Watchdog Closed Window Time
WDI Pulse Duration
t
−
t
/4
−
−
WD_CLS
WD
t
Number of Oscillator periods
(WDT pin) the WDI input must remain
high or low
3
−
WDT
cycles
WDImin
Watchdog Input WDI Threshold Voltage
V
V
increasing
WD
WI
−
0.8
150
−
−
−
2.0
−
500
V
V
mV
WDH
WDL
V
V
decreasing
V
WD_HYS
Watchdog Input WDI Current
RESET
I
V
WD
= 5 V
30
50
70
mA
WDI
Low Voltage Reset Threshold – Switcher 1
V
V
decreasing
increasing
2.97
3.04
3.05
3.12
3.14
3.20
V
V
V
V
V
V
UV1FAL
UV1RIS
OUT1
OUT1
V
V
High Voltage Reset Threshold – Switcher 1
Low Voltage Reset Threshold – Switcher 2
High Voltage Reset Threshold – Switcher 2
V
V
decreasing
increasing
3.40
3.47
3.48
3.55
3.56
3.63
OV1FAL
OUT1
V
V
OV1RIS
UV2FAL
OUT1
V
V
V
decreasing
increasing
4.50
4.60
4.63
4.73
4.75
4.85
OUT2
V
UV2RIS
OUT2
V
V
decreasing
increasing
5.15
5.25
5.28
5.38
5.40
5.50
OV2FAL
OUT2
V
V
OV2RIS
OUT2
Low Voltage Reset Threshold – External
Supply
V
FB_VM decreasing
FB_VM increasing
0.720 0.740 0.760
0.736 0.756 0.776
UVextFAL
UVextRIS
V
High Voltage Reset Threshold – External
Supply
V
FB_VM decreasing
FB_VM increasing
0.824 0.844 0.864
0.840 0.860 0.880
OVextFAL
V
OVextRIS
RES_HYS
RES_FILT
Reset Hysteresis (ratio of VOUTx)
K
0.5
5
2
−
%
Noise−Filtering Delay
t
−
25
ms
Reset Delay Time
Time RSTB1 remains low after output voltage
enters the monitor window.
t
I
= 1 mA
= 500 mA
= 100 mA
−
4.0
19
1.0
5.0
24
−
6.0
29
ms
ms
ms
RESET
RSTBx
I
I
RSTBx
RSTBx
Reset Output Low level
BOOTSTRAP VOLTAGE SUPPLY
Output Voltage
V
I
= 1 mA
−
−
0.4
V
RESL
RSTBx
V
DRV1
3.1
2.7
3.3
2.875
2.75
3.5
V
V
V
V
DRV1
V
DRV1
POR Start Threshold
POR Stop Threshold
V
V
3.05
2.95
DRV1ST
DRV1SP
2.55
THERMAL SHUTDOWN
Thermal Shutdown Activation Temperature
Hysteresis
T
150
5
−
−
190
20
C
C
SD
T
HYS
VOUT_PD
Pulldown Resistance
R
During Enable Delay Time
5
16
40
W
PD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCV97200
TYPICAL CHARACTERISTICS − (DEMOBOARD DATA)
VBAT = 13.2 V
VBAT = 13.2 V
No Load
Figure 3. Shutdown VBAT Current vs.
Temperature
Figure 4. Operating VBAT Current vs.
Temperature
25C
25C
No Load
Figure 5. Shutdown VBAT Current vs. VBAT
Voltage
Figure 6. Operating VBAT Current vs. VBAT
Voltage
VBAT = 13.2 V
VBAT = 13.2 V
Figure 7. VDRV1 Voltage vs. Temperature
Figure 8. Switcher 1 Minimum ON Time vs.
Temperature
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NCV97200
TYPICAL CHARACTERISTICS − (DEMOBOARD DATA)
VBAT = 13.2 V
VBAT = 13.2 V
Figure 9. Switcher 1 Minimum OFF Time vs.
Temperature
Figure 10. Switcher 2 Minimum ON Time vs.
Temperature
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
37V
28V
20V
18V
13.2V
5.0V
VBAT = 13.2 V
−40 −20
0
20 40 60 80 100 120 140 160
Temperature (degC)
Figure 11. Switcher 2 Minimum OFF Time vs.
Temperature
Figure 12. Switcher 1 Load Current Limit vs.
Temperature
VBAT = 13.2 V
No Load
VBAT = 13.2 V
Figure 13. Switcher 2 Load Current Limit vs.
Temperature
Figure 14. Switcher 1 Output Voltage vs.
Temperature
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NCV97200
TYPICAL CHARACTERISTICS − (DEMOBOARD DATA)
25C
VBAT = 13.2 V
No Load
Figure 15. Switcher 2 Output Voltage vs.
Temperature
Figure 16. Switcher 1 Output Voltage vs. VBAT
Voltage
VBAT = 13.2 V
3 A Load
VBAT = 13.2 V
3 A Load
Figure 17. Switcher 1 Risetime vs.
Temperature
Figure 18. Switcher 1 Falltime vs. Temperature
VBAT = 13.2 V
400 mA Load
VBAT = 13.2 V
400 mA Load
Figure 19. Switcher 2 Risetime vs.
Temperature
Figure 20. Switcher 2 Falltime vs. Temperature
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11
NCV97200
TYPICAL CHARACTERISTICS − (DEMOBOARD DATA)
VBAT = 13.2 V
40 mA Load
Average Frequency
VBAT = 13.2 V
210 mA Load
Average Frequency
Figure 21. Switcher 1 Frequency vs.
Temperature
Figure 22. Switcher 2 Frequency vs.
Temperature
VBAT = 13.2 V
VBAT = 4.5 V
Figure 23. Switcher 1 Efficiency vs. Load,
4.5 V VBAT
Figure 24. Switcher 1 Efficiency vs. Load,
13.2 V VBAT
VBAT = 13.2 V
VBAT = 28 V
Figure 25. Switcher 1 Efficiency vs. Load,
28 V VBAT
Figure 26. Switcher 2 Efficiency vs. Load
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12
NCV97200
APPLICATION INFORMATION
General Description
The NCV97200 consists of one 2 MHz battery−connected 2.5 A switcher (switcher 1) and a downstream low−current boost
converter (switcher 2).
VDRV
VDRV1
BST1
Switcher 1
Non−synchronous buck
VDD
REGULATOR 1
3V3
STEP DOWN
SW1
VBAT
COMP1
RSTB1
RSTB2
RSTB1
VOUT1
SW2
REGULATOR 2
5V0
EN
Switcher 2
Non−synchronous boost
BOOST
VOUT2
GND1
RSTB2
GND2
VOUT_PD
EN DELAY
TIMER
RSTBVM
RSTB1
RSTB_VM
WATCHDOG
OSCILLATOR
WDT
WDI
RESET
LOGIC
WINDOW
WATCHDOG
TSD
VOLTAGE
FB_VM
MONITORING
VIN_UVLO
VIN_OV
FAULT
LOGIC
VOUT1 VOUT2
PSR
SPREAD
SPECTRUM
SYNCI
OSC
SYNCO
Figure 27. NCV97200 Simplified Block Diagram
Input Voltage
Above 40 V (max) an over−voltage shutdown (OVSD)
circuit inhibits all switching and allows the NCV97200 to
survive a 45 V load dump condition. Normal operation
resumes when VBAT decreases below 34 V (min)
The main supply for the NCV97200 is the VBAT pin,
which must always be connected to a voltage source
between 4.1 V and 37 V.
Below 4.1 V (max) an under−voltage lockout (UVLO)
circuit inhibits all switching and resets the soft−start
circuits.
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13
NCV97200
FSW
(MHz)
switching is inhibited and the outputs do not power up. Once
the delay time is complete, switching begins and the
regulators power up with a soft start.
2
Output Discharge Device
In addition to the delay timer on the EN signal, an optional
active pull down is available to discharge the outputs during
the enable delay time. When not used, the VOUT_PD pin
should be connected to GND. Please refer to the following
schematic:
1
VIN (V)
45
3.7 4.85
18 20
34
40
VOUT 1
Regulator
Figure 28. Input Voltage Range
1
SW1
Enable and Soft−Start
The NCV97200 can be completely disabled (shutdown
mode) by connecting the enable (EN) pin to GND. As a
result, both outputs are stopped and the internal current
consumption drops below 10 mA.
VOUT 2
Regulator
2
EN
SW2
Rlim
EN Delay
Timer
The EN pin is designed to accept either a logic−level
signal or the battery voltage. If connecting EN to battery, and
battery voltage could exceed 40 V, make the connection
through a 10 k resistor. Upon receiving an input greater than
2 V, the EN pin allows switcher 1 to begin soft−start and
ramp up to 3.3 V (typically in 1.4 ms). After the soft−start of
VOUT1 is complete, switcher 2 (the boost regulator) begins
its soft−start and ramps up to 5.0 V. Switcher 2 does not have
its own enable input pin and is linked to the master enable
input.
VOUT _PD
Internal Circuitry
Figure 30. VOUT_PD Internal Circuitry
The diagram below shows the startup sequence when EN
is activated:
To use the active discharge, connect VOUT2 through a
current limiting resistor to the VOUT_PD pin. The current
limiting resistor, Rlim, should be in the range of 10 W. Upon
enabling and during the enable delay time, the internal
discharge device will be activated until the regulators are
turned on.
Oscillator
Both switching regulators in the NCV97200 share the
same oscillator, which, by default, operates at 2.0 MHz with
pseudo−random spread spectrum (spread spectrum
described in next section). The switching frequency can be
adjusted from 2.0 MHz to 2.6 MHz using the external
synchronization input pin, SYNCI. Manually adjusting the
switching frequency using the SYNCI pin will adjust the
switching frequency for both regulators since they share a
common oscillator.
There are 2 types of frequency adjustments that can occur
with the NCV97200: maximum duty cycle foldback and
high voltage frequency foldback. These frequency foldback
mechanisms take place outside the main oscillator in logic
and only affect the regulators meeting the criteria. The main
oscillator frequency remains unchanged.
Figure 29. Startup Sequence
Enable Delay Time
The switching outputs of the NCV97200 are delayed for
16 ms after receiving a valid high signal on the EN pin.
When a valid EN signal is received by the IC, the internal
rails and circuitry power up. During the enable delay time,
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14
NCV97200
Maximum duty cycle foldback takes place at low input
Table 4. PSEUDO−RANDOM FREQUENCY BINS
voltages where the conversion ratio wants to be larger than
the minimum off time allows. Each switch cycle, logic
outside the oscillator allows either a maximum duty cycle up
to 90% (typical) or 100% duty cycle operation by skipping
an off−time. The oscillator is allowed to skip up to three
consecutive off−times in this manner. The lowest effective
frequency is 500 kHz at typical battery voltages. Once the
input voltage increases or the load decreases, 2 MHz
operation will resume.
At high input voltages (above 20 V), the oscillator folds
back to 1 MHz operation to properly maintain the output
voltage when the conversion ratio needs to be lower than the
minimum on time allows at 2 MHz operation. If maximum
duty cycle foldback also takes place above 20 V input, the
lowest effective frequency is still 500 kHz. Once the input
voltage drops back below 18 V, 2 MHz operation will
resume.
Pseudo Random Digital Output
Switching Frequency
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2.00 MHz
2.04 MHz
2.08 MHz
2.12 MHz
2.16 MHz
2.20 MHz
2.24 MHz
2.28 MHz
2.32 MHz
2.36 MHz
2.40 MHz
2.44 MHz
2.48 MHz
2.52 MHz
2.56 MHz
2.60 MHz
Spread Spectrum
In SMPS devices, switching translates to higher
efficiency and switching at high frequency can reduce the
size of external components. Unfortunately, switching also
leads to a higher EMI profile. We can greatly reduce some
of the peak radiated emissions with some spread spectrum
techniques. Spread spectrum is a method used to reduce the
peak electromagnetic emissions of a switching regulator.
The period of each switch cycle will change inversely to
the switching frequency but the duty cycle will remain
constant to properly maintain the output.
EMI and Input Filter
In addition to spread spectrum, an input filter is
recommended to further reduce emissions due to switching
heavy loads.
Time Domain
Frequency Domain
Unmodulated
Lfilt = 1.0 mH
To Battery Input
To VBAT pin on NCV97200
V
V
NCV97200
Input Caps
Cfilt = 0.1 mF
t
fc 3fc 5fc 7fc 9fc
Modulated
Figure 32. LC Input Filter
When connecting the battery voltage to other circuits on
the PCB, be sure to connect them to the battery input side,
not the NCV97200 side, of the LC filter. This will give the
best possible noise performance.
t
fc 3fc 5fc 7fc 9fc
Figure 31. Spread Spectrum Comparison
Current Limit and Short Circuit Frequency Foldback
Each switching regulator has a peak current limit to
protect the inductor and downstream components in case of
a short circuit or transient event. Due to the ripple current
through the inductor, the maximum dc output current of each
converter is lower than the peak current limit. If the peak
current limit is reached during the switch cycle, the switch
turns off for the remainder of the cycle and turns on again at
the start of the next cycle.
The NCV97200 includes built−in spread spectrum for
reduced peak radiated emissions. This IC uses a pseudo−
random generator to set the oscillator frequency to one of 16
discrete frequency bins (shown in the table, below). Each
digital bin represents a shift in frequency by 40 kHz over the
range 2.0 MHz to 2.6 MHz. Over time, each bin is used an
equal number of times to ensure an even spread of the
spectrum. This reduces the peak energy at the fundamental
frequency, 2.0 MHz, and spreads it into a wider band.
During severe output overloads or short circuit
conditions, the primary regulator (switcher 1) automatically
reduces its switching frequency and enters analog foldback.
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15
NCV97200
This creates a duty cycle small enough to limit the power in
The SYNCO falling edge precedes switchnode 1 rising
edge by approximately 100 ns, and SYNCO rises half a
switching period later. Connecting the SYNCI pin of
another NCV97200 to SYNCO causes both switchers to
switch at the same frequency, but out of phase. If a SYNCI
signal is present, or under transient conditions such as
startup and high VBAT voltage, the SYNCO output is held
low. When SYNCO is active, the frequency is modified by
the same Spread Spectrum utilized by switchers 1 and 2.
the output components while maintaining the ability to
automatically reestablish the output voltage if the overload
is removed. This foldback changes the main oscillator and
will apply to both regulators. Once the overload or short
circuit is removed, 2 MHz operation will resume.
If the output current is still too high, the regulators,
individually, automatically enter an auto−recovery burst
mode (hiccup mode) to self−protect and further reduce
dissipated power in the output components. When a
short−circuit is detected, the switcher disables its output,
remains off for the hiccup time, and then goes through the
power−on reset procedure. If the short has been removed,
the output re−enables and operates normally. If the short is
still present, the cycle begins again until the short is
removed. Hiccup mode is continuous at a typical rate of
32 kHz until the short is removed.
Reset & Delay
When the voltage at the VOUT1 pin is not between the
Switcher 1 high−voltage and low−voltage reset thresholds,
the open−drain RSTB1 output is asserted (pulled low). Also,
if VOUT1 voltage is greater than approximately 2 V, then an
EN pin low, or a Thermal Shutdown, VBAT over−or
under−voltage, or Watchdog Timer fault will cause the
RSTB1 output to be asserted.
When the voltage at the VOUT2 pin is not between the
Switcher 2 high−voltage and low−voltage reset thresholds,
the open−drain RSTB2 output is asserted. RSTB2 is also
asserted in response to VBAT and TSD faults. When the
voltage at the FB_VM pin is not between the External
Supply high−voltage and low−voltage reset thresholds, the
open−drain RSTB_VM output is asserted.
Each of the RSTB signals can either be used as a reset with
delay or as a power good (no delay). The delay is determined
by the current into the RSTBx pin, set by a resistor, show in
External Frequency Synchronization
The NCV97200 can be synchronized to an external clock
signal. If the IC does not have its switching frequency
controlled by the SYNCI input, it operates normally at the
default switching frequency, typically 2.0 MHz with spread
spectrum.
The signal at the SYNCI pin is used as a synchronization
input during normal operation and is ignored during startup,
shutdown, overvoltage, and other transient conditions.
When the switching frequency is controlled by the SYNCI
input, synchronization starts within 2 ms of soft start
completion. Please keep in mind that spread spectrum will
be disabled when the oscillator is being synchronized with
an external clock.
Figure 34, below.
VOUT1
RRSTBx
A rising edge on the SYNCI pin causes the current
oscillator period to end and a new period to start. The
switchnode of switcher 1 goes high 90 ns after a SYNCI
rising edge, and the switchnode of switcher 2 goes low
350 ns after a SYNCI rising edge. If another rising edge does
not arrive at the SYNCI pin within the Master Reassertion
time, the NCV97200 resumes with the default switching
frequency. This allows for uninterrupted operation in the
event that the external clock is turned off.
RSTBx
RSTx
Figure 34. Reset Delay Circuit
Use the following equation to determine the ideal reset
delay time using currents less than 500 mA:
2475
IRSTBx
tdelay
+
SYNCI
SW1
where:
t
: ideal reset delay time [ms]
delay
I
: current into the RSTBx pin [mA]
RSTBx
SW2
Using I
= 1 mA removes the delay and allows the reset
RSTBx
time
to function as a “power good” pin.
Figure 33. External Synchronization Timing
The RSTBx resistor is commonly tied to VOUT1. Typical
delay times for a 3.3 V pull−up can be achieved with the
following resistor values:
Output SYNCO
The SYNCO output produces a square wave derived from
the VDRV1 output that is suitable for driving the
synchronization inputs of other switching converters.
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16
NCV97200
Watchdog
Table 5. RESET DELAY TIMES
The NCV97200 contains a Window Watchdog Timer
function, which requires the microcontroller to send a
correctly−timed pulse to the WDI pin in order to
demonstrate proper functionality. The watchdog oscillator
runs independently of the switching oscillator. Window
watchdog is active unless RSTB1 is asserted (low) due to
VOUT1 out of regulation, or global faults (VBAT under− or
over−voltage or thermal shutdown).
R
(kW)
t
(ms)
DLY
RSTBx
3.3
0
6.6
10
15
20
25
33
5
7.5
11.3
15.0
18.8
24.8
Any Watchdog Timer fault (t
, t
, t
,
WD_timeout WD_CLS WD
or WDI always high) causes RSTB1 to be pulled low for the
duration of the Reset Delay Time plus 3 WDT cycles (typ).
Additionally, depending on the version of NCV97200,
Switchers 1 and 2 will be disabled (see Table 6).
Functional Safety
The NCV97200 has been developed according to
ISO−26262 targeting ASIL B/C applications. With this in
mind, we’ve specifically included the following items to make
this power supply compatible with your safety application:
1. There are 2 independent bandgaps for the internal
reference voltages. The primary bandgap is used
for the internal supplies and the regulation of each
power supply output. The second bandgap is
Watchdog timeout mode with long timing (t
)
WD_timeout
begins at the rising edge of RSTB1. If a rising edge is not
received at the WDI pin during t , it is a fault.
WD_timeout
When a rising edge is received at the WDI pin during
, both a closed (short) window time (t
t
)
WD_CLS
WD_timeout
and an open (longer) window time (t ) are started. If a
WD
second rising edge is received during t
, it is a fault.
WD_CLS
primarily used as a safety mechanism as a reference
to which the RSTBx circuits are compared.
To avoid assertion of RSTB1, the second rising edge must
appear before the end of t (but not during t ). If
WD
WD_CLS
2. Each output voltage has a separate window voltage
monitoring circuit that’s comparing the output
feedback signal to the internal reference generated by
the second bandgap. Each output voltage is monitored
for overvoltage and undervoltage conditions.
the second rising edge is not received before the end of t
it is a fault.
,
WD
If the WDI pin voltage remains high for the duration of the
active timeout or window period (t or t ), it is
WD_timeout
WD
a fault. WDI already high when RSTB1 rises is treated as a
WDI pulse − immediately starting the closed and open
Please see “Reset & Delay” for more details.
3. A window watchdog is included to monitor an
incoming watchdog signal from a microcontroller.
This behavior is detailed in the “Watchdog” section.
window times (t
and t ).
WD_CLS
WD
Table 6. WATCHDOG FAULTS
Part Number
Type of Watchdog Fault
Closed window (t
st
1
timeout (t
)
)
Open window (t )
WD
WDI Stays High
WD_timeout
WD_CLS
NCV97200MW01
NCV97200MW33
RSTB1 goes low for the Reset Delay Time (t
), but both switchers remain active
RESET
RSTB1 goes low, and both switchers are disabled for the Enable Delay Time (t
start. After VOUT1 reaches regulation, RSTB1 remains low for the Reset Delay Time (t
) − after which they soft-
RESET
DISABL
)
RSTB1
WDI
1
2
1
3
4
5
6
7
tWD_CLS
tWD
tWD_CLS
tWD_CLS
tRSTB1
tWD_timeout
tRSTB1 tWD_timeout
tWD
tWD
Figure 35. Watchdog Function and Timing
1. Rising edge on RSTB1 triggers the start of watchdog timeout mode.
2. No watchdog trigger within the watchdog timeout time t . RSTB1 pulled low.
WD_timeout
3. Window trigger mode active after rising edge on the WDI pin.
4. First successful watchdog trigger within the window time t
.
WD
5. Watchdog trigger failed, no rising edge at WDI pin within window time t . RSTB1 pulled low.
WD
6. Watchdog trigger failed, rising edge at WDI pin within boundary time t . RSTB1 pulled low.
WD_CLS
7. Watchdog trigger failed, signal at WDI pin permanent high. RSTB1 pulled low.
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NCV97200
Choosing the best capacitor for C
finding the value that sets the minimum t
to the maximum processor boot−up time t
requires first
than 2 V). If either of these 2 criteria are not met, the
NCV97200 will resume normal operation. Further, if the
WDT pin is held low while the SYNCI is not held high, a
fault will be reported on RSTB1.
WDT
equal
WD_timeout
:
BOOT
C
(pF) 0.4366 x t
(ms) +7 pF.
WDTmin
BOOT
Then choose the lowest standard value capacitor C
satisfying the following equation:
WDTstd
SWITCHER 1
The primary dc−dc output for the NCV97200 is 3.3 V, set
by an internal resistor divider. This buck regulator is
non−synchronous and requires an external low−side
freewheeling diode to operate.
C
C
/ (100% − tol) [tol = % tolerance
WDTstd
WDTmin
& temperature variation of the chosen capacitor]
The resulting typical t interval is:
WD_timeout
t
(ms, typ) = 2.87 x C
(pF) + 20
WD_timeout
WDTstd
and the resulting t
temperature & tolerance effects is:
range including NCV97200
WD_timeout
VBAT
t
(ms, min) = 2.29 x (100% − tol) x C
WD_timeout
WDTstd
(pF) + 16
t
(ms, max) = 3.63 x (100% + tol) x C
WD_timeout
WDTstd
Gate
(pF) + 26
Driver
SW1
VOUT1
To be valid, the period of the signal the processor applies
to the WDI pin (T
) must be: min t
/15
Bandgap 1
WDI
WD_timeout
T
WDI
max t
/60.
WD_timeout
Error
Amplifier
tolerance
tolerance
Bandgap 2
WDI
Reset
Comparator
t
Watchdog
Trigger Window
tWD_CLS
VOUT1
tWD
Internal Circuitry
Figure 36. Watchdog Window with Tolerances
Figure 38. Switcher 1 Block Diagram
Internally, connected to the VOUT1 pin, the primary
feedback regulates the output and the secondary path
compares to the second reference for the reset circuitry.
The EN pin controls the enable circuitry for the switchers.
It can accept a logic−level input and is also capable of high
voltages and can be connected directly to VBAT. If EN is
connected to VBAT, and VBAT voltage might exceed 40 V,
the connection from EN to VBAT should be made with a 10
kW resistor.
Error Amplifier
Switcher 1 uses a transconductance type error amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
Figure 37. NCV97200 Valid & Invalid Watchdog
Periods vs. CWDT
Debug Mode
The compensation components must be connected
between the output of the error amplifier and the electrical
ground (between pins COMP1 and GND). For most
applications, the following compensation circuitry is
recommended:
The NCV97200 includes a user selectable “debug mode”
that disables spread spectrum and the watchdog to make it
easier to take certain measurements during evaluation.
While the watchdog is disabled, it is unable to assert a fault
on the RSTB1 signal.
To enter and remain in debug mode, connect the WDT pin
to GND and connect the SYNCI pin high (a voltage greater
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18
NCV97200
COMP
DRV 1
VBAT
12.4 k
10 pF
DRV LDO
560 pF
BST 1
Figure 39. Recommended Compensation for
Switcher 1
Switcher
1
Gate Driver
SW 1
Slope Compensation
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50% (sub−harmonics oscillations). The
fixed amplitude of the slope compensation signal requires
the inductor to be greater than a minimum value in order to
avoid sub−harmonic oscillations. For the 3.3 V output, the
recommended inductor value is from 2.2 mH to 4.7 mH.
To determine the minimum inductor required to avoid
sub−harmonic oscillations, please refer to the following
equation:
Internal Circuitry
Figure 40. Switcher 1 Drive and Bootstrap Circuitry
In order for the bootstrap capacitor to stay charged, the
switch node needs to be pulled down to ground regularly. In
very light load condition, when switcher 1 skips switching
cycles to keep the output voltage in regulation, the bootstrap
voltage could collapse and the regulator stop switching. To
prevent this, an approximately 10 mA internal load is
connected on VOUT1 to operate correctly in all cases. When
the NCV97200 is enabled and VBAT is below
approximately 7.5 V, the internal load is increased to
approximately 60 mA.
VOUT
2 @ Sramp
Lmin
+
where:
A fast−charge circuit ensures the bootstrap capacitor is
always charged prior to starting the switcher after it has been
enabled.
L
: minimum inductor required to avoid sub−harmonic
oscillations [mH]
min
V : output voltage [V]
OUT
Soft Start
S
ramp
: internal slope compensation [A/ms]
Upon being enabled or released from a fault condition,
and after the Enable Delay Time, a soft−start circuit ramps
the switching regulator error amplifier reference voltage to
the target value. During soft−start, the average switching
frequency is lower than its normal mode value (typically 2
MHz) until the output voltage approaches regulation.
Drive and Bootstrap
At the DRV1 pin an internal regulator provides a
ground−referenced voltage to an external capacitor
(C
DRV1
), to allow fast recharge of the external bootstrap
capacitor (C
) used to supply power to the power switch
BST1
gate driver. If the voltage at the DRV1 pin goes below the
DRV1 POR Threshold V , switching is inhibited and
Current Limit
DRV1SP
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
the soft−start circuit is reset, until the DRV1 pin voltage goes
back up above V
.
DRV1ST
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19
NCV97200
current set point of the regulator. Figure 41 shows − for a
Frequency reduction is automatically terminated when the
input voltage drops back below the V Frequency
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current switcher
1 can deliver to a load. Figure 42 shows the same for 2.2 mH
inductor.
BAT
Foldback threshold V
.
FL1D
FSW
(MHz)
Internal slope compensation Sramp1 also reduces
switcher 1 peak current limit proportional to the duty cycle.
The amount of this reduction for switcher 1 is the product of
Sramp1, switching period, and 3.3 divided by VBAT.
2
1
VIN (V)
3.7 4.85
18 20
34
40
45
Figure 43. High Voltage Frequency Foldback
Inductor Selection
A 3.3 mH inductor is recommended for Switcher 1,
although values between 2.2 mH and 4.7 mH may give more
optimized performance in some applications. The
relationship between several operating parameters are given
by the equation below.
VOUT
VIN,max
VOUT
ǒ
1 *
Ǔ
Figure 41. Switcher 1 Dc Output Current vs. VIN with
L +
dIr @ fsw @ IOUT
a 4.7 mH Inductor
where:
V
V
: dc output voltage [V]
OUT
: maximum dc input voltage [V]
IN,max
dI : inductor current ripple [%]
r
f
I
: switching frequency [Hz]
sw
: dc output current [A]
OUT
Discontinuous Mode
The regulator operates in Continuous Conduction Mode
(CCM) when average inductor current exceeds half the
peak−to−peak ripple current, and in Discontinuous
Conduction Mode (DCM) when it does not. The borderline
between these modes can be found using the following
equation:
VOUT
VIN,max
ǒ
1 *
Ǔ
@
VOUT
L
1
2
IBCM
+
@
fsw
where:
Figure 42. Switcher 1 Dc Output Current vs. VIN with
I
: borderline conduction mode output current [A]
: dc output voltage [V]
BCM
a 2.2 mH Inductor
V
V
f
OUT
: maximum dc input voltage [V]
IN,max
: switching frequency [Hz]
High Voltage Frequency Foldback
sw
To limit the power lost in generating the drive voltage for
the power switch, the switching frequency is reduced by a
L: inductor value [H]
Average output currents above IBCM will cause operation
in CCM while average output currents below IBCM will
cause operation in DCM.
factor of 2 when the input voltage exceeds the V
BAT
Frequency Foldback Threshold V
(see Figure 43)
FL1U
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20
NCV97200
Soft Start
SWITCHER 2
Upon being enabled or released from a fault condition,
and once switcher 1 has completed soft start, a soft−start
circuit ramps the switching regulator error amplifier
reference voltage to the final value. The typical soft−start
duration is 1.4 ms.
Please note that since this is a boost regulator, the VOUT2
output will be a diode voltage below VOUT1 until it starts
switching in regulation. This is normal behavior – please see
the scope capture below:
The NCV97200 contains a boost regulator, switcher 2,
which boosts the 3.3 V from the switcher 1 to 5.0 V. This
non−synchronous boost regulator requires an external
freewheeling diode. Switcher 2 is intended to be used for
in−vehicle networks (e.g. CAN) and can supply up to
400 mA dc.
SW2
VOUT1
Gate
Driver
VOUT2
GND2
Bandgap 1
Error
Amplifier
Bandgap 2
Reset
Comparator
VOUT2
Figure 45. Switcher 2 Soft−start
Internal Circuitry
Current Limit
Due to the ripple on the inductor current, the average
output current of the boost converter is lower than the peak
current set point of the regulator. Table 7 shows some
examples of common setups.
Figure 44. Switcher 2 Block Diagram
Internally, connected to the VOUT2 pin, the primary
feedback regulates the output and the secondary path
compares to the second reference for the reset circuitry.
The EN pin controls the enable circuitry for the switcher 2
output. Once switcher 1 has completed soft−start and the
output is in regulation, switcher 2 is automatically enabled.
Table 7. SW2 WORST CASE DC OUTPUT CURRENT
Output
Inductor Worst Case Max Typical Max Dc
Voltage (V) Value (uH) Dc Output (mA)
Output (mA)
5.0
5.0
4.7
2.2
450
400
530
Error Amplifier
480
Switcher 2 uses a voltage type error amplifier. The
compensation for this regulator is internal and cannot be
adjusted.
ORDERING INFORMATION
Distinguishing
†
Characteristic
Device
Package
Part Marking
Shipping
NCV97200MW01R2G
No shutdown upon
Watchdog fault
QFNW20
97200
01
4000 / Tape & Reel
4000 / Tape & Reel
(Pb−Free)
NCV97200MW33R2G
Shutdown (auto−restart)
upon Watchdog fault
QFNW20
(Pb−Free)
97200
33
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW20 4x4, 0.5P
CASE 484AD
ISSUE C
DATE 03 DEC 2019
SCALE 2:1
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
XXXXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON16467G
QFNW20 4x4, 0.5P
PAGE 1 OF 1
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