NDC7002N [ONSEMI]
双 N 沟道增强型场效应晶体管，50V，0.51A，2Ω;
| 型号： | NDC7002N |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道增强型场效应晶体管，50V，0.51A，2Ω PC 开关 光电二极管 晶体管 场效应晶体管 |
| 文件： | 总7页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
D2
Field Effect Transistor -
Dual, N-Channel,
Enhancement Mode
S1
D1
G2
S2
G1
TSOT23 6−Lead
CASE 419BL
NDC7002N
MARKING DIAGRAM
General Description
These dual N−Channel enhancement mode power field effect
transistors are produced using onsemi’s proprietary, high cell density,
DMOS technology. This very high density process has been designed
to minimize on−state resistance, provide rugged and reliable
performance and fast switching. These devices is particularly suited
for low voltage applications requiring a low current high side switch.
XXX MG
G
1
XXX = Specific Device Code
M
G
= Date Code
= Pb−Free Package
Features
• 0.51 A, 50 V, R
• High Density Cell Design for Low R
= 2 W @ V = 10 V
GS
DS(ON)
(Note: Microdot may be in either location)
DS(ON)
PINOUT
• Proprietary SUPERSOTt−6 Package Design Using Copper Lead
Frame for Superior Thermal and Electrical Capabilities
• High Saturation Current
3
2
1
4
5
6
• This is a Pb−Free Device
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Drain−Source Voltage
Gate−Source Voltage
Ratings
50
Unit
V
V
DS
V
GSS
20
V
I
D
Drain Current
− Continuous (Note 1a)
− Pulsed
A
SOT−6 (SUPERSOTt−6)
0.51
1.5
ORDERING INFORMATION
P
Power Dissipation
(Note 1a)
W
D
0.96
0.9
†
Shipping
Package
Device
(Note 1b)
(Note 1c)
0.7
3000 /
Tape & Reel
TSOT−23−6
(Pb−free)
NDC7002N
T , T
Operating and Storage Tempera-
ture Range
−55 to +150
°C
J
STG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
RθJC
Thermal Resistance,
Junction to Case (Note 1)
60
°C/W
RθJA
Thermal Resistance,
Junction to Ambient (Note 1a)
130
© Semiconductor Components Industries, LLC, 1997
1
Publication Order Number:
December, 2021 − Rev. 2
NDC7002N/D
NDC7002N
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
I
D
= 250 mA, V = 0 V
50
V
DSS
GS
I
Zero Gate Voltage Drain Current
V
DS
= 40 V, V = 0 V
1
500
mA
DSS
GS
T = 125°C
J
I
Gate−Body Leakage, Forward
Gate−Body Leakage, Reverse
V
V
= 20 V, V = 0 V
100
nA
nA
GSSF
GS
DS
I
= −20 V, V = 0 V
−100
GSSR
GS
DS
ON CHARACTERISTICS (Note 2)
V
Gate Threshold Voltage
V
V
= V , I = 250 mA
1
0.8
1.9
1.5
2.5
2.2
V
GS(th)
GS
DS
D
T = 125°C
J
R
Static Drain−Source On−Resistance
= 10 V, I = 0.51 A
1
1.7
2
3.5
W
DS(ON)
GS
D
T = 125°C
J
V
GS
V
GS
V
DS
= 4.5 V, I = 0.35 A
1.6
4
D
I
On−State Drain Current
= 10 V, V = 10 V
1.5
A
D(on)
DS
g
FS
Forward Transconductance
= 10 V, I = 0.51 A
400
mS
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 25 V, V = 0 V, f = 1.0 MHz
20
13
5
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
rss
SWITCHING CHARACTERISTICS (Note 2)
t
Turn−On Delay Time
Turn−On Time
V
= 25 V, I = 0.25 A, V = 10 V,
GEN
6
6
20
20
20
20
ns
d(on)
DD
D
GS
R
= 25 W
t
r
t
Turn−Off Delay Time
Turn−Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate to Drain Charge
11
5
d(off)
t
f
Q
V
DS
= 25 V, I = 0.51 A, V = 10 V
1
nC
nC
nC
g
D
GS
Q
0.19
0.33
gs
gd
Q
DRAIN−SOURCE DIODE CHARACTERISTICS
I
Maximum Continuous Source Current
Maximum Pulse Source Current (Note 2)
Drain−Source Diode Forward Voltage
0.51
1.5
A
A
V
S
I
SM
V
SD
V
GS
= 0 V, I = 0.51 A (Note 2)
0.8
1.2
S
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
θ
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
θ
θ
JC
CA
TJ * TA
TJ * TA
qJC ) RqCA(t)
PD(t) +
+
+ I2D(t) RDS(ON)@TJ
R
qJA(t)
R
Typical R
for single device operation using the board layouts shown below on 4.5″ x 5″ FR−4 PCB in a still air environment:
q
JA
2
a. 130°C/W when mounted on a 0.125 in pad of 2oz copper.
b. 140°C/W when mounted on a 0.005 in pad of 2oz copper.
c. 180°C/W when mounted on a 0.0015 in pad of 2oz copper.
2
2
1a
1b
1c
Scale 1:1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 ms, Duty cycle ≤ 2.0 %.
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2
NDC7002N
TYPICAL ELECTRICAL CHARACTERISTICS
3
1.5
1.2
0.9
0.6
0.3
0
V
GS
= 3.5 V
V
GS
= 10 V
8.0
7.0
4.0
6.0
2.5
4.5
5.5
5.0
5.0
2
5.5
6.0
4.5
1.5
7.0
8.0
10
4.0
3.5
3.0
1
0.5
0
0.3
0.6
0.9
1.2
1.5
0
1
2
3
4
5
I , Drain Current (A)
D
V
DS
, Drain−Source Voltage (V)
Figure 2. On−Resistance Variation with Gate
Figure 1. On−Region Characteristics
Voltage and Current
2
2.5
2
I
= 0.51 A
GS
V
GS
= 10 V
D
V
1.8
1.6
1.4
1.2
1
= 10 V
T = 125°C
J
1.5
1
25°C
0.8
0.6
0.4
-55°C
0.5
0
0.3
0.6
0.9
1.2
1.5
−50 −25
0
25
50
75 100 125 150
I , Drain Current (A)
D
T , Junction Temperature (°C)
J
Figure 4. On−Resistance vs Variation with Drain
Figure 3. On−Resistance Variation with Temperature
Current and Temperature
1.5
1.2
1.1
1
V
I
= V
GS
DS
D
V
DS
= 10 V
T = −55°C
J
= 250 mA
25°C
125°C
1.2
0.9
0.6
0.3
0
0.9
0.8
0.7
−50 −25
0
25
50
75 100 125 150
1
2
3
4
5
6
7
8
V
GS
, Gate to Source Voltage (V)
T , Junction Temperature (°C)
J
Figure 6. Gate Threshold Variation with Temperature
Figure 5. Transfer Characteristics
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3
NDC7002N
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
1.5
1.16
1.12
1.08
1.04
1
1
I
D
= 250 mA
V
= 0 V
GS
0.5
T = 125°C
J
25°C
0.1
0.01
-55°C
0.96
0.92
0.88
0.001
0.2
0.4
0.6
0.8
1
1.2
−50 −25
0
25
50
75
100 125 150
T , Junction Temperature (°C)
J
V
SD
, Body Diode Forward Voltage (V)
Figure 7. Breakdown Voltage Variation with Temperature
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
100
50
10
V
D
= 25 V
DS
I
= 0.51 A
8
6
4
2
0
C
iss
20
10
5
C
oss
C
rss
2
1
f = 1 MHz
= 0 V
V
GS
0
0.2
0.4
0.6
0.8
1
1.2
0.1 0.2
0.5
1
2
5
10 20
50
Q , Gate Charge (nC)
g
V
DS
, Drain to Source Voltage (V)
Figure 10. Gate Charge Characteristics
Figure 9. Capacitance Characteristics
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DS
= 10 V
T = −55°C
J
25°C
125°C
0
0.3
0.6
0.9
1.2
1.5
V
GS
, Gate to Source Voltage (V)
Figure 11. Transconductance Variation with Drain
Current and Temperature
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4
NDC7002N
TYPICAL THERMAL CHARACTERISTICS
0.55
1.2
1.1
1
1a
0.5
1a
1b
1c
1b
0.45
1c
0.9
0.8
0.7
0.6
4.5″ x 5″ FR−4 Board
0.4
4.5″ x 5″ FR−4 Board
T = 25°C’
A
T = 25°C
A
Still Air
Still Air
V
GS
= 10 V
0.35
0
0.2
0.4
0.6
0.8
1
0
0.025
0.05
0.075
0.1
0.125
2
2
2oz Copper Mounting Pad Area (in )
2oz Copper Mounting Pad Area (in )
Figure 12. SOT−6 Dual Package Maximum Steady−State
Figure 13. Maximum Steady−State Drain Current
Power Dissipation versus Copper Mounting Pad Area
versus Copper Mounting Pad Area
3
2
1
0.5
0.2
0.1
V
= 10 V
GS
0.05
Single Pulse
R
= See Note 1c
q
JA
0.02
0.01
T = 25°C
A
1
2
5
10
20
50 70
V
DS
, Drain−Source Voltage (V)
Figure 14. Maximum Safe Operating Area
1
D = 0.5
0.5
0.2
R
R
(t) = r(t) * R
q
JA
= See Note 1c
q
q
JA
JA
0.2
0.1
0.1
P(pk)
0.05
0.02
0.01
Single Pulse
t
0.05
1
t
2
T − T = P * R (t)
Duty Cycle, D = t /t
q
JA
1
J
A
0.02
0.01
2
0.001
0.1
t , Time (sec)
1
10
100
300
0.0001
0.01
1
Figure 15. Transient Thermal Response Curve
(Note: Thermal characterization performed using the conditions described in note 1c. Transient
thermal response will change depending on the circuit board design.)
SUPERSOT is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOT23 6−Lead
CASE 419BL
ISSUE A
1
DATE 31 AUG 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
XXX MG
G
1
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON83292G
TSOT23 6−Lead
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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