NDDL01N60ZT4G [ONSEMI]
功率 MOSFET，600V，0.8A，15Ω，单 N 沟道，DPAK;
| 型号： | NDDL01N60ZT4G |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，600V，0.8A，15Ω，单 N 沟道，DPAK |
| 文件： | 总11页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NDDL01N60Z, NDTL01N60Z
N-Channel Power MOSFET
600 V, 15 W
Features
• 100% Avalanche Tested
• Gate Charge Minimized
http://onsemi.com
• Zener−protected
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
V
R
MAX
DS(ON)
(BR)DSS
Compliant
600 V
15 W @ 10 V
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current
Symbol
NDD
NDT
Unit
V
N−Channel MOSFET
D (2, 4)
V
DSS
600
30
V
GS
V
I
D
0.8
0.5
26
0.25
0.15
2
A
Steady State, T = 25°C (Note 1)
C
Continuous Drain Current
I
D
A
G (1)
Steady State, T = 100°C (Note 1)
C
Power Dissipation
P
D
W
Steady State, T = 25°C
C
S (3)
Pulsed Drain Current, t = 10 ms
I
3.4
12
A
A
p
DM
Source Current (Body Diode)
I
S
2.5
1.7
4
Single Pulse Drain−to−Source
EAS
mJ
1
Avalanche Energy (I = 0.8 A)
D
2
3
Peak Diode Recovery (Note 2)
dv/dt
4.5
V/ns
SOT−223
CASE 318E
STYLE 3
Lead Temperature for Soldering
Leads
T
L
260
°C
Operating Junction and Storage
Temperature
T , T
−55 to +150
°C
J
STG
4
4
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Limited by maximum junction temperature
2
1
2
3
1
3
2. I = 1.5 A, di/dt ≤ 100 A/ms, V ≤ BV
S
DD
DSS
DPAK
IPAK
CASE 369C
STYLE 2
CASE 369D
STYLE 2
THERMAL RESISTANCE
Parameter
Symbol
Value
Unit
°C/W
°C/W
Junction−to−Case (Drain)
NDDL1N60Z
R
4.8
q
JC
JA
MARKING & ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 3 of this data sheet.
Junction−to−Ambient
(Note 4) NDDL1N60Z
(Note 3) NDDL1N60Z−1
(Note 4) NDTL1N60Z
(Note 5) NDTL1N60Z
R
42
96
62
q
151
3. Insertion mounted.
4. Surface−mounted on FR4 board using 1” sq. pad size
(Cu area = 1.127” sq. [2 oz] including traces).
5. Surface−mounted on FR4 board using minimum recommended pad size
(Cu area = 0.026” sq. [2 oz]).
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May, 2014 − Rev. 0
NDDL01N60Z/D
NDDL01N60Z, NDTL01N60Z
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Test Conditions
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 1 mA
600
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
Reference to 25°C, I = 1 mA
610
mV/°C
(BR)DSS
D
Drain−to−Source Leakage Current
I
V
DS
= 600 V, V = 0 V
T = 25°C
J
1
mA
DSS
GS
T = 125°C
J
50
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 6)
Gate Threshold Voltage
I
V
=
20 V
nA
GSS
GS
V
V
= V , I = 50 mA
3
4.0
9.6
4.5
15
V
GS(TH)
DS
GS
D
Negative Threshold Temperature Coef-
ficient
V
/T
J
mV/°C
GS(TH)
Static Drain-to-Source On Resistance
Forward Transconductance
R
V
V
= 10 V, I = 0.4 A
12.2
0.7
W
DS(on)
GS
D
g
= 15 V, I = 0.4 A
S
FS
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCES
Input Capacitance (Note 7)
C
C
92
13
3
pF
pF
iss
Output Capacitance (Note 7)
V
= 25 V, V = 0 V, f = 1 MHz
GS
oss
DS
Reverse Transfer Capacitance (Note 7)
C
rss
Effective output capacitance, energy
related (Note 9)
C
5.5
o(er)
V
= 0 V, V = 0 to 480 V
GS
DS
Effective output capacitance, time
related (Note 10)
C
8.1
I
D
= constant, V = 0 V,
o(tr)
GS
V
DS
= 0 to 480 V
Total Gate Charge (Note 7)
Gate-to-Source Charge (Note 7)
Gate-to-Drain Charge (Note 7)
Plateau Voltage
Q
4.9
1.2
2.4
5.8
6.6
nC
g
Q
gs
V
DS
= 300 V, I = 0.4 A, V = 10 V
D GS
Q
gd
GP
V
V
Gate Resistance
R
W
g
SWITCHING CHARACTERISTICS (Note 8)
Turn-on Delay Time
t
10
5
ns
d(on)
Rise Time
t
r
V
DD
= 300 V, I = 0.4 A,
D
V
GS
= 10 V, R = 0 W
G
Turn-off Delay Time
t
13
18
d(off)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Diode Forward Voltage
V
T = 25°C
0.8
0.7
183
33
1.2
V
SD
J
I
S
= 0.4 A, V = 0 V
GS
T = 100°C
J
Reverse Recovery Time
Charge Time
t
ns
rr
t
a
V
GS
= 0 V, V = 30 V
DD
I
S
= 1 A, d /d = 100 A/ms
i t
Discharge Time
t
150
255
b
Reverse Recovery Charge
Q
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
7. Guaranteed by design.
8. Switching characteristics are independent of operating junction temperatures.
9. C
10.C
is a fixed capacitance that gives the same stored energy as C
while V is rising from 0 to 80% V
o(er)
o(tr)
oss DS
(BR)DSS
while V is rising from 0 to 80% V
DS (BR)DSS
is a fixed capacitance that gives the same charging time as C
oss
http://onsemi.com
2
NDDL01N60Z, NDTL01N60Z
MARKING DIAGRAMS
4
Drain
4
Drain
Drain
4
AYW
1N60ZG
G
2
1
2
3
Drain
1
3
1
2
3
Gate Source
Gate Drain Source
Gate Drain Source
IPAK
DPAK
SOT−223
A
Y
= Assembly Location
= Year
W, WW = Work Week
L1N60Z, 1N60Z = Specific Device Codes
G or G = Pb−Free Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
NDDL01N60Z−1G
Package
Shipping
IPAK
75 Units / Rail
(Pb-Free, Halogen-Free)
NDDL01N60ZT4G
NDTL01N60ZT1G
NDTL01N60ZT3G
DPAK
2500 / Tape & Reel
1000 / Tape & Reel
4000 / Tape & Reel
(Pb-Free, Halogen-Free)
SOT−223
(Pb-Free, Halogen-Free)
SOT−223
(Pb-Free, Halogen-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
3
NDDL01N60Z, NDTL01N60Z
TYPICAL CHARACTERISTICS
1.4
1.2
1.0
0.8
0.6
0.4
1.4
V
GS
= 10 V to 7.0 V
V
DS
= 15 V
1.2
1.0
T = 25°C
J
V
V
= 6.5 V
= 6.0 V
GS
0.8
0.6
0.4
GS
T = 150°C
J
V
V
= 5.5 V
= 5.0 V
GS
0.2
0
0.2
0
T = −55°C
J
GS
0
5
10
15
20
25
30
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
25
23
21
19
17
15
25
23
21
19
17
15
T = 25°C
D
T = 25°C
GS
J
J
V
I
= 0.4 A
= 10 V
13
11
13
11
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
GS
, GATE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.6
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
I
V
= 0.4 A
= 10 V
I
D
= 1 mA
D
GS
0.925
0.900
0.6
0.4
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Breakdown Voltage Variation with
Temperature
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4
NDDL01N60Z, NDTL01N60Z
TYPICAL CHARACTERISTICS
10,000
1.15
1.10
1.05
I
D
= 50 mA
1000
100
T = 150°C
J
1.00
0.95
0.90
0.85
0.80
0.75
T = 125°C
J
T = 100°C
J
10
1
0.70
0.65
−50 −25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Threshold Voltage Variation with
Temperature
Figure 8. Drain−to−Source Leakage Current
vs. Voltage
12
11
10
9
1000
100
350
300
Q
V
= 0 V
T
GS
V
DS
T = 25°C
J
f = 1 MHz
250
200
150
100
C
C
V
ISS
GS
8
7
Q
Q
GD
GS
6
OSS
5
10
1
4
V
= 300 V
T = 25°C
= 0.4 A
DS
3
J
C
RSS
I
D
2
50
0
1
0
0.1
1
10
100
1000
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 9. Capacitance Variation
Figure 10. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
10
T = 100°C
J
V
V
= 10 V
= 300 V
GS
DD
I
D
= 0.8 A
T = 125°C
J
1
t
d(off)
t
f
t
d(on)
10
0.1
t
r
T = 150°C
J
T = 25°C
J
0.01
T = −55°C
J
1
0.001
0.1
1
10
100
0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0 1.1
R , GATE RESISTANCE (W)
G
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
http://onsemi.com
5
NDDL01N60Z, NDTL01N60Z
TYPICAL CHARACTERISTICS
10
1
10
V
≤ 30 V
V
≤ 30 V
GS
GS
10 ms
100 ms
1 ms
Single Pulse
= 25°C
Single Pulse
T = 25°C
C
T
C
1
10 ms
100 ms
10 ms
1 ms
10 ms
dc
0.1
0.1
dc
0.01
0.01
R
Limit
R
Limit
DS(on)
DS(on)
Thermal Limit
Package Limit
Thermal Limit
Package Limit
0.001
0.001
0.1
1
10
100
1000
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area for NDDL01N60Z
Figure 14. Maximum Rated Forward Biased
Safe Operating Area for NDTL01N60Z
10
Duty Cycle = 0.5
0.20
R
steady state = 4.8°C/W
q
JC
1
0.10
0.05
0.02
0.01
0.1
Single Pulse
0.01
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 15. Thermal Impedance (Junction−to−Case) for NDDL01N60Z
100
10
1
Duty Cycle = 0.5
0.20
0.10
0.05
R
steady state = 62°C/W
q
JA
0.02
0.01
0.1
Single Pulse
0.01
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 16. Thermal Impedance (Junction−to−Ambient) for NDTL01N60Z
http://onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. ANODE
STYLE 3:
STYLE 4:
PIN 1. SOURCE
STYLE 5:
PIN 1. DRAIN
PIN 1. GATE
2. DRAIN
2. CATHODE
3. NC
2. DRAIN
3. GATE
4. DRAIN
2. GATE
3. SOURCE
4. DRAIN
3. SOURCE
4. GATE
4. CATHODE
STYLE 6:
PIN 1. RETURN
STYLE 7:
STYLE 8:
STYLE 9:
STYLE 10:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
CANCELLED
PIN 1. INPUT
2. GROUND
3. LOGIC
PIN 1. CATHODE
2. ANODE
2. INPUT
3. OUTPUT
4. INPUT
3. GATE
4. CATHODE
4. GROUND
4. ANODE
STYLE 11:
PIN 1. MT 1
STYLE 12:
STYLE 13:
PIN 1. INPUT
2. OUTPUT
3. NC
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. MT 2
3. GATE
4. MT 2
4. OUTPUT
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
Y
= Assembly Location
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
DATE 15 DEC 2010
C
B
NOTES:
SCALE 1:1
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
R
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
S
1
2
3
−T−
SEATING
PLANE
2.29 BSC
K
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
G
M
T
0.13 (0.005)
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
STYLE 2:
STYLE 3:
PIN 1. ANODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
Integrated
Circuits
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
Discrete
3. GATE
4. ANODE
xxxxx
ALYWW
x
YWW
xxxxxxxx
STYLE 5:
PIN 1. GATE
2. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
xxxxxxxxx = Device Code
A
= Assembly Location
lL
Y
= Wafer Lot
= Year
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE G
2
1
DATE 31 MAY 2023
3
SCALE 1:1
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX = Device Code
A
= Assembly Location
L
= Wafer Lot
STYLE 1:
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
Y
WW
G
= Year
= Work Week
= Pb−Free Package
PIN 1. BASE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. CATHODE
2. ANODE
3. GATE
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
2. COLLECTOR
3. EMITTER
3. SOURCE
4. DRAIN
4. COLLECTOR
4. CATHODE
4. ANODE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
PIN 1. GATE
STYLE 8:
PIN 1. N/C
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
onsemi and
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