NDS352AP [ONSEMI]
P 沟道逻辑电平增强型场效应晶体管，-30V，-0.9A，300mΩ;
| 型号： | NDS352AP |
| 厂家： | 
ONSEMI |
| 描述： | P 沟道逻辑电平增强型场效应晶体管，-30V，-0.9A，300mΩ PC 开关 光电二极管 晶体管 场效应晶体管 |
| 文件： | 总9页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
P-Channel Logic Level
Enhancement Mode Field
Effect Transistor
D
G
S
SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9
CASE 527AG
NDS352AP
MARKING DIAGRAM
General Description
These P −Channel logic level enhancement mode power field effect
transistors are produced using onsemi’s proprietary, high cell density,
DMOS technology. This very high density process is especially
tailored to minimize on− state resistance. These devices are
particularly suited for low voltage applications such as notebook
computer power management, portable electronics, and other battery
powered circuits where fast high−side switching, and low in− line
power loss are needed in a very small outline surface mount package.
Drain
3
352A(M)
1
Gate
2
Source
M = Date Code
Features
S
• −0.9 A, −30 V
♦ R
♦ R
= 0.5 ꢀ @ V = −4.5 V
GS
DS(on)
= 0.3 ꢀ @ V = −10 V
DS(on)
GS
G
• Industry Standard Outline SOT−23 Surface Mount Package Using
Proprietary SUPERSOTt−3 Design for Superior Thermal and
Electrical Capabilities
• High Density Cell Design for Extremely Low R
DS(on)
D
• Exceptional On−Resistance and Maximum DC Current Capability
• This is a Pb−Free Device
P−Channel MOSFET
ORDERING INFORMATION
†
Device
NDS352AP
Package
Shipping
3000 /
Tape & Reel
SOT−23−3/
SUPERSOT−23
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 1997
1
Publication Order Number:
December, 2021 − Rev. 5
NDS352AP/D
NDS352AP
ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted.
A
Symbol
Parameter
Ratings
Unit
V
V
DSS
GSS
Drain−Source Voltage
Gate−Source Voltage − Continuous
−30
20
V
V
I
D
Maximum Drain Current – Continuous (Note 1a)
Maximum Drain Current – Pulsed
0.9
A
10
P
Maximum Power Dissipation (Note 1a)
Maximum Power Dissipation (Note 1b)
Operating and Storage Temperature Range
0.5
W
D
0.46
T , T
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Symbol
Parameter
Thermal Resistance, Junction−to−Ambient (Note 1a)
Thermal Resistance, Junction−to−Case (Note 1)
Ratings
250
Unit
°C/W
°C/W
R
ꢁ
JA
R
75
ꢁ
JC
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
ꢁ
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
ꢁ
ꢁ
JC
CA
TJ * TA
TJ * TA
PD(t) +
+
+ I2 (t) R
DS(ON)@TJ
D
R
ꢁ JA(t)
R
ꢁ JC ) Rꢁ CA(t)
Typical R
using the board layouts shown below on 4.5″x 5″ FR−4 PCB in a still air environment:
ꢁ
JA
2
2
a) 250°C/W when mounted on a 0.02 in pad
b) 270°C/W when mounted on a 0.001 in pad
of 2oz copper.
of 2oz copper.
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2
NDS352AP
ELECTRICAL CHARACTERISTICS T = 25°C unless otherwise noted.
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain–Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
V
DS
V
DS
V
GS
V
GS
= 0 V, I = −250 ꢂ A
−30
−
−
−
−
−
−
−
V
DSS
D
I
= −24 V, V = 0 V
−1
ꢂ
A
DSS
GS
= −24 V, V = 0 V, T = 125°C
−
−10
−100
100
GS
J
I
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
= −20 V, V = 0 V
−
nA
nA
GSSF
DS
I
= 20 V, V = 0 V
−
GSSR
DS
ON CHARACTERISTICS (Note 2)
V
Gate Threshold Voltage
−0.8
−0.5
−
−1.7
−1.4
0.45
0.65
0.25
−
−2.5
−2.2
0.5
0.7
0.3
−
V
V
DS
V
DS
V
GS
V
GS
V
GS
V
GS
V
DS
= V , I = −250 ꢂ A
GS(th)
GS D
= V , I = −250 ꢂ A, T = 125°C
GS
D
J
R
Static Drain–Source On–Resistance
= −4.5 V, I = −0.9 A
ꢀ
DS(on)
D
= −4.5 V, I = −0.9 A, T = 125°C
−
D
J
= −10 V, I = −1 A
−
D
I
On–State Drain Current
= −4.5 V, V = −5 V
−2
−
A
S
D(on)
DS
g
FS
Forward Transconductance
= −5 V, I = −0.9 A
1.9
−
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −15 V, V = 0 V, f = 1.0 MHz
−
−
−
135
88
−
−
−
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
40
rss
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
V
= −6 V, I = −1 A,
−
−
−
−
−
−
−
−
−
−
−
5
17
35
30
8
10
30
70
60
15
30
90
90
3
ns
ns
ns
ns
ns
ns
ns
ns
nC
nC
nC
d(on)
DD
GS
D
= −4.5 V, R
= 6 ꢀ
GEN
t
r
d(off)
t
f
V
DD
V
GS
= −10 V, I = −1 A,
D
d(on)
= −10 V, R
= 50 ꢀ
GEN
t
r
16
35
30
2
d(off)
t
f
Q
V
DS
V
GS
= −10 V, I = −0.9 A,
g
D
= −4.5 V
Q
0.5
1
−
gs
gd
Q
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Source Current
−
−
−
−
−
−0.42
−10
A
A
V
S
I
Maximum Pulsed Drain−Source Diode Forward Current
SM
V
SD
Drain–Source Diode Forward Voltage
V
GS
= 0 V, I = −0.42 A (Note 2)
−0.8
−1.2
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ꢂ s, Duty Cycle ≤ 2.0%.
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3
NDS352AP
TYPICAL ELECTRICAL CHARACTERISTICS
−5
−4
1.6
V
GS
= −10 V
V
GS
= −3.5 V
−7.0
−6.0
−5.5
−5.0
1.4
1.2
−4.0
−4.5
−4.5
−3
−2
−1
−5.0
1
−5.5
−4.0
−6.0
0.8
−7.0
−4
−3.5
−3.0
−10
0.6
0.4
0
0
−5
0
−1
−2
−3
−1
−2
−3
−4
−5
V
DS
, Drain−Source Voltage (V)
I , Drain Current (A)
D
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
1.6
1.4
1.2
1
1.6
1.4
1.2
I
V
= −0.9 A
D
= −4.5 V
GS
T = 125°C
J
25°C
1
0.8
0.6
−55°C
0.8
0.6
0.4
0.2
V
= −4.5 V
GS
−50
−25
0
25
50
75
100
125 150
0
−1
−2
I , Drain Current (A)
−3
−4
T , Junction Temperature (°C)
J
D
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Temperature
Drain Current and Temperature
−4
1.2
1.1
1
V
DS
= −10 V
T = −55°C
J
−3.2
25°C
−2.4
−1.6
−0.8
0
125°C
0.9
0.8
0.7
−1
−2
−3
−4
−5
−6
−50
−25
0
25
50
75
100 125 150
V
GS
, Gate to Source Voltage (V)
T , Junction Temperature (°C)
J
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation with
Temperature
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4
NDS352AP
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
1.1
I
D
= −250 ꢂ A
V
GS
= 0 V
1.08
1.06
1.04
1
T = 125°C
J
25°C
0.1
0.01
1.02
−55°C
1
0.98
0.96
0.94
0.001
0.0001
−50
−25
0
25
50
75
100
125 150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
T , Junction Temperature (°C)
J
−V , Body Diode Forward Voltage (V)
SD
Figure 7. Breakdown Voltage Variation with
Temperature
Figure 8. Body Diode Forward Voltage Variation
with Source Current and Temperature
10
8
400
300
V
DS
= −5 V
I
D
= −0.9 A
−10 V
200
100
50
C
iss
−15 V
6
C
oss
4
C
rss
2
f = 1 MHz
= 0 V
30
20
V
GS
0
0.1
1
10
0
1
2
3
4
5
−V , Drain−Source Voltage (V)
DS
Q , Gate Charge (nC)
g
Figure 9. Capacitance Characteristics
Figure 10. Gate Charge Characteristics
t
off
V
DD
t
on
t
r
t
t
t
f
d(on)
d(off)
V
IN
R
90%
L
90%
D
S
V
OUT
V
GS
V
OUT
10%
10%
90%
50%
R
GEN
DUT
G
50%
V
IN
10%
Pulse Width
Inverted
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
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5
NDS352AP
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
3
2.5
2
1 ms
V
DS
= −5.0 V
10
10 ms
T = −55°C
R
Limit
J
DS(on)
25°C
1
0.1
100 ms
125°C
1.5
1
1 s
10 s
DC
V
GS
= −4.5 V
Single Pulse
R = 270°C/W
ꢁ
JA
0.5
0
T = 25°C
A
0.01
0.1 0.2
0.5
1
2
5
10
20 30 50
0
−1
−2
−3
−4
−5
I , Drain Current (A)
D
V
DS
, Drain to Source Voltage (V)
Figure 13. Transconductance Variation with Drain
Current and Temperature
Figure 14. Maximum Safe Operating Area
1
1.2
1.1
0.8
1
0.6
0.4
0.2
0
1a
1b
0.9
1a
0.8
1b
4.5″x5″ FR−4 Board
4.5″x5″ FR−4 Board
T = 25°C
A
0.7
0.6
T = 25°C
A
Still Air
Still Air
V
GS
= −4.5 V
0.1
0.2
0.3
0.4
0.4
0
0
0.1
0.2
0.3
2
2
2oz Copper Mounting Pad Area (in )
2oz Copper Mounting Pad Area (in )
Figure 15. SUPERSOT−3 Maximum Steady−State
Figure 16. Maximum Steady−State Drain
Power Dissipation vs. Copper Mounting Pad Area
Current vs. Copper Mounting Pad Area
1
D = 0.5
0.2
P
D
0.1
0.1
M
0.05
t
1
0.02
t
2
0.01
0.01
NOTES:
R
R
(t)= r(t) x R
ꢁ
ꢁ
JA
JA
Single Pulse
= 270°C/W
x Z (t)
ꢁ
JA
T − T = P
ꢁ
JA
J
A
DM
Duty Cycle, D = t / t
1
2
0.001
0.000
1
0.001
0.01
0.1
t , Time (s)
1
10
100
300
1
Figure 17. Transient Thermal Response Curve
NOTE: Characterization performed using the conditions described in note 1b.
Transient thermal response will change depending on the circuit board design.
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6
NDS352AP
SUPERSOT is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
CASE 527AG
ISSUE A
DATE 09 DEC 2019
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
XXX = Specific Device Code
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
M
= Month Code
XXXMG
G
= Pb−Free Package
G
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34319E
SOT−23/SUPERSOT−23, 3 LEAD, 1.4X2.9
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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