NFAQ0860L36T [ONSEMI]
Intelligent Power Module (IPM), 600 V, 8 A, Short lead;
| 型号： | NFAQ0860L36T |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), 600 V, 8 A, Short lead 电动机控制 |
| 文件： | 总14页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Power Module (IPM)
600 V, 8 A
NFAQ0860L36T
The NFAQ0860L36T is a fully−integrated inverter power stage
consisting of a high−voltage driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous motors (PMSM),
brushless−DC (BLDC) motors and AC asynchronous motors. The
IGBT’s are configured in a 3−phase bridge with separate emitter
connections for the lower legs for maximum flexibility in the choice of
control algorithm. The power stage has a full range of protection
functions including cross−conduction protection, external shutdown
and under−voltage lockout functions. An internal comparator and
reference connected to the over−current protection circuit allows the
designer to set the over−current protection level.
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Features
• Three−phase 8 A / 600 V IGBT Module with Integrated Drivers
• Compact 29.6 mm x 18.2 mm Dual In−Line Package
• Built−in Under Voltage Protection
DIP38 29.6x18.2
CASE 125BS
• Cross−conduction Protection
MARKING DIAGRAM
• ITRIP Input to Shut Down All IGBT’s
• Integrated Bootstrap Diodes and Resistors
• Thermistor for Substrate Temperature Measurement
• Shut Down Pin
NFAQ0860L36T
ZZZATYWW
• UL1557 Certification (File Number: E339285)
Typical Applications
• Industrial Pumps
• Industrial Fans
• Industrial Automation
• Home Appliances
NFAQ0860L36T = Specific Device Code
ZZZ
A
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
T
Y
WW
= Work Week
Device marking is on package top side
HIN(U)
LIN(U)
HIN(V)
LIN(V)
HIN(W)
LIN(W)
HS1
LS1
HS2
LS2
HS3
LS3
HS1
LS1
HS2
LS2
HS3
LS3
Three channel
half−bridge
driver
with
protection
circuits
ORDERING INFORMATION
Shipping
(Qty / Packing)
Device
Package
NFAQ0860L36T
DIP38
400 / Box
(Pb-Free)
Figure 1. Function Diagram
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
January, 2020 − Rev. 0
NFAQ0860L36T/D
NFAQ0860L36T
NFAQ0860L36T
RC filtering for
HINx and LINx
not shown.
Recommended
in noisy
VPN
P:38
From Op −amp
circuit
+
C1
CS
environments.
ITRIP:10
HV Ground
RSU
NU:17
NV:18
NW:19
HIN(U):3
HIN(V):4
HIN(W):5
LIN(U):6
LIN(V):7
LIN(W):8
From HV
Power
Source
RSV
RSW
To Op −amp
circuit
Vctr
from external
regulator
RSD
RP RTH
VB(U):34
+
+
+
SD:11
FAULT :9
TH2:14
Controller
VS(U),U:32
VB(V):28
VDD:2
VDD=15V
from external
regulator
VS(V),V:26
Motor
RCLR
CCLR
CFOD:12
VB(W):22
+
TH1:13
VSS:1
VS(W),W:20
LV Ground
Star connection to HV Ground
Figure 2. Application Schematic
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2
NFAQ0860L36T
Bootstrap
Bootstrap
Bootstrap
VB(U) (34)
VB(V) (28)
VB(W) (22)
P (38)
VDD (2)
VSS (1)
Sets latch time.
VS(W),W (20)
VS(V),V (26)
VS(U),U (32)
MΩ
For R=2
,
C=1nF, latch time
is 1.65ms (typical).
CFOD(12)
NU (17)
NV (18)
NW (19)
Level
Shifter
Level
Shifter
Level
Shifter
HIN(U) (3)
HIN(V) (4)
HIN(W) (5)
LIN(U) (6)
LIN(V) (7)
LIN(W) (8)
Logic
Logic
Logic
TH1 (13)
TH2 (14)
VDD
undervoltage
shutdown
VDD
FAULT (9)
ITRIP (10)
SD (11)
Over current
protection
Internal Voltage
reference
Shutdown
Figure 3. Simplified Block Diagram
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NFAQ0860L36T
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
VSS
Description
Low−Side Common Supply Ground
2
VDD
Low−Side Bias Voltage for IC and IGBTs Driving
Signal Input for High−Side U Phase
3
HIN(U)
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
FAULT
ITRIP
SD
4
Signal Input for High−Side V Phase
5
Signal Input for High−Side W Phase
6
Signal Input for Low−Side U Phase
7
Signal Input for Low−Side V Phase
8
Signal Input for Low−Side W Phase
9
Fault output
10
11
12
13
14
17
18
19
20
22
26
28
32
34
38
Input for Over Current Protection
Shut Down Input
CFOD
TH1
Capacitor and Resistor for Fault Output Duration Selection
Thermistor Bias Voltage
TH2
Series Resistor for Thermistor
NU
Negative DC−Link Input for U Phase
NV
Negative DC−Link Input for V Phase
NW
Negative DC−Link Input for W Phase
VS(W), W
VB(W)
VS(V), V
VB(V)
VS(U), U
VB(U)
P
High−Side Bias Voltage GND for W phase IGBT Driving, Output for W Phase
High−Side Bias Voltage for W phase IGBT Driving
High−Side Bias Voltage GND for V phase IGBT Driving, Output for V Phase
High−Side Bias Voltage for V phase IGBT Driving
High−Side Bias Voltage GND for U phase IGBT Driving, Output for U Phase
High−Side Bias Voltage for U phase IGBT Driving
Positive DC−Link Input
NOTE: Pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36 and 37 are not present
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NFAQ0860L36T
Table 2. ABSOLUTE MAXIMUM RATINGS at T = 25°C (Note 1)
C
Parameter
Supply Voltage
Symbol
VPN
Conditions
P−NU,NV,NW, VPN (surge) < 500 V
P-U,V,W; U-NU; V-NV; W-NW
Rating
Unit
V
(Note 2)
450
Collector − Emitter Voltage
VCES
IC
600
V
Each IGBT Collector Current
P,U,V,W,NU,NV,NW terminal current
8
A
P,U,V,W,NU,NV,NW terminal current, Tc = 100°C
Tc = 25°C, Under 1 ms Pulse Width
Tc = 25°C, Per One Chip
4
A
Each IGBT Collector Current (Peak)
Corrector Dissipation
ICp
Pc
16
32
A
W
V
High−Side Control Bias voltage
VBS
VB(U)−VS(U), VB(V)−VS(V),
VB(W)−VS(W)
(Note 3)
−0.3 to +20.0
Control Supply Voltage
Input Signal Voltage
VDD
VIN
VDD−VSS
−0.3 to +20.0
V
V
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W) −
VSS
−0.3 to V
DD
FAULT Terminal Voltage
CFOD Terminal Voltage
SD Terminal Voltage
VFAULT
VCFOD
VSD
VITRIP
Tj
FAULT−VSS
CFOD−VSS
SD−VSS
−0.3 to V
−0.3 to V
−0.3 to V
V
V
DD
DD
DD
V
Current Sensing Input Voltage
Operating Junction Temperature
Storage Temperature
ITRIP−VSS
−0.3 to +10.0
150
V
_C
_C
_C
Nm
Vrms
Tstg
−40 to +125
−40 to +125
0.6
Module Case Operation Temperature
Tightening Torque
Tc
MT
Case mounting screws
Isolation Voltage
Viso
50 Hz sine wave AC 1 minute
(Note 4)
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
3. VBS=VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W)
4. Test conditions : AC2500V, 1 s
Table 3. RECOMMENDED OPERATING RANGES
Rating
Supply Voltage
Symbol
VPN
Conditions
P − NU, NV, NW
Min
0
Typ
280
15
Max
450
Unit
V
High−Side Control Bias
Voltage
VBS
VB(U) − VS(U), VB(V) − VS(V), VB(W) −
VS(W)
13.0
17.5
V
Control Supply Voltage
ON−state Input Voltage
OFF−state Input Voltage
PWM Frequency
VDD
VIN(ON)
VIN(OFF)
fPWM
VDD − VSS
14.0
3.0
0
15
−
16.5
5.0
0.3
20
−
V
V
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
−
V
1
−
kHz
ms
ms
Nm
Dead Time
DT
Turn−off to Turn−on (external)
ON and OFF
1
−
Allowable Input Pulse Width
Tightening Torque
PWIN
1
−
−
‘M3’ Type Screw
0.4
−
0.6
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NFAQ0860L36T
Table 4. ELECTRICAL CHARACTERISTICS at T = 25 _C, V
(VBS, VDD) = 15 V unless otherwise noted.
C
BIAS
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Power Output Section
Collector−Emitter Leakage Current
Collector−Emitter Saturation Voltage
V
= 600 V
ICES
−
−
−
−
−
−
−
−
100
3.0
−
mA
V
CE
IN = 5 V, IC = 8 A, Tj = 25 _C
IN = 5 V, IC = 4 A, Tj = 100 _C
IN = 0 V, IC = −8 A, Tj = 25 _C
IN = 0 V, IC = −4 A, Tj = 100 _C
Inverter IGBT Part (per 1/6 Module)
Inverter FRD Part (per 1/6 Module)
VCE(sat)
2.4
1.9
2.1
1.6
−
V
2.7
−
V
FWDi Forward Voltage
VF
V
Rth(j−c)Q
Rth(j−c)F
3.9
7.3
_C/W
_C/W
Junction to Case Thermal Resistance
−
Switching Character
t
−
−
−
−
−
−
−
−
−
−
0.4
0.4
1.1
1.1
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
Switching Time
IC = 8 A, VPN = 300 V, Tj = 25_C,
ON
Inductive Switching
t
OFF
Turn−on Switching Loss
Turn−off Switching Loss
Total Switching Loss
E
190
90
IC = 8 A, VPN = 300 V, Tj = 25_C
ON
E
OFF
E
TOT
−
280
100
50
−
Turn−on Switching Loss
Turn−off Switching Loss
Total Switching Loss
E
−
IC = 4 A, VPN = 300 V, Tj = 100_C
ON
OFF
TOT
E
E
E
−
150
25
−
Diode Reverse Recovery Energy
Diode Reverse Recovery Time
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
Driver Section
−
IC = 4 A, VPN = 300 V, Tj = 100_C,
REC
(di/dt set by internal driver)
t
140
Full Square
−
−
RR
IC = 16 A, V = 450 V
RBSOA
CE
V
CE
= 400 V, Tj = 100_C
SCSOA
4
−
ms
Quiescent VBS Supply Current
Quiescent VDD Supply Current
ON Threshold Voltage
VBS = 15 V, HIN = 0 V, per driver
IQBS
IQDD
−
−
0.07
0.95
−
0.4
3.0
2.5
−
mA
mA
V
VDD = 15 V, LIN = 0 V, VDD−VSS
VIN(ON)
VIN(OFF)
IIN+
−
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
OFF Threshold Voltage
Logic 1 Input Current
0.8
−
−
V
VIN = +3.3 V
VIN = 0 V
660
−
900
3
mA
mA
W
Logic 0 Input Current
IIN−
−
Bootstrap ON Resistance
FAULT Terminal Sink Current
Fault−Output Pulse Width
CFOD Threshold
IB = 1 mA
RB
−
500
2
−
FAULT: ON / VFAULT = 0.1 V
FAULT−VSS
CFOD−VSS
IoSD
−
−
mA
ms
V
tFOD
1.1
−
1.65
8
2.2
−
VCFOD
VSD+
−
−
2.5
−
V
Shut Down Threshold
SD−VSS
VSD−
0.8
0.44
−
−
V
ITRIP Trip Level
ITRIP−VSS
VITRIP
tITRIP
tITRIPBL
UVBSR
UVBSD
UVBSH
UVDDR
UVDDD
UVDDH
0.49
1.1
350
11.1
10.9
0.2
11.1
10.9
0.2
0.54
−
V
ITRIP to Shutdown Propagation Delay
ITRIP Blanking Time
ms
ns
V
250
10.3
10.1
−
−
Reset Level
Detection Level
Hysteresis
11.9
11.7
−
High−Side Control Bias Voltage Under−
Voltage Protection
V
V
Reset Level
Detection Level
Hysteresis
10.3
10.1
−
11.7
11.5
−
V
Supply Voltage Under−Voltage Protection
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NFAQ0860L36T
TYPICAL CHARACTERISTICS
Figure 4. VCE versus IC for Different Temperatures
Figure 5. VF versus IF for Different Temperatures
(VDD = 15 V)
Figure 6. EON versus IC for Different Temperatures
Figure 7. EOFF versus IC for Different Temperatures
Figure 8. Thermal Impedance Plot (IGBT)
Figure 9. Thermal Impedance Plot (FRD)
Figure 10. Turn−on Waveform Tj = 1005C, VCC = 300 V
Figure 11. Turn−off Waveform Tj = 1005C, VCC = 300 V
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NFAQ0860L36T
APPLICATIONS INFORMATION
Input / Output Timing Chart
HIN is disabled until LIN receives input (Note 5)
VBS undervoltage protection reset signal
HIN
LIN
VDD undervoltage protection reset voltage (Note2)
VBS undervoltage protection reset voltage(Note3)
VDD
VB(U), VB(V), VB(W)
VIT w0.54V
( Note 4)
ITRIP
VIT < 0.44V
FAULT driven output
(with pull−up)
SD driven input
(with pull−up)
Cross−conduction prevention period(Note1)
Upper IGBT
Gate Drive
Lower IGBT
Gate Drive
Automatic reset after protection(Fault−Output Pulse Width)
NOTES:
1. This section of the timing diagram shows the effect of cross−conduction prevention.
2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go
low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.
3. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output
U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBTs are turned off. Normal operation
resumes later after the over−current condition is removed.
5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN
input before enabling the driver for the HIN signal.
Figure 12. Input / Output Timing Chart
Table 5. INPUT / OUTPUT LOGIC TABLE
INPUT
ITRIP
OUTPUT
Low side IGBT
HIN
H
LIN
L
SD
H
H
H
H
X
High side IGBT
ON (Note 5)
OFF
U,V,W
FAULT
OFF
OFF
OFF
OFF
ON
L
L
L
L
H
L
OFF
ON
P
L
H
L
NU,NV,NW
L
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
High Impedance
H
H
X
OFF
X
OFF
X
X
L
OFF
OFF
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NFAQ0860L36T
Table 6. THERMISTOR CHARACTERISTICS
Parameter
Resistance
Symbol
Condition
Min
99
Typ
100
5.38
4250
−
Max
101
Unit
kW
kW
K
R
Tth = 25_C
Tth = 100_C
25
R
5.18
4208
−40
5.60
4293
+125
100
B−Constant (25 to 50_C)
B
Temperature Range
_C
Figure 13. Thermistor Resistance versus Thermistor Temperature
Figure 14. Thermistor Voltage versus Thermistor Temperature
Conditions: RTH = 39 kW, Pull−up Voltage 5.0 V (see Figure 2)
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NFAQ0860L36T
FAULT Pin
Calculation of Bootstrap Capacitor Value
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS: Bootstrap power supply.
15 V is recommended.
• QG: Total gate charge of IGBT at VBS = 15 V.
8 nC
• UVLO: Falling threshold for UVLO.
Specified as 12 V.
• IDMAX: High side drive power dissipation.
Specified as 0.4 mA
• TONMAX: Maximum ON pulse width of high side
IGBT.
The FAULT output is an open drain output requiring a
pull−up resistor. If the pull−up voltage is 5 V, use a pull−up
resistor with a value of 6.8 kW or higher. If the pull−up
voltage is 15 V, use a pull−up resistor with a value of 20 kW
or higher. The FAULT output is triggered if there is a VDD
undervoltage or an overcurrent condition.
Under−voltage Protection
If VDD goes below the VDD supply under−voltage
lockout falling threshold, the FAULT output is switched on.
The FAULT output stays on until VDD rises above the VDD
supply under−voltage lockout rising threshold. After VDD
has risen above the threshold to enable normal operation, the
driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal.
Capacitance calculation formula:
Overcurrent Protection
CB = (QG + IDMAX * TONMAX) / (VBS − UVLO)
An over−current condition is detected if the voltage on the
ITRIP pin is larger than the reference voltage. There is a
blanking time of typically 350 ns to improve noise
immunity. After a shutdown propagation delay of typically
1.1 ms, the FAULT output is switched on. The FAULT output
is held on for a time determined by the resistor and capacitor
connected to the CFOD pin. If RCLR = 2 MW and CCLR =
1 nF, the FAULT output is switched on for 1.65 ms (typ.)
because the FAULT pin goes back to high impedance when
CFOD is higher than 8 V (typ.).
CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the
range of 1 to 47 mF, however, the value needs to be verified
prior to production. When not using the bootstrap circuit,
each high side driver power supply requires an external
independent power supply.
The internal bootstrap circuit uses a MOSFET. The turn
on time of this MOSFET is synchronized with the turn on of
the low side IGBT. The bootstrap capacitor is charged by
turning on the low side IGBT.
The over−current protection threshold should be set to be
equal or lower to 2 times the module rated current (Io).
An additional fuse is recommended to protect against
system level or abnormal over−current fault conditions.
If the low side IGBT is held on for a long period of time
(more than one second for example), the bootstrap voltage
on the high side MOSFET will slowly discharge.
Capacitors on High Voltage and VDD Supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high frequency
capacitor is between 100 nF and 10 mF.
100
10
1
SD Pin
The SD terminal pin is used to enable or shut down the
built−in driver. If the voltage on the SD pin rises above the
VSD+ voltage, the output drivers are enabled. If the voltage
on the SD pin falls below the VSD− voltage, the drivers are
disabled.
0.1
0.01
0.1
1
10
100
1000
Tonmax (ms)
Minimum Input Pulse Width
When input pulse width is less than 1 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
Figure 15. Bootstrap Capacitance versus Tonmax
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NFAQ0860L36T
TEST CIRCUITS
• ICES
34
32
ICE
VBS=15V
VBS=15V
VBS=15V
VDD=15V
U+
38
32
V+
38
26
W+
38
U−
32
17
V−
26
18
W−
20
A
A
A
B
28
26
20
19
VCE
U+, V+, W+ : High side phase
U−, V−, W− : Low side phase
22
20
2,9,11,12
B
1,10,17,18,19
Figure 16. Test Circuit for ICE
• VCE(sat) (Test by pulse)
U+
38
32
3
V+
38
26
4
W+
38
20
5
U−
32
17
6
V−
26
18
7
W−
20
19
8
34
VBS=15V
VBS=15V
VBS=15V
A
B
C
A
32
28
26
V
IC
22
20
VCE(sat)
2,9,11,12
VDD=15V
5V
C
B
1,10,17,18,19
Figure 17. Test Circuit for VCE(SAT)
• VF (Test by pulse)
U+
38
32
V+
W+
38
U−
32
17
V−
26
18
W−
20
A
B
38
26
A
20
19
V
VF
B
Figure 18. Test Circuit for VF
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NFAQ0860L36T
• RB (Test by pulse)
U+
2
V+
2
W+
2
A
B
A
B
C
34
6
28
7
22
8
V
IB
VB
2,9,11,12
VDD=15V
5V
(RB)
C
1,10,17,18,19
Figure 19. Test Circuit for RB
• IQBS, IQDD
VBS U+
VBS V+
28
VBS W+
22
V
DD
IQBS
A
B
34
32
2
A
A
A
B
VBSx=15V
26
20
1
IQDD
VDD=15V
2
9,11,12
1,10
Figure 20. Test Circuit for ID
• Switching Time (The circuit is a representative example of the Inverter Low side U phase.)
34
32
VBS=15V
VBS=15V
VBS=15V
VDD=15V
38
32
Input Signal
(0 to 5V)
28
26
CS
22
20
90%
lo
10%
2,9,11,12
6
17
Input Signal
tON
tOFF
Io
1,10,17,18,19
Figure 21. Test Circuit for Switching Time
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP38, 29.60x18.20x7.70, 1.00P (EP−4)
CASE 125BS
ISSUE B
DATE 26 APR 2023
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXXXXXXXXXXXXX
ZZZATYWW
AT
Y
= Assembly & Test Location
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
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