NFCS1060L3TT [ONSEMI]
Intelligent Power Module (IPM), PFC Combo, 600V, 10A;
| 型号： | NFCS1060L3TT |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), PFC Combo, 600V, 10A 功率因数校正 |
| 文件： | 总17页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NFCS1060L3TT
2-in-1 PFC and Inverter
Intelligent Power Module
(IPM), 600 V, 10 A
The NFCS1060L3TT is a fully−integrated PFC and inverter power
stage consisting of a high−voltage driver, six motor drive IGBT’s, one
PFC SJ−MOSFET, one PFC SiC−SBD for rectifier and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless−DC (BLDC) motors and AC asynchronous motors.
The IGBT’s are configured in a 3−phase bridge with separate
emitter connections for the lower legs for maximum flexibility in the
choice of control algorithm.
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An internal comparator and reference connected to the over−current
protection circuit allows the designer to set individual over−current
protection levels for the PFC and the inverter stages. Additionally, the
power stage has a full range of protection functions including
cross−conduction protection, external shutdown and under−voltage
lockout functions.
SIP35 56x25.8 / SIP2A−2
CASE 127DT
Features
• Simple Thermal Design with PFC and Inverter Stage in One Package
• Cross−Conduction Protection
• Integrated Bootstrap Diodes and Resistors
• UL1557 Certification (File Number: E339285)
MARKING DIAGRAM
Typical Applications
• Heat Pumps
• Home Appliances
• Industrial Fans
• Industrial Pumps
NFCS1060L3TT = Specific Device Code
ZZZ
A
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
T
Y
WW
= Work Week
Device marking is on package top side
HIN(U)
LIN(U)
HIN(V)
LIN(V)
HIN(W)
LIN(W)
IN(X)
HS1
LS1
HS2
LS2
HS3
LS3
HS1
HS2
HS3
Three channel
half−bridge
driver
ORDERING INFORMATION
+
single−ended
PFC driver
Shipping
(Qty / Packing)
Device
Package
with
protection
circuits
LS1
LS2
LS3
NFCS1060L3TT SIP35 56x25.8 /
8 / Tube
SIP2A−2
(Pb-Free)
Figure 1. Function Diagram
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2019 − Rev. 0
NFCS1060L3TT/D
NFCS1060L3TT
NFCS 1060L3TT
X (1)
P (16)
RC filtering for
From Op−amp
circuit
+
C1
CS
HIN(U, V, W), LIN(U, V, W)
and IN(X) not shown.
Recommended
ITRIP(P) (31)
RSPFC
NX (19)
NU (22)
ITRIP(I) (32)
in noisy environments.
RSU
RSV
RSW
From HV
Power
Source
HV Ground
HIN(U) (23)
HIN(V) (24)
HIN(W) (25)
LIN(U) (26)
LIN(V) (27)
LIN(W) (28)
IN(X) (29)
NV (21)
NW (20)
To Op−amp
circuit
To Op−amp
circuit
VB(U) (12)
U (13)
+
+
RP
RTH
Controller
VB(V) (8)
V (9)
FLTEN (30)
TH (33)
Motor
VDD Supply
+
VB(W) (4)
W (5)
VDD (34)
VSS (35)
+
From 15V
Power
LV Ground
Source
Figure 2. Application Schematic − Adjustable Option
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NFCS1060L3TT
X (1)
DB
DB
DB
RBS
RBS
RBS
VB(U) (12)
VB(V) (8)
VB(W) (4)
RBC
VDD (34)
VSS (35)
P (16)
W (5)
V (9)
PFC
Driver
IN(X) (29)
U (13)
NX (19)
NU (22)
NV (21)
NW (20)
Level
Shifter
Level
Shifter
Level
Shifter
HIN(U) (23)
HIN(V) (24)
HIN(W) (25)
LIN(U) (26)
LIN(V) (27)
LIN(W) (28)
Logic
Logic
Logic
VDD
undervoltage
shutdown
TH (33)
VDD
FLTEN (30)
ITRIP (I) (32)
VITRIP(I)
Reset after
delay
ITRIP (P) (31)
VITRIP(P)
Figure 3. Equivalent Block Diagram
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NFCS1060L3TT
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
X
Description
X Phase MOSFET Drain for PFC Inductor Connection
High−Side Bias Voltage for W Phase IGBT Driving
Output for W Phase and High−Side Bias Voltage GND for W Phase IGBT Driving
High−Side Bias Voltage for V Phase IGBT Driving
Output for V Phase and High−Side Bias Voltage GND for V Phase IGBT Driving
High−Side Bias Voltage for U Phase IGBT Driving
Output for U Phase and High−Side Bias Voltage GND for U Phase IGBT Driving
Positive DC−Link Input / Positive PFC Output Voltage
X Phase MOSFET Source for PFC
4
VB(W)
W
5
8
VB(V)
V
9
12
13
16
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VB(U)
U
P
NX
NW
Negative DC−Link Input for W Phase
NV
Negative DC−Link Input for V Phase
NU
Negative DC−Link Input for U Phase
HIN(U)
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
IN(X)
FLTEN
ITRIP(P)
ITRIP(I)
TH
Signal Input for High−Side U Phase
Signal Input for High−Side V Phase
Signal Input for High−Side W Phase
Signal Input for Low−Side U Phase
Signal Input for Low−Side V Phase
Signal Input for Low−Side W Phase
Signal Input for PFC X Phase
Fault Output / Enable
Input for Current Protection for PFC
Input for Current Protection for Inverter
Thermistor Bias Voltage
VDD
VSS
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground
NOTE: Pins 2, 3, 6, 7, 10, 11, 14, 15, 17 and 18 are not present.
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NFCS1060L3TT
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)
T
C
= 25°C unless otherwise noted
Rating
Symbol
Conditions
Value
Unit
PFC Section
PFC
MOSFET
Drain−Source Voltage
Drain Current (peak)
Drain Current
VDSS
IDP
ID
X − NX
600
30
20
10
83
600
30
20
10
32
10
V
A
A
A
W
V
A
A
A
W
A
Pulse Width < 100 ms, VBS, VDD = 15 V
Tc = 25 _C
Tc = 100 _C
Power Dissipation
PD1
VRRM
IFP
PFC Diode
Repetitive Reverse Voltage
Forward Current (peak)
Forward Current
P − X
Pulse Width < 100 ms
IF
Tc = 25 _C
Tc = 100 _C
Power Dissipation
Forward Current
PD2
ISD
MOSFET
Body Diode
Tc = 25 _C
Maximum AC Input Voltage
Maximum Output Voltage
Input AC Current (steady state)
Inverter Section
VAC
Vo
Single−Phase Full−Rectified
277
450
10
Vrms
V
In the Application Circuit (VAC = 200 V)
Iin
Arms
Supply Voltage
VPN
VCES
IC
P − NU, NV, NW surge < 500 V (Note 2)
P − U, V, W or U − NU, V − NV, W − NW
P, U, V, W, NU, NV, NW Terminal Current
450
600
10
V
V
A
A
Collector−Emitter Voltage
Each IGBT Collector Current
P, U, V, W, NU, NV, NW Terminal Current
5
at Tc = 100 _C
Each IGBT Collector Current (peak)
ICP
PC
P, U, V, W, NU, NV, NW Terminal
Current, Pulse Width 1 ms
20
29
A
Corrector Dissipation
Driver Section
IGBT per one chip
W
High−Side Control Bias Voltage
Control Supply Voltage
Input Signal Voltage
VBS
VDD
VIN
VB(U) − U, VB(V) − V, VB(W) − W,
VDD − VSS
−0.3 to +20.0
−0.3 to +20.0
−0.3 to VDD
V
V
V
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W), IN(X)
Fault Output Supply Voltage and Enable
Input
VFLTEN
FLTEN Terminal
−0.3 to VDD
V
ITRIP(I) Terminal Voltage
ITRIP(P) Terminal Voltage
Intelligent Power Module Total
Operating Junction Temperature
Storage Temperature
VITRIP(I)
VITRIP(P)
ITRIP(I) Terminal
ITRIP(P) Terminal
0.3 to +10.0
1.5 to +2.0
V
V
Tj
Tstg
Tc
150
−40 to +125
40 to +100
0.9
_C
_C
Module Case Operation Temperature
Tightening Torque
IPM Case Temperature
Case Mounting Screws
_C
MT
Viso
Nm
Isolation Voltage
60 Hz, Sinusoidal, AC 1 minute, Connec-
tion Pins to Heat Sink Plate (Note 4)
2000
Vrms
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminals.
3. VBS = VB(U) − U, VB(V) − V, VB(W) − W
4. Test conditions : AC 2500 V, 1 sec
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NFCS1060L3TT
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Rth(j−c) M
Rth(j−c) R
Rth(j−c) Q
Rth(j−c) F
Conditions
Min
−
Typ
1.3
3.2
3.5
6.8
Max
1.5
3.9
4.2
8.2
Unit
°C/W
°C/W
°C/W
°C/W
Junction to Case Thermal
Resistance
PFC MOSFET
PFC Diode
−
Inverter IGBT Part (per 1/6 Module)
Inverter FRD Part (per 1/6 Module)
−
−
5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
Table 4. RECOMMENDED OPERATING RANGES
Rating
Supply Voltage
Symbol
VPN
Conditions
P − NX, NU, NV, NW
Min
0
Typ
280
15
Max
400
Unit
V
High−Side Control Bias
Voltage
VBS
VB(U) − U, VB(V) − V, VB(W) − W
13.0
17.5
V
Control Supply Voltage
ON Threshold Voltage
OFF Threshold Voltage
PWM Frequency (PFC)
VDD
VDD − VSS (see table note below)
14.0
2.5
0
15
−
16.5
5.0
0.3
125
300
20
V
V
VIN(ON)
VIN(OFF)
fPWMp
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W), IN(X)
−
V
1
−
kHz
kHz
kHz
ms
No load, Duty = 0.5, Tc = 25 _C
1
−
PWM Frequency (Inverter)
Dead Time
fPWMi
DT
1
−
Turn−off to Turn−on (external)
ON and OFF
1
−
−
Allowable Input Pulse Width
Tightening Torque
PWIN
1
−
−
ms
‘M3’ Type Screw
0.6
−
0.9
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. ELECTRICAL CHARACTERISTICS
T
C
= 25 _C, VBIAS (VBS, VDD) = 15 V unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
PFC Section
Drain−Source Leakage Current
Reverse Leakage Current (PFC Diode)
Drain−Source On Resistance
VDSS = 600 V
IDSS
IR
−
−
−
−
−
−
−
−
−
−
−
100
500
0.18
−
mA
mA
W
VRRM = 600 V
ID = 20 A, Tj = 25 _C
ID = 10 A, Tj = 100 _C
IF = 20 A, Tj = 25 _C
IF = 10 A, Tj = 100 _C
IF = 10 A, Tj = 25 _C
ID = 20 A, VPN = 300 V, Tj = 25 _C
0.125
0.23
1.85
1.55
1.0
RDS(on)
W
Diode Forward Voltage (PFC Diode)
VF
2.6
−
V
V
MOSFET Body Diode Forward Voltage
Switching Time
VSD
ton
1.5
0.9
1.1
V
0.4
ms
ms
toff
0.6
Inverter Section
Collector−Emitter Leakage Current
Bootstrap Diode Leakage Current
Collector−Emitter Saturation Voltage
VCES = 600 V
ICES
IR(DB)
−
−
−
−
−
−
−
−
−
100
100
2.65
−
mA
mA
V
VRRM(DB) = 600 V
−
VCE(sat)
2.0
1.7
1.8
1.4
0.5
0.6
IC = 10 A, Tj = 25 _C
IC = 5 A, Tj = 100 _C
IF = 10 A, Tj = 25 _C
IF = 5 A, Tj = 100 _C
IC = 10 A, VPN = 300 V, Tj = 25 _C
V
FWDi Forward Voltage
Switching Times
VF
2.4
−
V
V
ton
toff
1.0
1.1
ms
ms
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NFCS1060L3TT
Table 5. ELECTRICAL CHARACTERISTICS (continued)
T
C
= 25 _C, VBIAS (VBS, VDD) = 15 V unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
−
Typ
295
Max
−
Unit
mJ
Turn−on Switching Loss
Turn−off Switching Loss
IC = 10 A, VPN = 300 V, Tj = 25 _C
E
ON
E
OFF
E
TOT
−
155
−
mJ
Total Switching Loss
−
450
−
mJ
Turn−on Switching Loss
Turn−off Switching Loss
IC = 5 A, VPN = 300 V, Tj = 100 _C
IC = 5 A, VPN = 300 V, Tj = 100 _C
E
−
195
−
mJ
ON
OFF
TOT
E
E
E
−
115
−
mJ
Total Switching Loss
−
310
−
mJ
Diode Reverse Recovery Energy
Diode Reverse Recovery Time
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
Allowable Offset Voltage Slew Rate
Driver Section
−
50
−
mJ
REC
trr
−
200
−
ns
−
IC = 20 A, VCES = 450 V
VCES = 400 V, Tj = 150 _C
U − NU, V − NV, W − NW
RBSOA
SCSOA
dv/dt
Full Square
−
5
−
ms
−50
−
50
V/ns
Quiescent VBS Supply Current
Quiescent VDD Supply Current
ON Threshold Voltage
VBS = 15 V, per driver
VDD = 15 V
IQBS
IQDD
−
−
0.08
0.85
−
0.4
2.4
−
mA
mA
V
HIN(U), HIN(V), HIN(W), LIN(U),
LIN(V), LIN(W), IN(X) − VSS
VIN(ON)
VIN(OFF)
2.5
−
OFF Threshold Voltage
−
0.8
143
2
V
Logic Input Current
VIN = +3.3 V
VIN = 0 V
I
−
100
−
mA
mA
V
IN+
Logic Input Current
I
−
IN−
Bootstrap Diode Forward Voltage
Bootstrap Circuit Resistance
IF(DB) = 0.1 A
VF(DB)
RBC
−
0.8
2
−
Resistor Value for Common Boot
Charge Line
−
−
W
Resister Values for Separate Boot
Charge Lines
RBS
−
10
−
W
FLTEN Terminal Sink Current
FLTEN Output Pulse Width
FLTEN Threshold
VFLTEN : ON / VFAULT = 0.1 V
IoSD
tFO
−
2
−
−
3.0
−
mA
ms
V
1.0
VEN ON−state Voltage
VEN OFF−state Voltage
ITRIP(I) − VSS
VEN(ON)
VEN(OFF)
VITRIPth(I)
VITRIPth(P)
tITRIP(I)
tITRIP(P)
tITRIPBL
2.5
−
−
−
0.8
0.54
−0.25
850
800
−
V
ITRIP(I) Threshold Voltage
0.44
0.37
490
440
290
10.5
0.49
−0.31
600
550
350
11.1
V
ITRIP(P) Threshold Voltage
ITRIP(P) − VSS
V
Shutdown Propagation Delay for INV
Shutdown Propagation Delay for PFC
ITRIP Blanking Time
ns
ns
ns
V
Supply Circuit Under−voltage Protection
Reset Level
UVBSR
UVDDR
11.7
Supply Circuit Under−voltage Protection
Detection Level
UVBSD
UVDDD
10.3
0.14
10.9
0.2
11.5
−
V
V
Supply Circuit Under−voltage Protection
Hysteresis
UVBSHYS
UVDDHYS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NFCS1060L3TT
TYPICAL CHARACTERISTICS − PFC SECTION
T
J
= 25 °C
Figure 4. VDS versus ID for Different Temperatures
(VDD = 15 V)
Figure 5. PFC Diode VF versus IF for Different
Temperatures
Figure 6. EON versus ID for Different Temperatures
Figure 7. EOFF versus ID for Different Temperatures
Figure 8. Thermal Impedance Plot (PFC MOSFET)
Figure 9. Thermal Impedance Plot (PFC Diode)
Figure 10. Turn−on Waveform Tj = 1005C, VPN = 300 V
Figure 11. Turn−off Waveform Tj = 1005C, VPN = 300 V
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NFCS1060L3TT
TYPICAL CHARACTERISTICS − INVERTER SECTION
T
J
= 25 °C
Figure 12. VCE versus IC for Different Temperatures
(VDD/VBS = 15 V)
Figure 13. VF versus IF for Different Temperatures
Figure 14. EON versus IC for Different Temperatures
Figure 15. EOFF versus IC for Different Temperatures
Figure 16. Thermal Impedance Plot (IGBT)
Figure 17. Thermal Impedance Plot (FRD)
Figure 18. Turn−on Waveform Tj = 1005C, VPN = 300 V
Figure 19. Turn−off Waveform Tj = 1005C, VPN = 300 V
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NFCS1060L3TT
APPLICATIONS INFORMATION
Input / Output Timing Chart
VBS under−voltage protection reset signal
HIN
LIN
VDD under−voltage protection reset voltage (Note 2)
VBS under−voltage protection reset voltage (Note 3)
VDD
VBS
Voltage w0.54 V
(Note 4)
Voltage < 0.44 V
ITRIP(I)
ITRIP(P)
Voltage v−0.39 V
FLTEN
(with pull−up)
Cross−conduction prevention period (Note 1)
Upper IGBT
Gate Drive
Lower IGBT
Gate Drive
Automatic reset after protection (FAULT output pulse width)
NOTES:
1. This section of the timing diagram shows the effect of cross−conduction prevention.
2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go
low, switching off all six IGBTs and PFC MOSFET. When the voltage on VDD rises sufficiently, normal operation will resume.
3. This section shows that when the bootstrap voltage on VBS drops, the corresponding high side output U (V, W) is switched
off. When the voltage on VBS rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP(I) exceeds the threshold, all IGBTs and PFC MOSFET are turned off.
Normal operation resumes later after the over−current condition is removed. Similarly, when the voltage on ITRIP(P) ex-
ceeds the threshold, all IGBTs and PFC MOSFET are turned off. Normal operation resumes later after the over−current
condition is removed
5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN
input before enabling the driver for the HIN signal.
Figure 20. Input / Output Timing Chart
Table 6. INPUT / OUTPUT LOGIC TABLE
INPUT
ITRIP(I)
OUTPUT
Low side IGBT
HIN
H
LIN
L
ITRIP(P)
High side IGBT
ON (Note 5)
OFF
U,V,W
VFLTEN
OFF
OFF
OFF
OFF
ON
L
L
L
L
OFF
ON
P
L
H
L
NU,NV,NW
L
L
L
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
High Impedance
H
H
X
L
L
OFF
X
H
X
X
H
OFF
X
X
OFF
ON
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NFCS1060L3TT
Table 7. THERMISTOR CHARACTERISTICS
Parameter
Resistance
Symbol
Condition
Min
44.65
1.29
Typ
47
Max
49.35
1.53
Unit
kW
kW
K
R
Tc = 25_C
25
R
Tc = 125_C
1.41
4050
−
125
B−Constant (25−50_C)
−
−
B
4009.5
−40
4090.5
+125
Temperature Range
−
_C
Figure 21. Thermistor Resistance − Thermistor Temperature
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NFCS1060L3TT
Signal Inputs
Minimum Input Pulse Width
Each signal input has a pull−down resistor internally. An
additional pull−down resistor of between 2.2 kW and 3.3 kW
is recommended on each input to improve noise immunity.
When input pulse width is less than 1 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
Calculation of Bootstrap Capacitor Value
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS: Bootstrap power supply.
15 V is recommended.
FLTEN pin
The FLTEN pin is connected internally to an open−drain
FAULT output and an ENABLE input requiring a pull−up
resistor. If the pull−up voltage is 5 V, use a pull−up resistor
with a value of 6.8 kW or higher. If the pull−up voltage is
15 V, use a pull−up resistor with a value of 20 kW or higher.
The pulled up voltage in normal operation for the FLTEN
pin should be above 2.5 V, noting that it is connected to an
internal ENABLE input. The FAULT output is triggered if
there is a VDD under−voltage or an overcurrent condition on
either the PFC or inverter stages.
Driving the FLTEN terminal pin is used to enable or shut
down the built−in driver. If the voltage on the FLTEN pin
rises above the positive going FLTEN threshold, the output
drivers are enabled. If the voltage on the FLTEN pin falls
below the negative going FLTEN threshold, the drivers are
disabled.
• QG: Total gate charge of IGBT at VBS = 15 V.
12.7 nC
• UVLO: Falling threshold for UVLO.
Specified as 12 V.
• IDMAX: High side drive power dissipation.
Specified as 0.4 mA
• TONMAX: Maximum ON pulse width of high side
IGBT.
Capacitance calculation formula:
CB = (QG + IDMAX * TONMAX)/(VBS − UVLO)
Under−voltage Protection
CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the
range of 1 to 47 mF, however, the value needs to be verified
prior to production. When not using the bootstrap circuit,
each high side driver power supply requires an external
independent power supply.
If VDD goes below the VDD supply undervoltage lockout
falling threshold, the FAULT output is switched on. The
FAULT output stays on until VDD rises above the VDD
supply under−voltage lockout rising threshold. The
hysteresis is approximately 200 mV.
Overcurrent Protection
An over−current condition is detected if the voltage on the
ITRIP(I) or ITRIP(P) pins are exceed the reference voltage
(Refer to Table 6 − Input / Output Logic Table). There is a
blanking time of typically 350 ns to improve noise
immunity. After a shutdown propagation delay of typically
0.6 ms, the FAULT output is switched on.
The over−current protection threshold should be set to be
equal or lower to 2 times the module rated current (Io).
An additional fuse is recommended to protect against
system level or abnormal over−current fault conditions.
Capacitors on High Voltage and VDD supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high frequency
capacitor is between 100 nF and 10 mF.
Figure 22. Bootstrap Capacitance versus Ton−max
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12
NFCS1060L3TT
Table 8. MOUNTING INSTRUCTIONS
Item
Recommended Condition
Pitch
56.0 0.1 mm (Please refer to MECHANICAL CASE OUTLINE)
Screw
Diameter : M3
Screw head types: pan head, truss head, binding head
Washer
Plane washer
The size is D: 7 mm, d: 3.2 mm and t: 0.5 mm JIS B 1256
Heat sink
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : −50 to 100 mm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts IPM.
Torque
Grease
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.6 to 0.9 Nm on first screw
Final tightening : 0.6 to 0.9 Nm on second screw
Silicone grease.
Thickness : 100 to 200 mm
Uniformly apply silicone grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and compressibility
parameters have a strong influence on performance.
Figure 23. Mount IPM on a Heat Sink
Figure 24. Size of Washer
Figure 25. Uniform Application of Grease Recommended
Steps to mount an IPM on a heat sink
st
1 : Temporarily tighten maintaining a left/right balance.
nd
2
: Finally tighten maintaining a left/right balance.
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13
NFCS1060L3TT
TEST CIRCUITS
ICES,
IDSS,
IR
• ICES, IDSS, IR, IR(DB)
4
5
VBS=15V
A
A
Inverter High Side
Inverter Low Side
PFC
MOSFET
VBS=15V
VBS=15V
8
U
V
16
9
W
16
5
U
V
9
W
5
VCES,
9
VDSS,
VRRM
A
B
16
13
13
22
1
12
13
34
21
20
19
VDD=15V
B
Boot Strap Diode
V
PFC
Diode
35,19,20,21,22
U
W
4
A
12
35
8
16
1
Figure 26. Test Circuit for ICES, IDSS, IR
B
35
35
• VCE(sat), RDS(on) (Test by pulse)
VBS=15V
Inverter High Side
Inverter Low Side
4
5
PFC
MOSFET
U
V
16
9
W
16
5
U
V
9
W
5
A
VBS=15V
VBS=15V
8
A
B
C
16
13
23
13
22
26
1
9
21
27
20
28
19
29
12
13
34
30
C
24
25
IC,
ID
V
VCE(sat),
RDS(on)
VDD=15V
5V
B
35,19,20,21,22
Figure 27. Test Circuit for VCE(sat)
• VF, VF(DB), VSD (Test by pulse)
Inverter High Side
Inverter Low Side
U
V
16
9
W
16
5
U
V
9
W
5
A
A
B
16
13
13
22
V
21
20
IF
B
MOSFET
Body
Diode
Boot Strap Diode
PFC
Diode
U
V
8
W
4
Figure 28. Test Circuit for VF
A
12
34
16
1
1
B
34
34
19
• IQBS, IQDD
IQBS,
IQDD
A
A
VBS U
VBS V
VBS W
VDD
A
B
12
13
8
9
4
5
34
35
VBS,
VDD
B
Figure 29. Test Circuit for IQBS, IQDD
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14
NFCS1060L3TT
• VITRIP(I), VITRIP(P)
A
B
VITRIP(I) (U−)
VITRIP(P)
34
30
VDD=15V
A
B
C
D
13
22
26
32
1
V
Io
19
29
31
Input Signal
VSC
C
D
35, 19, 20, 21, 22
Input Signal
(0 to 5 V)
Figure 31. Test Circuit for VITRIP(I), VITRIP(P)
VSC
I
O
Figure 30.
• Switching Time (The circuit is a representative example of the Inverter Low side U phase.)
Inverter High Side
Inverter Low Side
VBS=15V
VBS=15V
VBS=15V
4
5
PFC
MOSFET
A
C
U
V
W
16
20
5
U
V
W
16
20
5
8
A
B
C
D
E
16
22
13
22
23
16
21
9
16
22
13
16
26
16
21
9
16
19
1
9
12
13
34
VPN
CS
D
B
21
24
20
25
16
27
16
28
16
29
VDD=15V
30
E
Input Signal
Input Signal
(0 to 5 V)
35,19,20,21,22
IC
Figure 33. Test Circuit for Switching Time
90%
10%
IC
ton
toff
Figure 32.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP35 56x25.8 / SIP2A−2
CASE 127DT
ISSUE A
DATE 05 MAR 2019
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXXXXXXXXXXXXX
ZZZATYWW
AT
Y
= Assembly & Test Location
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04875G
SIP35 56X25.8 / SIP2A−2
PAGE 1 OF 1
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