NID9N05BCL [ONSEMI]
Power MOSFET;
| 型号： | NID9N05BCL |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NID9N05ACL, NID9N05BCL
Power MOSFET
9.0 A, 52 V, N−Channel, Logic Level,
Clamped MOSFET w/ESD Protection
in a DPAK Package
www.onsemi.com
Benefits
V
I MAX
D
(Limited)
DSS
• High Energy Capability for Inductive Loads
• Low Switching Noise Generation
(Clamped)
R
TYP
DS(ON)
52 V
90 mW
9.0 A
Features
Drain
(Pins 2, 4)
• Diode Clamp Between Gate and Source
• ESD Protection − HBM 5000 V
• Active Over−Voltage Gate to Drain Clamp
M
PWR
Overvoltage
Protection
• Scalable to Lower or Higher R
DS(on)
Gate
(Pin 1)
• Internal Series Gate Resistance
R
G
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ESD Protection
Compliant
Applications
Source
(Pin 3)
• Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
MARKING
DIAGRAM
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
52−59
15
Unit
V
Drain−to−Source Voltage Internally Clamped
Gate−to−Source Voltage − Continuous
V
DSS
1
3
YWW
D9N
xxxxxG
V
GS
V
2
4
DPAK
CASE 369C
STYLE 2
Drain Current − Continuous @ T = 25°C
I
9.0
35
A
A
D
Drain Current − Single Pulse (t = 10 ms)
I
p
DM
Total Power Dissipation @ T = 25°C
P
1.74
−55 to 175
160
W
°C
mJ
A
D
Y
= Year
1 = Gate
2 = Drain
3 = Source
4 = Drain
Operating and Storage Temperature Range
T , T
J
stg
WW
xxxxx
G
= Work Week
= 05ACL or 05BCL
= Pb−Free Package
Single Pulse Drain−to−Source Avalanche
E
AS
Energy − Starting T = 125°C
J
(V = 50 V, I
= 1.5 A, V = 10 V,
DD
D(pk)
GS
R
= 25 W)
G
Thermal Resistance, Junction−to−Case
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
R
R
R
5.2
72
100
°C/W
°C
q
JC
JA
JA
ORDERING INFORMATION
q
q
†
Device
Package
Shipping
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
T
260
L
NID9N05ACLT4G
DPAK
2500/Tape & Reel
(Pb−Free)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
NID9N05BCLT4G
DPAK
(Pb−Free)
2500/Tape & Reel
2
1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in ).
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
2. When surface mounted to a FR4 board using minimum recommended pad
2
size, (Cu area 0.412 in ).
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
November, 2016 − Rev. 11
NID9N05CL/D
NID9N05ACL, NID9N05BCL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
V
(BR)DSS
(V = 0 V, I = 1.0 mA, T = 25°C)
52
50.8
−
55
54
−10
59
59.5
−
V
V
GS
D
J
(V = 0 V, I = 1.0 mA, T = −40°C to 125°C)
GS
D
J
Temperature Coefficient (Negative)
mV/°C
Zero Gate Voltage Drain Current
I
mA
DSS
(V = 40 V, V = 0 V)
−
−
−
−
10
25
DS
GS
(V = 40 V, V = 0 V, T = 125°C)
DS
GS
J
Gate−Body Leakage Current
I
mA
GSS
(V
GS
(V
GS
=
=
8 V, V = 0 V)
−
−
−
22
10
−
DS
14 V, V = 0 V)
DS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
GS(th)
(V = V , I = 100 mA)
1.3
−
1.75
−4.5
2.5
−
V
DS
GS
D
mV/°C
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
R
mW
DS(on)
(V = 4.0 V, I = 1.5 A)
−
−
−
70
67
153
175
−
90
95
181
364
1210
−
GS
D
(V = 3.5 V, I = 0.6 A)
GS
D
(V = 3.0 V, I = 0.2 A)
GS
D
(V = 12 V, I = 9.0 A)
GS
D
(V = 12 V, I = 12 A)
−
GS
D
Forward Transconductance (Note 3) (V = 15 V, I = 9.0 A)
g
FS
−
24
−
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
−
−
−
155
60
250
100
40
−
iss
Output Capacitance
Transfer Capacitance
Input Capacitance
C
oss
(V = 40 V, V = 0 V, f = 10 kHz)
DS
GS
C
25
rss
C
C
175
70
pF
ns
ns
ns
nC
iss
Output Capacitance
Transfer Capacitance
−
(V = 25 V, V = 0 V, f = 10 kHz)
oss
DS
GS
C
30
−
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
t
t
t
t
t
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
130
500
200
750
2000
1850
−
d(on)
Rise Time
t
r
(V = 10 V, V = 40 V,
GS
DD
I
D
= 9.0 A, R = 9.0 W)
G
Turn−Off Delay Time
Fall Time
1300
1150
200
d(off)
t
f
Turn−On Delay Time
Rise Time
d(on)
t
r
500
−
(V = 10 V, V = 15 V,
GS
DD
I
D
= 1.5 A, R = 2 kW)
G
Turn−Off Delay Time
Fall Time
2500
1800
120
−
d(off)
t
f
−
Turn−On Delay Time
Rise Time
−
d(on)
t
r
275
−
(V = 10 V, V = 15 V,
GS
DD
I
D
= 1.5 A, R = 50 W)
G
Turn−Off Delay Time
Fall Time
1600
1100
4.5
−
d(off)
t
f
−
Gate Charge
Q
T
Q
1
Q
2
7.0
−
(V = 4.5 V, V = 40 V,
GS
DS
1.2
I
D
= 9.0 A) (Note 3)
2.7
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NID9N05ACL, NID9N05BCL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Gate Charge
Q
T
Q
1
Q
2
−
−
−
3.6
1.0
2.0
−
−
−
nC
(V = 4.5 V, V = 15 V,
GS
DS
I
D
= 1.5 A) (Note 3)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 4.5 A, V = 0 V) (Note 3)
V
SD
−
−
−
0.86
0.845
0.725
1.2
−
−
V
S
GS
(I = 4.0 A, V = 0 V)
S
GS
(I = 4.5 A, V = 0 V, T = 125°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
700
200
500
6.5
−
−
−
−
ns
rr
(I = 4.5 A, V = 0 V,
dI /dt = 100 A/ms) (Note 3)
s
S
GS
t
a
t
b
Reverse Recovery Stored Charge
Q
mC
RR
ESD CHARACTERISTICS
Electro−Static Discharge
Capability
Human Body Model (HBM)
Machine Model (MM)
ESD
5000
500
−
−
−
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NID9N05ACL, NID9N05BCL
TYPICAL PERFORMANCE CURVES
18
16
14
12
10
8
18
6 V
V
= 10 V
GS
T = −55°C
T = 25°C
16
14
J
J
8 V
6.5 V
T = 25°C
5 V
T = 100°C
J
J
12
10
8
4.6 V
4.2 V
4 V
3.8 V
6
6
3.2 V
4
4
3.4 V
2.8 V
2
0
2
0
V
DS
≥ 10 V
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.4
0.35
0.3
0.5
0.4
I
= 4.5 A
D
T = 25°C
J
T = 25°C
V
GS
= 4 V
J
0.25
0.2
0.3
0.2
0.1
0
0.15
0.1
V
GS
= 12 V
0.05
0
2
4
6
8
10
12
0
2
4
6
8
10
12
14
16
18
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.5
1,000,000
100,000
10,000
I
V
= 9 A
D
V
GS
= 0 V
= 12 V
GS
2
T = 150°C
J
1.5
T = 100°C
J
1
1000
100
0.5
−50 −25
0
25
50
75 100 125 150 175
20
25
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
30
35
40
45
50
T , JUNCTION TEMPERATURE (°C)
J
V
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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4
NID9N05ACL, NID9N05BCL
TYPICAL PERFORMANCE CURVES
500
400
300
200
Frequency = 10 kHz
T = 25°C
J
V
GS
= 0 V
C
iss
C
oss
100
0
C
rss
0
10
20
30
40
50
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
5
4
3
2
50
40
10,000
1000
100
Q
T
V
= 40 V
= 9 A
= 10 V
DD
I
D
V
V
GS
GS
Q
Q
gs
gd
30
20
t
d(off)
t
f
t
r
I
= 9 A
T = 25°C
D
J
V
DS
10
0
1
0
t
d(on)
0
1
2
3
4
5
1
10
100
Q , TOTAL GATE CHARGE (nC)
g
R , GATE RESISTANCE (OHMS)
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
10
V
GS
= 0 V
T = 25°C
J
8
6
4
2
0
0.4
0.6
0.8
1.0
1.2
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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5
NID9N05ACL, NID9N05BCL
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C
qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
100
V
= 12 V
GS
10 ms
SINGLE PULSE
T
C
= 25°C
100 ms
10
1 ms
10 ms
dc
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
0.05
0.01
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
t
2
T
J(pk)
− T = P
R
q
(t)
JC
C
(pk)
SINGLE PULSE
0.0001
DUTY CYCLE, D = t /t
1
2
0.01
0.00001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 12. Thermal Response
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6
NID9N05ACL, NID9N05BCL
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
L4
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
b2 0.028 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2 0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3 0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW
SOLDERING FOOTPRINT*
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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