NIV6350MT1TXG [ONSEMI]
5 Volt Electronic eFuse;
| 型号： | NIV6350MT1TXG |
| 厂家： | 
ONSEMI |
| 描述： | 5 Volt Electronic eFuse |
| 文件： | 总10页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+5 Volt Electronic eFuse
NIS6350, NIV6350
The NIS6350 is a cost effective, resettable fuse which can greatly
enhance the reliability of a USB application from both catastrophic
and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits and to protect the input side
circuitry from reverse currents. It includes an overvoltage clamp
circuit that limits the output voltage during transients but does not shut
the unit down, thereby allowing the load circuit to continue its
operation.
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Features
• 85 mW Max R
WDFNW10, 3 x 3
CASE 515AB
DS(on)
• Integrated Reverse Current Protection
• Adjustable Output Current Limit Protection with Thermal Shutdown
MARKING DIAGRAM
• IEC61000−4−2 Level 4 ESD Protection for V up to 7 kV
bus
XXXXX
XXXXX
ALYWG
G
• Fast Response Overvoltage Clamp Circuit with Selectable Level
• Internal Undervoltage Lockout Circuit
• Digital Enable with Separate FLAG for Fault Identification
• Integrated Current Monitoring
• Both Latching and Auto−Retry Options Available
A
L
= Assembly Location
= Wafer Lot
• NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONNECTIONS
Typical Applications
• Automotive Infotainment
• USB 2.0/3.0/3.1 VBUS
• USB Type−C PD Charging
• Solid State Drives
1
V
V
SRC
SRC
Ilim
CC
CC
GND
N/C
I
EN
MON
• Mother Boards
Vc_SEL
FLAG
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2020 − Rev. 3
NIS6350/D
NIS6350, NIV6350
+3.3V
System
Power
NIV1161/NIV2161
Vcc
D−
D−
USB
Transceiver
IC
D+
D+
GND
USB 2.0
Connector
Vbus
+5V
System
Power
C
L
22μF
47μF
C
IN
Vcc
Vcc
Source
Source
GND
Rlim
GND
Ilim
EN
NIS6350
RMON
1kΩ
1 μF
Imon
Enable
FLAG
Vc_SEL
FLAG
Floating or
Grounded
Figure 1. Typical USB 2.0 Application Circuit
VCC
EN
EN
Reverse
Current
FLAG
FLAG
Charge
Pump
Thermal
Shutdown
Source
UVLO
Current
Limit
Current
Sense
Voltage
Clamp
Vc_SEL
Ilim
Imon
GND
Figure 2. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1, 2
3
V
Positive input voltage to the device. (Low ESR capacitor of minimum 47 mF from V to GND is required)
CC
CC
GND
Negative input voltage to the device. This is used as the internal reference for the IC.
4
I
This pin can be used to monitor the output current by using an external pull−down resistor and de−coupling
capacitor.
MON
5
6
Vc_SEL
FLAG
The Vc_SEL pin allows the overvoltage clamp to be set at either a 5.6 V or 6.2 V minimum.
If a thermal fault occurs, the voltage on this pin will go to a low state to signal a monitoring circuit that the
device is in thermal shutdown.
7
EN
When this pin is pulled low the eFuse is turned off. It can be used to enable or disable the output of the
device by pulling it to ground using an open drain or open collector device, as it has an internal pull−up.
8
Ilim
A resistor between this pin and the source pin sets the overload and short circuit current limit levels.
Source of the internal power FET and the output terminal of the fuse
9, 10
11
Source
N/C (EP)
(Exposed Pad) This pad to be used as heatsink only with no electrical connection. It should be connected
to a large area of copper on the PCB, or to the PCB’s GND plane.
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2
NIS6350, NIV6350
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (V to GND)
V
−0.3 to +10
−0.3 to +10
−0.3 to +20
−0.3 to +20
−0.3 to 5
CC
CC
V
Transient (100 ms)
Output Voltage, operating, steady−state (SRC to GND)
Voltage range on ILIM pin
V
OUT
V
V
V
ILIM
Voltage range on Enable pin
V
EN
V
Voltage range on FLAG pin
V
FLAG
−0.3 to 6
V
Voltage range on all other pins
−0.3 to 5
V
Electrostatic Discharge
ESD
kV
Human Body Model (All pins)
Charged Device Model (All pins)
2
1
7
IEC61000−4−2 Contact (Source pins, with 22 mF C
condition)
SOURCE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL RATINGS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Air
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
q
95
°C/W
JA
2
Thermal Characterization Parameter, Junction−to−Lead
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
y
21
13
°C/W
°C/W
J−L
J−B
2
Thermal Characterization Parameter, Junction−to−Board
y
y
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Top
5
°C/W
J−T
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Total Continuous Power Dissipation @ T = 25°C
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Derate above 25°C
P
1.3
W
A
max
2
10.4
mW/°C
°C
Operating Ambient Temperature Range
Operating Junction Temperature Range
Non−operating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
−40 to 125
−40 to 150
−55 to 155
260
A
T
°C
J
T
STG
°C
T
°C
L
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3
NIS6350, NIV6350
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V = 5 V, C = 22 mF, R
= 15 W, T = −40 to 125°C)
A
CC
L
limit
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
Delay Time (enabling of chip to ID = 100 mA with 5 W resistive load)
T
1500
36
ms
dly
ON Resistance (Note 1)
R
85
mW
DS(on)
T = 140°C (Note 2)
J
58
Continuous Current T = 25°C (Note 2)
I
3
1
A
A
d
Off State Leakage (V = 5 V, EN = 0)
I
mA
in
OFF_LEAK
THERMAL LATCH
Shutdown Temperature (Note 3)
UNDER/OVERVOLTAGE PROTECTION
T
SD
150
175
200
°C
V
Maximum (V = 10 V with Vc_SEL pin floating)
V
out−clamp
6.2
5.6
6.9
6.1
11
7.5
6.5
20
V
V
OUT
OUT
CC
V
Maximum (V = 10 V with Vc_SEL pin pulled low (0V))
V
out−clamp
CC
Over Voltage Response Time
Undervoltage Lockout (Turn on, Voltage Going High)
UVLO Hysteresis
T
ms
V
vout−clamp
V
UVLO
3.4
3.8
0.35
2
4.6
V
Hyst
V
Under Voltage Response Time, VCC Falling, −5 V/ms
Under Voltage Response, VCC Rising, +5 V/ms
CURRENT LIMIT
T
uvlo
6
ms
ms
5
10
Current Limit
I
3.0
0.9
2.0
A
A
OL
Short Circuit Current
I
0.6
1.2
10
sc
Current Limit Response Time
REVERSE CURRENT LIMIT
T
ms
ilim
Reverse current blocking threshold (V −V ) (Note 4)
V
25
4
100
7
250
12
mV
out in
rev−th
Reverse current limit response time (dV /dt = −5 V/1 ms, 20 mF Load)
V
ms
in
rev−resp
SLEW RATE CONTROL
Slew Rate
SR
1
3
ms
CURRENT MONITOR
No Load Current (EN = high, I
= 0 A)
I
0
100
1.0
200
1.1
mA
load
mon−o
Gain (I − I
/I , @ I = 1 A, R
= 1 kW, C
= 1 mF)
I
0.9
mA/A
MON out
out
MON
MON
mon−gain
ENABLE
Logic Level Low (Output Disabled)
Logic Level High (Output Enabled) (Note 5)
High State Maximum Voltage
V
0.4
V
V
in−low
in−high
in−max
in−low
V
V
1.1
2
5
V
Logic Low Sink Current (V = 0 V)
I
15
10
35
50
mA
ms
EN
De−glitch Filter−delay
Filter−delay
FLAG
Fault Output Low Voltage (Fault Detected)
Fault Output High Voltage (No Fault Detected)
Logic High Source Current
Fault−low
Fault−high
0.7
5.0
V
V
2.5
Flag−I
60
mA
OH
Maximum Fan Out for Fault Signal (guaranteed by design)
Fan
2
Units
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4
NIS6350, NIV6350
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V = 5 V, C = 22 mF, R
= 15 W, T = −40 to 125°C)
A
CC
L
limit
Characteristics
Symbol
Min
Typ
Max
Unit
TOTAL DEVICE
Bias Current
Operational (I
I
mA
Bias
= 0 A, EN = 1, FLAG = high)
300
100
100
800
200
200
Load
Shutdown (EN = 0)
Thermal Fault
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Pulse test: Pulse width 300 s, duty cycle 2%
2. Verified by design.
3. eFuse is latched off until the En/Fault pin is pulled low and then released or a power on reset is applied to the device. If an auto−retry part
is used the device will automatically attempt to turn on once the internal temperature is less than 135°C.
4. Once the device has entered shutdown mode due to a reverse current event, it will re-enable its output when V > V
for at least 100 ms.
IN
OUT
The slew rate SR will be applied when the output is re-enabled.
5. A voltage level higher than Vin−high min (1.1 V) must be present to ensure a Logic Level High on the Enable pin.
7
6
5
4
I
OL
3
2
I
SC
1
0
4
5
6
7
8
9
10 11 12 13 14 15
(W)
R
limit
Figure 3. Current Limit vs. Rlimit for Direct Current Sensing
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5
NIS6350, NIV6350
APPLICATIONS INFORMATION
Basic Operation
be used in both short and long haul USB applications where
the VBUS voltage is adjusted for cable loss compensation.
This operation can be seen in Figure 5.
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The output voltage, which is controlled
by an internal dv/dt circuit, will slew from 0 V to the rated
output voltage in 1 ms.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The internal current limit circuit does not shut down the
part but will reduce the conductivity of the FET to maintain
a constant current at the internally set current limit level. The
input overvoltage clamp also does not shutdown the part, but
will limit the output voltage in the event that the input
exceeds the Vclamp level. This operation can be seen in
Figure 5.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage (VCC) and ground.
Thermal Protection
The NIS6350 includes an internal temperature sensing
circuit that senses the temperature on the die of the power
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. If a latching device
is used, output power can be restored by either recycling the
input power or toggling the enable pin. An auto−retry device
will automatically try to restore output power on its own.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events.
FLAG
The FLAG pin sends information to other devices
regarding the state of the chip. This pin is connected to an
internal pull−up so that it behaves as active high. The FLAG
pin remains at logic level high during normal operation and
gets pulled low and subsequently turns the device off when
one of the following conditions occurs:
1. EN pin set to Logic Level Low (Output Disabled)
2. Thermal fault
The VCC line can generate spike noise in fast transient
conditions such as short circuit, and this high peak can cause
over−stress and malfunction. To prevent this, a low ESR
capacitor (i.e. MLCC) of at least 47 mF is required.
3. UVLO − Undervoltage Lockout
4. Reverse current fault
Enable
Reverse Current Protection
The Enable feature provides a digital interface to control
the output of the eFuse. This pin is meant for push−pull
operation and is connected to an internal pull−up so that it
behaves as active high. When pulled low by an external
circuitry (below 0.5 V), the eFuse output is turned off.
Leakage current in this condition is described in the
electrical characteristics table.
The NIS6350 monitors and protects against reverse
current events, which can be the result of a malfunction in
the power supply or noise induced in the input voltage rail
under certain load characteristics (for example, when the
load is largely capacitive).
The protection mechanism disables the eFuse’s output
and triggers when the reverse voltage drop exceeds 100 mV
in magnitude and this condition remains for at least 4 ms.
The NIS6350 automatically re−enables its output once the
input voltage exceeds the output voltage for at least 100 ms.
IMON (Current Monitor)
The current monitor ”IMON” pin provides a small current
proportional to the main device current which is passing
through the device. This pin must have a decoupling
capacitor to filter out internal sampling noise. A resistor
connected between the IMON pin and GND converts the
IMON current into a GND referenced voltage. The
recommended resistor value of 1 kW will give about 1 V for
every 1 A of device current. The IMON voltage to output
current relationship is given in the below equation.
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
voltage exceeds the Vclamp voltage, the gate drive of the
main FET is reduced to limit the output. This is intended to
allow operation through transients while protecting the load.
If an overvoltage condition exists for many seconds, the
device may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
The Vc_SEL pin can be used to select the Vclamp level.
By allowing this pin to float high, the Vclamp value will be
set to 6.2 − 7.5 V. By pulling this pin low (to 0V), the Vclamp
value will be set to 5.6 − 6.5 V. This allows the NIS6350 to
Id
1000
ǒ Ǔ
V
MON + RMON
Although there is no maximum value that this resistor can
be, the value should be limited to 3 kW for best operation of
the IMON function. This pin can be floated if this function
is not needed thus saving a few mA of leakage current.
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6
NIS6350, NIV6350
Latching vs. Auto−Retry
device is allowed to pull−up the output to its normal, high
state.
This device features two options regarding its reset ability
after a thermal shutdown event. These are called latching
and auto−retry which are respectively marked MT1 and
MT2 as part number suffixes. Upon reaching a thermal
shutdown state, a latching device (MT1) will remain
shutdown with no power supplied to the output (SRC pins).
The only way to reset the device is to either perform a power
cycle on the VCC bus or pull the EN pin low (<0.4 V). By
doing either of these actions, the fault state is cleared and the
Instead of remaining in thermal shutdown, an Auto−retry
device (MT2) will automatically attempt to pull up the
output once the die temperature cools to < 135°C. If the fault
remains on the output during this attempt, the device will
once again enter a short period of current limiting that will
eventually lead to thermal shutdown for which the
auto−retry process will repeat indefinitely.
Latch version
Auto−Retry version
Figure 4. Output Short Circuit
Figure 5. Output Voltage Protection
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7
NIS6350, NIV6350
Figure 6. Reverse Current Protection
Figure 7. UVLO
ORDERING INFORMATION
Device
†
Shutdown Version
Marking
6350
Package
Shipping
NIS6350MT1TXG
*NIV6350MT1TXG
NIS6350MT2TXG
*NIV6350MT2TXG
Latching
Latching
6350
WDFNW10
(Pb−Free)
3000 / Tape and Reel
Auto−Retry
Auto−Retry
6350H
6350H
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW10, 3x3, 0.5P
CASE 515AB
ISSUE A
1
DATE 15 JUN 2018
SCALE 2:1
NOTES:
A
B
L3
L3
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURE TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
L
L
ALTERNATE
CONSTRUCTION
DETAIL A
E
PIN ONE
REFERENCE
EXPOSED
COPPER
MILLIMETERS
A4
A1
DIM MIN
NOM
0.75
0.03
MAX
0.80
0.05
A
A1
A3
A4
b
D
D2
E
0.70
0.00
0.20 REF
−−−
0.25
3.00
2.50
PLATING
A1
A4
TOP VIEW
ALTERNATE
CONSTRUCTION
0.10
0.20
2.90
2.40
2.90
1.70
−−−
0.30
3.10
2.60
3.10
1.90
DETAIL B
A
DETAIL B
0.10
0.08
C
C
3.00
1.80
A4
A3
C
C
E2
e
K
0.50 BSC
0.20 REF
0.40
L3
L
0.30
0.50
PLATED
SEATING
PLANE
NOTE 4
C
L
SIDE VIEW
D2
SURFACES
L3
0.05 REF
SECTION C−C
DETAIL A
GENERIC
10X
MARKING DIAGRAM*
5
1
1
XXXXX
XXXXX
ALYWG
G
E2
XXXXX = Specific Device Code
K
A
L
= Assembly Location
= Wafer Lot
10
6
10X b
e
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.10
0.05
C
C
A B
NOTE 3
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
10X
0.57
2.60
PACKAGE
OUTLINE
1.85 3.31
1
10X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30588G
WDFNW10, 3x3, 0.5P
PAGE 1 OF 1
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