NL17SZ125DTT1G [ONSEMI]
Non-Inverting 3-State Buffer; 非反相三态缓冲器
| 型号： | NL17SZ125DTT1G |
| 厂家： | 
ONSEMI |
| 描述： | Non-Inverting 3-State Buffer |
| 文件： | 总10页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NL17SZ125
Non-Inverting 3-State Buffer
The NL17SZ125 is a high performance non−inverting buffer operating
from a 1.65 V to 5.5 V supply.
Features
• Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V
PD
CC
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MARKING DIAGRAMS
• Designed for 1.65 V to 5.5 V V Operation
CC
• Overvoltage Tolerant Inputs and Outputs
• LVTTL Compatible − Interface Capability With 5.0 V TTL Logic
with V = 3.0 V
CC
• LVCMOS Compatible
M0 M G
SC−88A (SOT−353)
DF SUFFIX
G
• 24 mA Balanced Output Sink and Source Capability
CASE 419A
• Near Zero Static Supply Current Substantially Reduces System
Power Requirements
• 3−State OE Input is Active−Low
M0 MG
• Replacement for NC7SZ125
SOT−553
XV5 SUFFIX
CASE 463B
G
• Chip Complexity = 36 FETs
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
5
1
5
1
M0 MG
G
TSOP−5
DT SUFFIX
CASE 483
1
2
3
5
V
CC
OE
IN A
GND
M
UDFN6
1.0 x 1.0
1
CASE 517BX
4
OUT Y
M0
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(*Note: Microdot may be in either location)
Figure 1. Pinout (Top View)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
OE
EN
OUT Y
IN A
FUNCTION TABLE
OE Input
A Input
Y Output
Figure 2. Logic Symbol
L
L
L
H
X
L
H
Z
H
PIN ASSIGNMENT
X = Don’t Care
1
2
3
4
5
OE
IN A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
GND
OUT Y
V
CC
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2012 − Rev. 13
NL17SZ125/D
NL17SZ125
MAXIMUM RATINGS
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Units
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
V
V
OUT
DC Output Voltage
V
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
mA
mA
mA
mA
°C
IK
I
−50
OK
I
50
OUT
I
100
CC
T
−65 to +150
260
STG
T
L
T
J
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
°C
+150
°C
q
Thermal Resistance (Note 1)
SC−88A/SOT−553
TSOP−5
°C/W
JA
350
230
P
Power Dissipation in Still Air at 85°C
150
mW
V
D
MSL
Moisture Sensitivity
Level 1
F
Flammability Rating
Oxygen Index: 28 to 34
R
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
5.5
Units
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
0
5.5
V
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
ns/V
f
V
CC
V
CC
V
CC
V
CC
= 1.8 V 0.15 V
= 2.5 V 0.2 V
= 3.0 V 0.3 V
= 5.0 V 0.5 V
0
0
0
0
20
20
10
5.0
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2
NL17SZ125
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
1
100
110
120
130
140
20.4
9.4
1
10
100
1000
37,000
4.2
TIME, YEARS
17,800
2.0
Figure 3. Failure Rate vs. Time Junction Temperature
8,900
1.0
DC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Typ
−555C 3 T 3 1255C
A
V
(V)
CC
Min
Max
Min
Max
Symbol
Parameter
Units
Condition
V
IH
High−Level Input
Voltage
1.65 to 1.95 0.75 V
0.75 V
V
CC
CC
CC
CC
2.3 to 5.5
0.7 V
0.7 V
V
Low−Level Input
1.65 to 1.95
2.3 to 5.5
0.25 V
0.25 V
V
V
IL
CC
CC
CC
CC
Voltage
0.3 V
0.3 V
V
OH
High−Level Output
1.65
1.8
2.3
3.0
4.5
1.55
1.7
2.2
2.9
4.4
1.65
1.8
2.3
3.0
4.5
1.55
1.7
2.2
2.9
4.4
I
= −100 mA
OH
Voltage
V
IN
= V
IH
1.65
2.3
3.0
3.0
4.5
1.29
1.9
2.4
2.3
3.8
1.52
2.15
2.80
2.68
4.20
1.29
1.9
2.4
2.3
3.8
V
V
V
I
= −4 mA
= −8 mA
= −16 mA
= −24 mA
= −32 mA
OH
I
OH
I
OH
I
OH
I
OH
V
OL
Low−Level Output
1.65
1.8
2.3
3.0
4.5
0.0
0.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
OL
= 100 mA
Voltage
V
IN
= V
IL
1.65
2.3
3.0
3.0
4.5
0.08
0.10
0.15
0.22
0.22
0.24
0.30
0.40
0.55
0.55
0.24
0.30
0.40
0.55
0.55
I
OL
= 4 mA
= 8 mA
= 16 mA
= 24 mA
= 32 mA
OL
I
I
OL
I
OL
I
OL
I
Input Leakage Current
0 to 5.5
0.1
0.5
1.0
5.0
mA
mA
V
= 5.5 V or GND
IN
IN
I
3−State Output
Leakage
1.65 to 5.5
V
IN
= V or V
IH
OZ
IL
0 V ≤ V
≤ 5.5 V
OUT
I
Power Off Leakage
Current
0
1.0
1.0
10
10
mA
mA
V
V
= 5.5 V or
OUT
OFF
IN
= 5.5 V
I
Quiescent Supply
Current
5.5
V
IN
= 5.5 V or GND
CC
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3
NL17SZ125
AC ELECTRICAL CHARACTERISTICS (t = t = 3.0 ns)
R
F
T
= 255C
−555C 3 T 3 1255C
A
A
V
(V)
CC
Min Typ Max
Min
2.0
1.0
Max
10.5
8.0
Symbol
Parameter
Condition
Units
t
Propagation Delay
AN to YN
(Figures 4 and 5, Table 1)
ns
R = 1 MW
C = 15 pF
L
1.8 0.15
2.0
1.0
9.0
10
PLH
L
t
PHL
R = 1 MW
C = 15 pF 2.5 0.2
7.5
L
L
R = 1 MW
L
C = 15 pF 3.3 0.3
L
0.8
1.2
5.2
5.7
0.8
1.2
5.5
6.0
L
L
R = 500 W
C = 50 pF
R = 1 MW
L
C = 15 pF 5.0 0.5
L
0.5
0.8
4.5
5.0
0.5
0.8
4.8
5.3
L
L
R = 500 W
C = 50 pF
t
Output Enable Time
R = 250 W
C = 50 pF 1.8 0.15
2.0
1.8
1.2
0.8
2.0
1.5
0.8
0.3
7.6
8.0
9.5
8.5
6.2
5.5
10
2.0
1.8
1.2
0.8
2.0
1.5
0.8
0.3
10
9.0
6.5
5.8
10.5
8.5
6.0
5.0
ns
ns
PZH
PZL
L
L
t
(Figures 6, 7and 8, Table 1)
2.5 0.2
3.3 0.3
5.0 0.5
t
Output Disable Time
(Figures 6, 7and 8, Table 1)
R and R = 500 WC = 50 pF 1.8 0.15
L 1 L
PHZ
t
PLZ
2.5 0.2
3.3 0.3
5.0 0.5
8.0
5.7
4.7
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
2.5
Units
pF
C
IN
Input Capacitance
Output Capacitance
V
V
= 5.5 V, V = 0 V or V
I
CC
CC
CC
C
OUT
= 5.5 V, V = 0 V or V
2.5
pF
CC
I
C
PD
Power Dissipation Capacitance
(Note 5)
10 MHz, V = 3.3 V, V = 0 V or V
9
11
pF
CC
I
CC
CC
10 MHz, V = 5.5 V, V = 0 V or V
CC
I
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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4
NL17SZ125
OE = GND
V
CC
INPUT
OUTPUT
50%
A
Y
GND
t
PHL
t
PLH
C *
L
R
L
50% V
CC
Figure 4. Switching Waveform
*Includes all probe and jig capacitance.
A 1 MHz square input wave is recommended for
propagation delay tests.
Figure 5. tPLH or tPHL
2 V
CC
INPUT
INPUT
R = 500 W
1
V
CC
OUTPUT
R = 500 W
OUTPUT
C = 50 pF
L
C = 50 pF
L
R = 250 W
L
L
A 1 MHz square input wave is recommended for
propagation delay tests.
A 1 MHz square input wave is recommended for
propagation delay tests.
Figure 6. tPZL or tPLZ
Figure 7. tPZH or tPHZ
2.7 V
V
mi
V
mi
OE
0 V
t
t
PHZ
PZH
V
CC
V
− 0.3 V
OH
V
V
On
mo
≈ 0 V
t
t
PLZ
PZL
≈ 3.0 V
+ 0.3 V
On
mo
V
OL
GND
Figure 8. AC Output Enable and Disable Waveform
Table 1. OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F
W
V
CC
3.3 V + 0.3 V
1.5 V
2.7 V
1.5 V
1.5 V
2.5 V + 0.2 V
Symbol
V
mi
V
2
CC/
V
mo
1.5 V
V 2
CC/
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5
NL17SZ125
DEVICE ORDERING INFORMATION
Device
†
Package
Shipping
NL17SZ125DFT2G
SC−88A (SOT−353)
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NLV17SZ125DFT2G*
NL17SZ125XV5T2G
NL17SZ125DTT1G
NL17SZ125CMUTCG
SC−88A (SOT−353)
(Pb−Free)
SOT−553
(Pb−Free)
TSOP−5
(Pb−Free)
UDFN6, 1.0 x 1.0 x 0.35P
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
NL17SZ125
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NL17SZ125
PACKAGE DIMENSIONS
SOT−553, 5 LEAD
CASE 463B
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
D
−X−
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
L
5
4
3
E
−Y−
MILLIMETERS
INCHES
H
E
DIM
A
b
c
D
E
MIN
0.50
0.17
0.08
1.50
1.10
NOM
0.55
0.22
0.13
1.60
1.20
MAX
MIN
NOM
0.022
0.009
0.005
0.063
MAX
0.024
0.011
0.007
0.067
0.051
1
2
0.60
0.27
0.18
1.70
1.30
0.020
0.007
0.003
0.059
0.043
b 5 PL
c
e
0.047
M
0.08 (0.003)
X Y
e
L
0.50 BSC
0.20
1.60
0.020 BSC
0.008
0.10
1.50
0.30
1.70
0.004
0.059
0.012
0.067
H
0.063
E
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.0
0.0394
1.35
0.0531
0.5
0.5
0.0197 0.0197
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
NL17SZ125
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
SOLDERING FOOTPRINT*
2.50
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
NL17SZ125
PACKAGE DIMENSIONS
UDFN6, 1x1, 0.35P
CASE 517BX
ISSUE O
L1
NOTES:
L
A B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
PIN ONE
L3
REFERENCE
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
2X
0.08
C
MILLIMETERS
DIM MIN
MAX
0.65
0.05
A
A1
A3
b
0.50
0.00
0.13 REF
2X
0.08
C
TOP VIEW
EXPOSED Cu
MOLD CMPD
0.17
0.23
DETAIL B
0.05
C
C
D
E
e
L
L1
L3
1.00 BSC
1.00 BSC
0.35
A3
DETAIL B
A
0.20
−−−
0.26
0.40
0.15
0.33
ALTERNATE
CONSTRUCTION
0.05
A1
SEATING
PLANE
C
SIDE VIEW
e
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
6X
0.52
6X L
6X
0.25
3
1
1.20
PACKAGE
OUTLINE
1
6
4
6X b
0.35
M
0.07
0.05
C A
B
PITCH
M
C
NOTE 3
BOTTOM VIEW
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
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NL17SZ125/D
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