NLAS44599MN [ONSEMI]
Low Voltage Single Supply Dual DPDT Analog Switch; 低电压单电源双DPDT模拟开关
| 型号： | NLAS44599MN |
| 厂家： | 
ONSEMI |
| 描述： | Low Voltage Single Supply Dual DPDT Analog Switch |
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAS44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS44599 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
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vary across the full power−supply range (from V to GND).
MARKING
CC
The device has been designed so the ON resistance (R ) is much
DIAGRAMS
ON
lower and more linear over input voltage than R of typical CMOS
analog switches.
ON
16
16
1
1
AS
4459
ALYW
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
C
ALYW
QFN−16
MN SUFFIX
CASE 485G
Current
Previous
Part Marking*
Part Marking
The NLAS44599 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
*Previous releases of this device may be marked as
shown in this diagram.
• Channel Select Input Over−Voltage Tolerant to 5.5 V
• Fast Switching and Propagation Speeds
16
9
• Break−Before−Make Circuitry
16
NLAS
4459
ALYW
1
• Low Power Dissipation: I = 2 m A (Max) at T = 25°C
CC
A
• Diode Protection Provided on Channel Select Input
• Improved Linearity and Lower ON Resistance over Input Voltage
• Latch−up Performance Exceeds 300 mA
TSSOP−16
DT SUFFIX
CASE 948F
1
8
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
• Chip Complexity: 158 FETs
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
December, 2004 − Rev. 12
NLAS44599/D
NLAS44599
QFN−16 PACKAGE
FUNCTION TABLE
Select AB or CD
On Channel
L
H
NC to COM
NO to COM
16
15
14
13
COM D
NC A
1
SAB
See TSSOP−16
Switch Configuration
NO D
SCD
0
NO B
0
COM B
NC C
1
6
7
8
5
U
SELECT AB
COM A
X1
0
NO A
0
U
U
U
U
U
U
1
2
NC A
NO B
1
0/1
0
TSSOP−16 PACKAGE
3
0
COM B
2/3
X1
NC B
1
SELECT CD
NO C
0
NO A
1
2
3
16
V
0
CC
U
U
U
U
1
2
NC C
NO D
1
COM C
COM D
0/1
2/3
COM A
15 NC D1
0
U
3
NC D
1
14
13
12
11
10
9
COM D
NC A
1
Figure 2. IEC Logic Symbol
SELECT AB
4
5
6
7
8
NO D0
NO B
SELECT CD
0
COM B
NC C
1
NC B
1
COM C
GND
NO C
0
Figure 1. Logic Diagram
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2
NLAS44599
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
Positive DC Supply Voltage
*0.5 to )7.0
V
CC
IS
Analog Input Voltage (V or V
)
*0.5 v V v V )0.5
IS CC
NO
COM
Digital Select Input Voltage
*0.5 v V v)7.0
V
IN
I
I
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air
$50
mA
mW
IK
P
QFN−16
800
450
D
TSSOP−16
T
T
T
Storage Temperature Range
*65 to )150
260
°C
°C
°C
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
L
J
+150
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 30% − 35%
UL 94−V0 (0.125 in)
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
2000
200
V
Charged Device Model (Note 3)
1000
I
Latch−Up Performance
Thermal Resistance
Above V and Below GND at 125°C (Note 4)
$300
mA
Latch−Up
CC
q
QFN−16
80
°C/W
JA
TSSOP−16
164
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not implied. Functional
operationshould be restricted to the Recommended Operating Conditions.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
5.5
Unit
V
V
DC Supply Voltage
CC
IN
V
V
Digital Select Input Voltage
Analog Input Voltage (NC, NO, COM)
Operating Temperature Range
Input Rise or Fall Time, SELECT
GND
GND
*55
5.5
V
V
CC
V
IS
T
A
)125
°C
ns/V
t , t
V
CC
V
CC
= 3.3 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
r
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature 5C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
80
117.8
47.9
20.4
9.4
90
1
100
110
120
130
140
1
10
100
1000
37,000
4.2
TIME, YEARS
17,800
2.0
Figure 3. Failure Rate vs. Time Junction Temperature
8,900
1.0
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3
NLAS44599
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
*555C to 255C t855C t1255C
Symbol
Parameter
Condition
V
Unit
CC
V
IH
Minimum High−Level Input
Voltage, Select Inputs
2.0
2.5
3.0
4.5
5.5
1.5
1.9
1.5
1.9
1.5
1.9
V
2.1
2.1
2.1
3.15
3.85
3.15
3.85
3.15
3.85
V
IL
Maximum Low−Level Input
Voltage, Select Inputs
2.0
2.5
3.0
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
V
0.9
0.9
0.9
1.35
1.65
1.35
1.65
1.35
1.65
I
Maximum Input Leakage
Current, Select Inputs
V
= 5.5 V or GND
= 5.5 V or GND
IN
5.5
$0.2
$2.0
$2.0
m
A
IN
IN
I
I
Power Off Leakage Current
V
0
$10
$10
$10
m A
m A
OFF
Maximum Quiescent Supply
Current
Select and V = V or GND
5.5
4.0
4.0
8.0
CC
IS
CC
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
*555C to 255C t855C t1255C
Symbol
Parameter
Condition
V
Unit
CC
R
ON
Maximum “ON” Resistance
(Figures 17 − 23)
V
V
= V or V
2.5
3.0
4.5
5.5
85
45
30
25
95
50
35
30
105
55
W
IN
IL
IH
= GND to V
IS
CC
I
IN
I v 10.0 mA
40
35
R
ON Resistance Flatness
(Figures 17 − 23)
V
= V or V
IH
4.5
4
4
5
W
FLAT (ON)
IN
IL
I
IN
I v 10.0 mA
V
IS
= 1 V, 2 V, 3.5 V
I
I
NO or NC Off Leakage
Current (Figure 9)
V
V
= V or V
IH
5.5
5.5
1
1
10
10
100
100
nA
nA
NC(OFF)
IN
IL
or V = 1.0 V 4.5 V
COM
NO(OFF)
NO
NC
I
COM ON Leakage Current
(Figure 9)
V
V
V
V
= V or V
IL IH
COM(ON)
IN
1.0 V or 4.5 V with V floating or
NO
NO
COM
NC
1.0 V or 4.5 V with V floating
NO
= 1.0 V or 4.5 V
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4
NLAS44599
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
Guaranteed Maximum Limit
*555C to 255C
t855C
t1255C
V
(V)
V
IS
CC
(V) Min Typ* Max Min Max Min Max
Symbol
Parameter
Turn−On Time
Test Conditions
R = 300 WC, = 35 pF
Unit
t
t
t
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
5
5
2
2
23
16
11
9
35
24
16
14
5
5
2
2
38
27
19
17
5
5
2
2
41
30
22
20
ns
ON
L
L
(Figures 12 and 13)
(Figures 5 and 6)
Turn−Off Time
R = 300 WC, = 35 pF
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
7
5
4
3
12
10
6
1
1
1
1
15
13
9
1
1
1
1
18
16
12
11
ns
ns
OFF
BBM
L
L
(Figures 12 and 13)
(Figures 5 and 6)
5
8
Minimum Break−Before−Make
Time
V
IS
= 3.0 V (Figure 4)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
12
11
6
1
1
1
1
1
1
1
1
R = 300 WC, = 35 pF
L
L
5
Typical @ 25, V = 5.0 V
CC
pF
C
C
C
C
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
8
IN
or C
10
10
20
NO
NC
Common I/O (switch off)
COM
(ON)
Feedthrough (switch on)
*Typical Characteristics are at 25°C.
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Typical
V
CC
V
255C
145
170
175
Symbol
Parameter
Condition
Unit
BW
Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response (Figure 11)
V
V
= 0 dBm
3.0
4.5
5.5
MHz
IN
centered between V and GND
IN
CC
(Figure 7)
V
V
Maximum Feedthrough On Loss
V
V
= 0 dBm @ 100 kHz to 50 MHz
3.0
4.5
5.5
−3
−3
−3
dB
dB
pC
ONL
IN
centered between V and GND
IN
CC
(Figure 7)
Off−Channel Isolation (Figure 10)
f = 100 kHz; V = 1 V RMS
3.0
4.5
5.5
−93
−93
−93
ISO
IS
V
IN
centered between V and GND
CC
(Figure 7)
Q
Charge Injection Select Input to
Common I/O (Figure 15)
V
V
GND, F = 20 kHz
IN = CC to IS
t = t = 3 ns
r
3.0
5.5
1.5
3.0
f
R
= 0 W, C = 1000 pF
L
IS
Q = C * DV
L
OUT
(Figure 8)
THD
VCT
Total Harmonic Distortion THD +
Noise (Figure 14)
F
= 20 Hz to 100 kHz, R = Rgen = 600 W, C = 50 pF
%
IS
L
L
V
= 5.0 V sine wave
5.5
0.1
IS
PP
Channel−to−Channel Crosstalk
f = 100 kHz; V = 1 V RMS
dB
IS
V
centered between V and GND
5.5
3.0
−90
−90
IN
CC
(Figure 7)
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5
NLAS44599
V
CC
DUT
Input
GND
V
Output
CC
V
OUT
0.1 m F
t
BMM
300 W
35 pF
90%
90% of V
OH
Output
Switch Select Pin
GND
Figure 4. tBBM (Time Break−Before−Make)
V
CC
Input
50%
50%
90%
DUT
0 V
V
CC
Output
V
OUT
V
0.1 m F
OH
Open
90%
300 W
35 pF
Output
V
OL
Input
t
t
OFF
ON
Figure 5. tON/tOFF
V
CC
V
CC
Input
50%
50%
DUT
0 V
300 W
Output
V
OUT
V
OH
Open
35 pF
Output
10%
10%
V
OL
Input
t
t
ON
OFF
Figure 6. tON/tOFF
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6
NLAS44599
50 W
DUT
Reference
Input
50 W Generator
Transmitted
Output
50 W
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.
ISO
ONL
V
V
OUT
IN
ǒ Ǔfor V
V
V
= Off Channel Isolation = 20 Log
at 100 kHz
IN
ISO
V
OUT
= On Channel Loss = 20 Log ǒ Ǔfor V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
ONL
V
CT
= Use V
setup and test to all other switch analog input/outputs terminated with 50 W
ISO
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
V
CC
V
IN
Output
Open
GND
C
L
Output
Off
DV
OUT
Off
On
V
IN
Figure 8. Charge Injection: (Q)
100
10
1
I
COM(ON)
0.1
0.01
I
COM(OFF)
V
CC
= 5.0 V
85
I
NO(OFF)
0.001
−55
−20
25
70
125
TEMPERATURE (°C)
Figure 9. Switch Leakage vs. Temperature
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7
NLAS44599
+15
+10
+5
0
0
−20
−40
−60
−80
−100
1.0
Bandwidth
(ON−RESPONSE)
2.0
3.0
0
PHASE SHIFT
4.0
5.0
6.0
7.0
8.0
−5
Off Isolation
−10
−15
−20
−25
V
CC
= 5.0 V
T = 25°C
A
V
= 5.0 V
CC
9.0
−30
−35
100 300
T = 25°C
A
10.0
0.01
0.1
1
10
0.01
0.1
1
10
100 200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Off−Channel Isolation
Figure 11. Typical Bandwidth and Phase Shift
30
25
20
15
10
30
V
CC
= 4.5 V
25
20
15
10
5
t
(ns)
ON
t
ON
t
t
(ns)
3.5
OFF
5
0
OFF
0
−55
2.5
3
4
4.5
5
−40
25
Temperature (°C)
85
125
V
CC
(VOLTS)
Figure 12. tON and tOFF vs. VCC at 25°C
Figure 13. tON and tOFF vs. Temp
1
3.0
2.5
2.0
1.5
1.0
0.5
V
V
= 3.0 V
= 3.6 V
INpp
CC
V
CC
= 5 V
0.1
V
INpp
= 5.0 V
= 5.5 V
V
CC
V
CC
= 3 V
0
−0.5
0.01
1
10
FREQUENCY (kHz)
100
0
1
2
3
4
5
V
COM
(V)
Figure 14. Total Harmonic Distortion
Plus Noise vs. Frequency
Figure 15. Charge Injection vs. COM Voltage
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8
NLAS44599
100
80
60
40
20
0
100
10
V
= 2.0 V
CC
1
0.1
V
CC
= 2.5 V
0.01
V
= 3.0 V
V
= 3.0 V
CC
CC
V
= 4.0 V
5.0
0.001
0.0001
CC
V
= 5.0 V
V
CC
= 5.5 V
3.0
CC
0.00001
0.0
1.0
2.0
4.0
6.0
−40
−20
0
20
60
80
100
120
Temperature(°C)
V
IS
(VDC)
Figure 16. ICC vs. Temp, VCC = 3 V & 5 V
Figure 17. RON vs. VCC, Temp = 255C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
125°C
25°C
25°C
−55°C
−55°C
85°C
85°C
0.5
125°C
0.0
1.0
1.5
(VDC)
2.0
2.5
0.0
0.5
1.0
1.5
V (VDC)
IS
2.0
2.5
3.0
V
IS
Figure 18. RON vs Temp, VCC = 2.0 V
Figure 19. RON vs. Temp, VCC = 2.5 V
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
125°C
85°C
125°C
85°C
25°C
−55°C
25°C
−55°C
0
0
0.0
0.5
1.0
1.5
2.0
(VDC)
2.5
3.0
3.5
0.0 0.5 1.0 1.5 2.0
2.5 3.0 3.5 4.0 4.5
V
IS
(VDC)
V
IS
Figure 21. RON vs. Temp, VCC = 4.5 V
Figure 20. RON vs. Temp, VCC = 3.0 V
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9
NLAS44599
25
20
15
10
5
25
125°C
20
15
10
5
125°C
25°C
25°C
−55°C
−55°C
85°C
85°C
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
IS
(VDC)
V
IS
(VDC)
Figure 22. RON vs. Temp, VCC = 5.0 V
Figure 23. RON vs. Temp, VCC = 5.5 V
DEVICE ORDERING INFORMATION
Device Nomenclature
Device Order
Number
Circuit
Indicator
Device
Function
Package Tape & Reel
†
Suffix
Suffix
Technology
Package Type
QFN
Tape & Reel Size
NLAS44599MNR2
NLAS44599DTR2
NLAS44599MN
NLAS44599DT
NL
NL
NL
NL
AS
AS
AS
AS
44599
44599
44599
44599
MN
R2
R2
13−inch/2500 Unit
13−inch/2500 Unit
124 Unit Rail
DT
TSSOP
QFN
MN
DT
TSSOP
96 Unit Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
SpecificationsBrochure, BRD8011/D.
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10
NLAS44599
PACKAGE DIMENSIONS
QFN−16
MN SUFFIX
CASE 485G−01
ISSUE B
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
E
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
TOP VIEW
A3
b
0.20 REF
0.18
0.15
C
0.30
D
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
E2 1.65
1.85
e
K
L
0.50 BSC
(A3)
0.10
0.08
C
C
0.20
0.30
−−−
0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
SOLDERING FOOTPRINT
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
0.012
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
1.50
0.059
3.25
0.128
E2
e
16X K
12
1
16
13
0.30
16X b
0.012
0.50
0.02
0.10
0.05
C
C
A
B
BOTTOM VIEW
mm
inches
NOTE 3
ǒ
Ǔ
SCALE 10:1
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11
NLAS44599
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X K REF
M
S
S
0.10 (0.004)
T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T U
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
8
1
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
S
0.15 (0.006) T U
A
M
−V−
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
4.90
4.30
−−−
0.193
0.169
−−−
F
C
D
0.05
0.50
0.002
0.020
DETAIL E
F
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
−W−
J1
K
C
K1
L
0.10 (0.004)
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
DETAIL E
H
SEATING
PLANE
−T−
D
G
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