NLAS7222BMUTAG [ONSEMI]
High-Speed USB 2.0 (480 Mbps) DPDT Switches; 高速USB 2.0 （ 480 Mbps）的双刀双掷开关
| 型号： | NLAS7222BMUTAG |
| 厂家： | 
ONSEMI |
| 描述： | High-Speed USB 2.0 (480 Mbps) DPDT Switches |
| 文件： | 总10页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAS7222B, NLAS7222C
High-Speed USB 2.0
(480 Mbps) DPDT Switches
ON Semiconductor’s NLAS7222B and NLAS7222C are part of a
series of analog switch circuits that are produced using the company’s
advanced sub−micron CMOS technology, achieving industry−leading
performance.
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MARKING
Both the NLAS7222B and NLAS7222C are 2− to 1−port analog
switches. Their wide bandwidth and low bit−to−bit skew allow them to
pass high−speed differential signals with good signal integrity. Each
switch is bidirectional and offers little or no attenuation of the
high−speed signals at the outputs. Industry−leading advantages
include a propagation delay of less than 250 ps, resulting from its low
channel resistance and low I/O capacitance. Their high
channel−to−channel crosstalk rejection results in minimal noise
interference. Their bandwidth is wide enough to pass High−Speed
USB 2.0 differential signals (480 Mb/s).
DIAGRAM
UQFN10
CASE 488AT
XX M G
G
1
XX
=
Device Code
7222B = AS
7222C = AT
Date Code
M
G
=
=
Features
Pb−Free Device
• R is Typically 8.0 ꢀ at V = 3.3 V
ON
CC
(Note: Microdot may be in either location)
• Low Crosstalk: −30 dB @ 250 MHz
• Low Current Consumption: 1.0 ꢁ A
• Channel On−Capacitance: 8.0 pF (Typical)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
• V Operating Range: 1.65 V to 4.5 V
CC
• > 700 MHz Bandwidth (or Data Frequency)
• These are Pb−Free Devices
Typical Applications
• Differential Signal Data Routing
• USB 2.0 Signal Routing
Important Information
• Continuous Current Rating Through Each Switch 300 mA
• 8 kV I/O to GND ESD Protection
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 5
NLAS7222B/D
NLAS7222B, NLAS7222C
HSD1+
7
HSD1−
HSD2−
HSD1−
7
6
6
8
9
5
4
3
8
9
5
4
3
OE
OE
D−
HSD2+
V
CC
V
CC
GND
HSD2−
CONTROL
CONTROL
10
10
S
D+
S
GND
1
2
1
2
D+
D−
HSD1+
HSD2+
Figure 1. Pin Connections and Logic Diagram
Figure 2. Pin Connections and Logic Diagram
(NLAS7222B, Top View)
(NLAS7222C, Top View)
Table 1. PIN DESCRIPTION
Table 2. TRUTH TABLE
Pin
S
Function
Select Input
HSD1+,
HSD1−
HSD2+,
HSD2−
OE
S
1
0
0
X
0
1
OFF
ON
OFF
OFF
OFF
ON
OE
Output Enable
Data Ports
HSD1+, HSD1−, HSD2+,
HSD2−, D+, D−
MAXIMUM RATINGS
Symbol
Pins
Parameter
Value
−0.5 to +5.5
Unit
V
V
V
V
CC
Positive DC Supply Voltage
Analog Signal Voltage
CC
V
HSD1+, HSD1−
HSD2+, HSD2−
−0.5 to V + 0.3
IS
CC
D+, D−
−0.5 to +5.5
−0.5 to +5.5
50
V
IN
S, OE
Control Input Voltage, Output Enable Voltage
Positive DC Supply Current
V
I
V
CC
mA
°C
CC
T
Storage Temperature
−65 to +150
$300
S
I
I
I
HSD1+, HSD1−
HSD2+, HSD2−,
D+, D−
Analog Signal Continuous Current−Closed Switch
Analog Signal Continuous Current 10% Duty Cycle
Control Input Current, Output Enable Current
mA
IS_CON
HSD1+, HSD1−
HSD2+, HSD2−,
D+, D−
$500
mA
IS_PK
S, OE
$20
mA
IN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Pins
Parameter
Positive DC Supply Voltage
Min
1.65
GND
Max
Unit
V
V
V
4.5
CC
Analog Signal Voltage
V
HSD1+, HSD1−
HSD2+, HSD2−
V
CC
IS
D+, D−
GND
GND
−40
4.5
V
IN
S, OE
Control Input Voltage, Output Enable Voltage
Operating Temperature Range
V
CC
V
T
A
+85
°C
Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where
applicable. Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable.
These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions.
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2
NLAS7222B, NLAS7222C
ESD PROTECTION
Symbol
Parameter
Value
2.0
Unit
kV
ESD
ESD
Human Body Model − All Pins
Human Body Model − I/O to GND
8.0
kV
DC ELECTRICAL CHARACTERISTICS
CONTROL INPUT, OUTPUT ENABLE (Typical: T = 25°C, V = 3.3 V)
CC
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
V
IH
S, OE
Control Input, Output
Enable HIGH Voltage
(See Figure 3)
2.7
3.3
4.2
1.3
1.4
1.6
−
−
V
V
S, OE
S, OE
Control Input, Output
Enable LOW Voltage
(See Figure 3)
2.7
3.3
4.2
−
0.4
0.4
0.5
V
IL
I
IN
Control Input, Output
Enable Leakage
Current
0 ≤ V ≤ V
CC
1.65 − 4.5
−
−
1.0
ꢁ
A
IS
SUPPLY AND LEAKAGE CURRENT (Typical: T = 25°C, V = 3.3 V)
CC
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
I
V
CC
Quiescent Supply
Current
V
= V or GND; I
=
1.65 − 4.5
−
−
1.0
ꢁ
A
CC
IS
CC
OUT
0 A
I
V
CC
Increase in I
per
V = 2.6 V
IN
3.6
−
−
10
ꢁ
A
CCT
CC
Control Voltage
I
I
HSD1+, HSD1−
HSD2+, HSD2−
OFF State
0 ≤ V ≤ V
CC
1.65 − 4.5
−
−
−
−
1.0
1.0
ꢁ A
ꢁ A
OZ
IS
Leakage Current
D+, D−
Power OFF
Leakage Current
0 ≤ V ≤ 4.5 V
0
OFF
IS
HIGH SPEED ON RESISTANCE (Typical: T = 25°C, V = 3.3 V)
CC
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
R
On−Resistance
V
= 0 V to 0.4 V, I
=
=
=
2.7
3.3
4.2
−
9.0
8.0
7.0
12
10
ꢀ
ON
IS
ON
ON
ON
8 mA
8.0
R
On−Resistance
Flatness
V
= 0 V to 1.0 V, I
2.7
3.3
4.2
−
−
1.6
1.5
1.4
−
ꢀ
ꢀ
FLAT
IS
8 mA
ꢂ
R
On−Resistance
Matching
V
= 0 V to 0.4 V, I
2.7
3.3
4.2
1.05
0.85
0.65
−
ON
IS
8 mA
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3
NLAS7222B, NLAS7222C
DC ELECTRICAL CHARACTERISTICS (continued)
FULL SPEED ON RESISTANCE (Typical: T = 25°C, V = 3.3 V)
CC
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
= 0 V to V , I
8 mA
= 0 V to 1.0 V, I =
ON
V
CC
(V)
Unit
R
On−Resistance
V
=
CC ON
2.7
3.3
4.2
9.0
8.5
7.5
12
10.5
8.5
ꢀ
ON
IS
R
On−Resistance
Flatness
V
IS
2.7
3.3
4.2
1.6
1.5
1.4
ꢀ
ꢀ
FLAT
8 mA
= 0 V to V , I =
CC ON
ꢂ R
On−Resistance
Matching
V
IS
2.7
3.3
4.2
2.20
2.45
2.65
ON
8 mA
AC ELECTRICAL CHARACTERISTICS
TIMING/FREQUENCY (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF, f = 1 MHz)
CC
L
L
−405C to +855C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
t
Closed Turn−ON Time
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
−
14
30
ns
ON
to Open
t
Open to Turn−OFF Time
Closed
−
10
20
ns
ns
OFF
t
Break−Before−Make
Delay
3.0
4.4
7.0
BBM
BW
−3 dB Bandwidth
C = 5 pF
−
−
500
750
−
−
MHz
L
C = 0 pF
L
ISOLATION (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF, f = 1 MHz)
CC
L
L
−405C to +855C
Min
−
Typ
−22
−30
Max
−
Symbol
Pins
Parameter
Test Conditions
V
(V)
Unit
dB
CC
O
Open
OFF−Isolation
f = 250 MHz
f = 250 MHz
1.65 − 4.5
1.65 − 4.5
IRR
X
TALK
HSD1+ to Non−Adjacent
HSD1− Channel Crosstalk
−
−
dB
NLAS7222B CAPACITANCE (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF, f = 1 MHz)
CC
L
L
−405C to +855C
Min
−
Typ
3.0
8.0
Max
−
Symbol
Pins
Parameter
Test Conditions
= 0 V
Unit
pF
C
S, OE
Control Pin Input Capacitance
ON Capacitance
V
V
IN
CC
C
D+ to
HSD1+ or
HSD2+
= 3.3 V; OE = 0 V
S = 0 V or 3.3 V
−
−
pF
ON
CC
C
HSD1n or OFF Capacitance
HSD2n
V
= V = 3.3 V; OE = 0 V
−
4.5
−
pF
OFF
CC
IS
S = 3.3 V or 0 V
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4
NLAS7222B, NLAS7222C
NLAS7222C CAPACITANCE (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF, f = 1 MHz)
CC
L
L
−405C to +855C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
= 0 V
Unit
C
S, OE
Control Pin, Output Enable In-
put Capacitance
V
V
−
3.0
−
pF
IN
CC
C
D+ to
HSD1+ or
HSD2+
ON Capacitance
= 3.3 V; OE = 0 V
S = 0 V or 3.3 V
−
−
10
−
−
pF
pF
ON
CC
C
HSD1n or OFF Capacitance
HSD2n
V
CC
= V = 3.3 V; OE = 3.3 V
5.5
OFF
IS
S = 3.3 V or 0 V
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5
NLAS7222B, NLAS7222C
140
120
100
80
V
CC
= 4.2 V
60
V
CC
= 3.3 V
40
V
= 2.7 V
3.5
CC
20
0
0
0.5
1
1.5
2
2.5
3
4
4.5
V
IN
, (V)
Figure 3. ICC vs. VIN
V
CC
DUT
Input
GND
V
Output
CC
V
OUT
0.1 ꢁ F
50
ꢀ
35 pF
t
BMM
Output
50 % OF
DROOP
VOLTAGE
DROOP
Switch Select Pin
Figure 4. tBBM (Time Break−Before−Make)
V
CC
Input
50%
50%
90%
DUT
0 V
V
CC
Output
50
V
OUT
V
0.1 ꢁ F
OH
Open
90%
ꢀ
35 pF
Output
V
OL
Input
t
t
OFF
ON
Figure 5. tON/tOFF
V
CC
V
CC
Input
50%
50%
DUT
0 V
50
ꢀ
Output
V
OUT
V
OH
Open
35 pF
Output
V
10%
10%
OL
Input
t
t
ON
OFF
Figure 6. tON/tOFF
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6
NLAS7222B, NLAS7222C
50
ꢀ
DUT
Reference
Transmitted
Input
Output
50 ꢀ Generator
50
ꢀ
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss
is the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.
ISO
ONL
V
OUT
= Off Channel Isolation = 20 Logǒ Ǔfor V
V
V
at 100 kHz
IN
ISO
V
IN
OUT
V
= On Channel Loss = 20 Logǒ Ǔ for V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
= Use V setup and test to all other switch analog input/outputs terminated with 50
ONL
V
CT
ꢀ
ISO
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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7
NLAS7222B, NLAS7222C
APPLICATIONS INFORMATION
The low on resistance and capacitance of the NLAS7222B
(www.usb.org), the industry group responsible for defining
the USB certification requirements. The test patterns were
generated by a PC and MATLAB software, and were
inputted to the analog switch through USB connectors J1
(HSD1) or J2 (HSD2). A USB certified device was plugged
into connector J4 to function as a data transceiver. The high
speed and full speed tests used a flash memory device, while
the low speed tests used a mouse. Test connectors J3 and J5
provide a direct connection of the USB device and were used
to verify that the analog switch does not distort the data
signals.
provides for a high bandwidth analog switch suitable for
applications such as USB data switching. Results for the
USB 2.0 signal quality tests will be shown in this section,
along with a description of the evaluation test board. The
data for the eye diagram signal quality and jitter tests verifies
that the NLAS7222B can be used as a data switch in low, full
and high speed USB 2.0 systems.
Figures 8, 9 and 10 provide a description of the test
evaluation board. The USB tests were conducted per the
procedures provided by the USB Implementers Forum
Figure 8. Schematic of the NLAS7222B USB Demo Board
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8
NLAS7222B, NLAS7222C
Figure 9. Block Diagram of the NLAS7222B USB Demo Board
Figure 10. Photograph of the NLAS7222B USB Demo Board
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NLAS7222BMUTAG
AS
UQFN10
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NLAS7222BMUTBG
NLAS7222CMUTBG
AS
AT
UQFN10
(Pb−Free)
UQFN10
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NLAS7222B, NLAS7222C
PACKAGE DIMENSIONS
UQFN10, 1.4x1.8, 0.4P
CASE 488AT−01
ISSUE A
EDGE OF PACKAGE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L1
E
PIN 1 REFERENCE
DETAIL A
MILLIMETERS
Bottom View
DIM MIN
MAX
0.60
0.05
0.10
0.10
C
2X
A
A1
A3
b
0.45
0.00
(Optional)
0.127 REF
C
2X
0.15
0.25
MOLD CMPD
EXPOSED Cu
B
D
1.40 BSC
TOP VIEW
E
1.80 BSC
0.40 BSC
e
A
A3
0.05
0.05
C
L
0.30
0.50
0.15
0.60
0.00
0.40
L1
L3
A1
C
DETAIL B
Side View
(Optional)
10X
A1
SEATING
PLANE
MOUNTING FOOTPRINT
C
SIDE VIEW
1.700
0.0669
9 X
0.563
0.0221
5
3
e/2
e
9 X L
0.663
0.0261
6
1
0.200
0.0079
1
10
10 X
0.10 C A B
2.100
0.0827
L3
b
0.05 C
NOTE 3
BOTTOM VIEW
0.400
0.0157
PITCH
10 X
0.225
0.0089
mm
inches
ǒ
Ǔ
SCALE 20:1
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NLAS7222B/D
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