NLPS591MNTWG_技术文档

NLPS591

Fully-Configurable Port

Companion for Displays

The NLPS591 is a fully−configurable port companion for display

applications. The device supports 4 externally selectable modes: (1)

4−Ch autosensing logic level translator mode, (2) CRT mode, (3)

HDMI mode and (4) DisplayPort (DP) mode. The device provides

switchable power to the connected display and the level shifting

necessary for the different display modes. It also provides high−level

ESD protection on the connector side.

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Features

1

• Modes supported:

♦ 4−Ch Logic Level Translator (LT) Mode

♦ CRT Mode

WQFN16

CASE 488AP

♦ HDMI Mode

♦ DisplayPort (DP) Mode

MARKING DIAGRAM

• Wide V

Operating Range: 1.65 V to 5.5 V

• Wide V Range: 3.0 to 5.5 V (Power Modes)

CCA

IN

Wide V Range: 1.65 V to 5.5 V (Level Translator Mode)

IN

AJ M

G

• Low R

Load Switch: 300 mW @ V = 3.3 V

IN

DSON

• Soft−start Control for Load Switch

• Protection Provided: Overcurrent, Overvoltage, Backdrive

AJ

M

G

= Specific Device Code

= Date Code

= Pb−Free Package

• Power Consumption: < 10 mW with Load Switch On

Power Consumption: < 1 mW with Load Switch Off

• High Drive VESA−compliant Translator SYNC Level Translators in

CRT Mode

ORDERING INFORMATION

• Integrated Pull−ups for the Autosensing Bidirectional Translators

†

Device

Package

Shipping

• Low Input Capacitance for Translator Inputs: C < 10 pF

IN

NLPS591MNTWG WQFN16

3000 / Tape &

Reel

• Small, Space Saving Package

(Pb−Free)

♦ 1.8 mm x 2.6 mm WQFN16

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• Laptops, Desktops

• Tablets, SmartPhones

Important Information

• ESD Protection for All Pins

♦ Human Body Model (HBM) > 2000 V

1

Publication Order Number:

July, 2019 − Rev. 3

NLPS591/D

NLPS591

Figure 1. Function Diagram

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2

NLPS591

PINOUT DIAGRAM

Figure 2. WQFN16 (Top−Through View)

Table 1. PIN DESCRIPTIONS

Pin Function per Mode

Name

VIN

Number

LT

DP0

VIN

DP1

HDMI

VIN

CRT

VIN

1

VCC_I2C_1_B

VCC_I2C_0_B

“0”

VIN

AUX

2

3

AUX_A

“0”

−

“0”

CEC3V

“1”

−

MODE0

MODE1

AUX#

VCCA

CH4A

CH3A

CH2A

CH1A

CH1B

CH2B

CH3B

CH4B

GND

“1”

4

“0”

“1”

“0”

“1”

5

CH_EN

AUX_A#

VCCA

−

CH_EN

VCCA

CH_EN

6

VCCA

7

I2C_0_SDA_A

I2C_0_SCL_A

I2C_1_SDA_A

I2C_1_SCL_A

I2C_1_SCL_B

I2C_1_SDA_B

I2C_0_SCL_B

I2C_0_SDA_B

GND

DDC_DATA_A

DDC_CLK_A

HPD_A

−

DDC_DATA_A

DDC_CLK_A

HPD_A

CEC_A

CEC_B

HPD_B

DDC_CLK_B

DDC_DATA_B

GND

DDC_DATA_A

DDC_CLK_A

HSYNC_A

VSYNC_A

VSYNC_B

HSYNC_B

DDC_CLK_B

DDC_DATA_B

GND

8

−

9

HPD_A

−

10

11

12

13

14

15/EP*

16

CA_DET_B = 0

HPD_B

AUX_B

AUX_B#

GND

CA_DET_B = 1

HPD_B

DDC_CLK_B

DDC_DATA_B

GND

VOUT

−

VOUT

* EP – Exposed Pad for QFN−16 Package is connected to GND.

Table 2. MODE FUNCTION TABLE

Input

MODE0

MODE1

Operating Mode

0

1

0

1

0

1

Level Translator – LT (Default)

DisplayPort − DP

HDMI

CRT

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3

NLPS591

OPERATING MODES

Level Translator Mode – LT (Default Mode)

The function diagram is shown below. The A−side I/Os are

referred to VCCA (pin 6). The B−side I/Os are referred to

either VCC_I2C_1_B (pin 1) or VCC_I2C_0_B (pin 2).

When CH_EN = 0, the 4−ch level translator is disabled,

and the I/O pins (pins 7, 8, 9, 10, 11,12, 13, 14) go into

high−impedance.

When MODE0 = 0 and MODE1 = 0, the NLPS591 enters

level translator mode. In this mode, the power switch is

always off.

When CH_EN = 1, the device is configured as an

autosensing 4−channel bidirectional logic level translator.

Figure 3. Function Diagram − LT Mode

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4

NLPS591

DP Mode

When MODE0 = 0 and MODE1 = 1, the NLPS591 enters

DP (DisplayPort) mode. The device is configured as a

DP−compliant logic level translator for the control signals.

A power switch provides power to the connected display. An

unidirectional translator for HPD is provided.

A CA_DET_B input is provided to detect the use of an

HDMI dongle. When there is no HDMI dongle attached

(CA_DET_B = 0), the device goes into DP0 sub−mode,

where AUX and AUX# signals are passed. The function

diagram is shown below.

DP0 Sub−Mode

VIN

VOUT

1

16

Protection

Circuitry

CH_EN

Gate Driver

VCCA

CRT

HDMI

DP

MODE0 = 0

MODE1 = 1

CONTROL

3

4

LOGIC

LS

VCCA

6

CA_DET_B = 0

11

10 NOT USED

VBIAS

VCCA

1 MW

HPD_A

HPD_B

9

12

8

7

NOT USED

VCCA

100 kW

AUX_A

AUX_B

2

13

AUX_A#

GND

AUX_B#

14

5

15

100 kW

VOUT

Figure 4. Function Diagram − DP0 Sub−Mode

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5

NLPS591

When an HDMI dongle is attached (CA_DET_B = 1), the

device enters DP1 sub−mode. Two autosensing

bidirectional logic level translators for DDC signals are

provided. A−side I/Os are referred to VCCA (pin 1), while

B−side I/Os are referred to VOUT (pin 16). The function

diagram is shown below.

DP1 Sub−Mode

Figure 5. Function Diagram – DP1 Sub−Mode

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6

NLPS591

HDMI Mode

VCCA (pin 1), while B−side I/Os, except for CEC_B, are

referred to VOUT (pin 16). A CEC3V (pin 2) input is also

provided to power the connector−side pull−up of the CEC

translator. A power switch provides power to the connected

display. The function diagram is shown below.

When CH_EN = 0, the device is disabled. The power

switch turns off, VOUT is pulled to GND, and the I/O pins

(pins 7, 8, 9, 10, 11,12, 13, 14) go into high−impedance.

When MODE0 = 1 and MODE1 = 0, the NLPS591 enters

HDMI mode.

When CH_EN = 1, the device is configured as a

HDMI−compliant logic level translator for the control

signals. An unidirectional translator for HPD and three

autosensing bidirectional level translators for the DDC and

CEC signals are provided. A−side I/Os are referred to

Figure 6. Function Diagram – HDMI Mode

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7

NLPS591

CRT Mode

When MODE0 = 1 and MODE1 = 1, the NLPS591 enters

CRT mode.

When CH_EN = 1, the device is configured as a

VESA−compliant logic level translator for the CRT control

signals. Two unidirectional high−drive translators for the

HSYNC and VSYNC signals and two autosensing

bidirectional level translators are provided for the DDC

signals. A power switch provides power to the connected

display. The function diagram is shown below.

When CH_EN = 0, the device is disabled. The power

switch turns off, VOUT is pulled to GND and the I/O pins

(pins 7, 8, 9, 10, 11,12, 13, 14) go into high−impedance.

VIN

VOUT

1

16

Protection

Circuitry

CH_EN

Gate Driver

VCCA

CRT

HDMI

DP

MODE0 = 1

MODE1 = 1

CONTROL

3

4

LOGIC

LS

VCCA

6

VCCA

VOUT

VSYNC_A

VSYNC_B

11

10

CRT

VOUT

HSYNC_A

HSYNC_B

9

12

CRT

VBIAS

VCCA

VOUT

4.7 kW

2.2 kW

DDC_CLK_A

DDC_CLK_B

8

13

VBIAS

VCCA

VOUT

4.7 kW

2.2 kW

DDC_DATA _A

DDC_DATA _B

7

2

14

NOT USED

CH_EN

5

GND

15

Figure 7. Function Diagram – CRT Mode

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8

NLPS591

Power Switch

A power switch is provided for CRT, HDMI and DP

modes, but not for LT mode. The power switch is used to

provide power to a connected display. In the CRT and HDMI

modes, the power may be turned on or off under user control

through the CH_EN pin. When the power switch starts

turning on, VOUT is held LOW momentarily before VOUT

is released and follows VIN.

In the DP Mode, the CH_EN is not available, hence, the

power switch is always on.

The output (VOUT) of the power switch is

current−limited. The switch is protected against extended

exposure to high current flows by a thermal shutdown

protection circuit. The switch is back−drive protected

preventing reverse current flow from VOUT to VIN.

Figure 8. Function Diagram – Power Switch

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9

NLPS591

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Value

Condition

Unit

VIN / CEC3V /

VCC_I2C_0_B /

VCC_I2C_1_B

DC Supply Voltage

−0.5 to +7.0

V

Logic DC Supply Voltage

−0.5 to +7.0

V

CCA

OUT

Load Switch Output Voltage

V

A−Side DC Input/Output Voltage

(Power Down)

(Active)

V

= 0 V

IOA

CCA

−0.5 to (V

+ 0.5)

V

CCA

Active

CCA

V

IOB

B−Side DC Input/Output Voltage

(Power Down)

(Active)

−0.5 to +7.0

V

(Note 1) = 0 V

(Note 1) Active

V

CCB

−0.5 to (V

V

CCB

(Note 1) + 0.5)

T

Storage Temperature

ESD Protection

−65 to +150

°C

STG

ESD

kV

Connector−Side (VOUT, CH1B, CH2B, CH3B, CH4B)

8

2

All Other Pins

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

1.65

4.5

Max

5.5

3.6

5.5

Unit

V

CCA

Logic DC Supply Voltage

Load Switch Input Voltage

V

IN

LT Mode

CRT / HDMI Mode

DP Mode

V

3.0

V

OUT

Load Switch Output Voltage

GND

V

IOA

A−Side DC Input/Output Voltage

(Power Down)

(Active)

V

CCA

V

IOB

B−Side DC Input/Output Voltage

(Power Down)

(Active)

5.5

V

(Note 1)

100

CCB

Dt/DV

Input Transition Rise and Fall Rate A− or B−Ports, Push−Pull Driving

Control Input

ns/V

10

T

A

Operating Temperature Range

−40

+85

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

1. V

refers to the supply powering the translator B−side I/O pin. This supply could be VOUT, CEC3V, VCC_I2C_0_B or VCC_I2C_1_B,

CCB

depending on the device function mode.

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10

NLPS591

Table 5. DC ELECTRICAL CHARACTERISTICS (V

= 1.65 V to 5.5 V, V

(Note 2) = 1.65 V to 5.5 V, unless otherwise specified)

CCA

CCB

−405C to +855C

Typ

(Notes 2, 3)

Min

Max

Symbol

Parameter

Test Conditions (Note 2)

Unit

CONTROL PINS − MODE0, MODE1

V

Input HIGH Voltage

Input LOW Voltage

Input HIGH Leakage

Input LOW Leakage

2/3 * V

V

IH

CCA

V

1/3 * V

IL

CCA

I

IH

VCCA = 5.5 V

55

70

1

mA

I

IL

CONTROL PIN – AUX# (CH_EN in LT, HDMI and CRT Modes)

V

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

2/3 * V

V

IH

CCA

V

1/3 * V

1

IL

CCA

I

IL

VCCA = 5.5 V

mA

POWER SWITCH (VIN = 3.0 V to 5.5 V)

R

Static ON−State Resistance

VIN = 5 V, I

< 300 mA

240

300

1.0

mW

DSON

LOAD

VIN = 3.3 V, I

< 300 mA

LOAD

t

R

Output Rise Time

Output Fall Time

Gate Turn−On Time

VIN = 5 V, I

= 100 mA

0.2

ms

LOAD

t

F

0.01

1.5

t

VIN = 5 V, From VIN applied to

VOUT = 10% of fully on

0.5

ON

VIN = 3.3 V, From VIN applied to

VOUT = 10% of fully on

1.7

40

I

Reverse Current Protection

V

CCA

w 1.65 V, Switch Enabled, No

mA

REV

Load, (VOUT – VIN) w 0.5 V (Note 4)

I

Current Limit Threshold

Response Time to Short Circuit

Thermal Shutdown

DV = 400 mV (Note 5)

0.45

0.8

A

LIM

SW

t

(Note 6)

5

ms

°C

DET

T

SHUT

Shutdown Threshold, TRIP Temperature

140

12

Hysteresis

Trip Voltage

Hysteresis

V

Output Overvoltage Protection

5.9

0.3

V

OVP

2

LT Mode (I C Translator Channels)

CRT and DP1 Modes (DDC Translator Channels)

HDMI Mode (CEC and DDC Translator Channels)

V

A Side Input High Voltage

B Side Input High Voltage

A Side Input Low Voltage

B Side Input Low Voltage

A Side Output High Voltage

B Side Output High Voltage

A Side Output Low Voltage

B Side Output Low Voltage

V

– 0.4

V

IHA

IHB

CCA

– 0.4

CCB

V

0.15

V

ILA

ILB

V

A Side Source Current = 20 mA

B Side Source Current = 20 mA

A Side Sink Current = 20 mA

B Side Sink Current = 20 mA

2/3

V

CCA

V

OHA

OHB

*

V

CCB

V

1/3

V

OLA

OLB

OZA

*

CCA

V

CCB

I

Output Leakage Current on A Side

in “Disabled” Modes

1

mA

Output Leakage Current on B Side

in “Disabled” Modes

1

mA

OZB

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Typical values are for V

= +3.3 V, V

= +1.8 V and T = +25°C. V

may refer to VIN, AUX or VOUT depend on the operating mode.

CCB

CCA

A

CCB

3. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.

A

4. Reverse current protection is activated only when a reverse current threshold of about 200 mA is reached.

5. DV

is the voltage difference across the power switch.

SW

6. Guaranteed by design.

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11

NLPS591

Table 6. DC ELECTRICAL CHARACTERISTICS (V

= 1.65 V to 5.5 V, V

(Note 7) = 3.0 V to 5.5 V, unless otherwise specified)

CCA

CCB

−405C to +855C

Typ

(Notes 7, 8)

Min

Max

Symbol

Parameter

Test Conditions (Note 7)

Unit

CRT Mode (HSYNC/VSYNC Unidirectional Translator Drivers)

V

Input HIGH Voltage

VCCA = 4.5 to 5.5 V

VCCA = 3.0 to 3.6 V

VCCA = 2.3 to 2.7 V

VCCA = 1.65 to 1.95 V

VCCA = 4.5 to 5.5 V

VCCA = 3.0 to 3.6 V

VCCA = 2.3 to 2.7 V

VCCA = 1.65 to 1.95 V

2.0

1.8

1.6

1.4

V

IH

V

Input LOW Voltage

0.8

0.7

0.5

0.3

V

IL

V

Output HIGH Voltage

Output LOW Voltage

V

– 0.1

OUT

V

V = V

,

I

= − 20 mA

OH

I

IH

OH

I

= − 24 mA

2.0

OH

V

0.1

0.8

V = V ,

I

= 20 mA

OL

I

IL

OL

I

= 24 mA

OL

HPD Driver (HPD_B to HPD_A Translator for DP and HDMI Modes)

V

Input HIGH Voltage

VCCA v 2 V; VOUT w 3 V;

v 40 kW, HPD_A Open

2.0

V

IH

R

HPD_B2VOUT

V

Input LOW Voltage

VCCA v 2 V; VOUT w 3 V;

v 40 kW, HPD_A Open

0.4

IL

R

HPD_B2VOUT

V

Output HIGH Voltage

Output LOW Voltage

V = V , I = −0.1 mA

V – 0.5

CCA

V

OH

I

IH OH

V

V = V , I

= 20 mA

V +0.1

IL

OL

I

IL OL_SINK

CA_DET_B Input (CH1B for DP Modes)

V

Input HIGH Voltage

Input LOW Voltage

Input HIGH Leakage

Input LOW Leakage

1.0

V

IH

V

0.35

7.0

1

IL

I

IH

VCCA = 5.5 V

5.5

mA

I

IL

DP0 Mode (AUX, AUXN Level Shifters) See Figures 16 and 17.

R

ON−State Resistance

I

= 5mA, V

= 3.0 V, VI = 1.3 V to 1.7 V

= 4.5 V, VI = 2.7 V to 3.1 V

10

4

40

10

W

ON

LOAD

CCA

7. Typical values are for V

= +3.3 V, V

= +1.8 V and T = +25°C. V

may refer to VIN, AUX or VOUT depend on the operating mode.

CCB

CCA

A

CCB

8. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.

A

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12

NLPS591

Table 7. DC ELECTRICAL CHARACTERISTICS (V

= 1.65 V to 5.5 V, V

(Note 9) = 1.65 V to 5.5 V, unless otherwise specified)

CCA

CCB

−405C to +855C

Typ

(Notes 9,

10)

Min

Max

Symbol

SUPPLY AND LEAKAGE CURRENTS

V Supply Current

Parameter

Test Conditions (Note 9)

Unit

I

LT Mode: VIN = 5.5 V, AUX = 5.5 V, AUX# = V

IHA

or V , all other pins open

75

mA

VCCA

CCA

ILA

DP Mode: VIN = 3.3 V, all other pins left open

130

HDMI Mode: VIN = 5 V, AUX# = V

all other pins left open

or V

,

IHA

ILA

CRT Mode: VIN = 5 V, AUX# = V

or V

,

10

60

IHA

ILA

CH1A = CH2A = 0 V, all other pins left open

I

V

IN

Supply Current

LT Mode: VIN = 1.65 to 5.5 V, V = AUX = 5.5 V,

mA

VIN

CCA

AUX# = V

or V , all other pins left open

IHA

ILA

I

I/O Tristate Leakage Current

LT, HDMI or CRT Mode: CH_EN = L

All Modes: V = 0 V, V = 0 to 5.5 V,

0.1

1.0

mA

OZ

I

I/O Power−Off Leakage Cur-

rent

OFF

CCB

CCA

or V

= 0 to 5.5 V, V

= 0 V

CCB

CCA

9. Typical values are for V

= +3.3 V, V

= +1.8 V and T = +25°C. V

may refer to VIN, AUX or VOUT depend on the operating mode.

CCB

CCA

A

CCB

10.All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.

A

Table 8. PULLUP / PULLDOWN RESISTOR CONFIGURATIONS

Typical, T = +255C (W)

A

Function Mode

Pin / Mode

CH1A

CH2A

CH3A

CH4A

CH1B

CH2B

CH3B

CH4B

AUX

LT

CRT

HDMI

DP0 (AUX)

Hi−Z

DP1

10K to VCCA

10K to VIN

10K to AUX

Hi−Z

10K to VCCA

1M to VCCA

2.2K to VCCA

26K to CEC3V

100K to GND

4.7 K to VOUT

Hi−Z

1M to VCCA

Hi−Z

1M to VCCA

2.2K to VCCA

1M to GND

100K to GND

4.7K to VOUT

Hi−Z

2.2 K to VCCA

Hi−Z

1M to GND

100K to GND

100K to VOUT

4.7K to VOUT

Hi−Z

AUXN

Hi−Z

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13

NLPS591

Table 9. TIMING CHARACTERISTICS in Rail−to−Rail Driving Configuration for Bidirectional Transfer Channels:

CH1, CH2, CH3, CH4 in LT Mode for VCCA = 1.65 V to 5.5 V and VCCB = 1.65 V to 5.5 V;

CH3, CH4 in DP1 Mode for VCCA = 1.65 V to 5.5 V and VCCB = 3.0 V to 3.6 V;

CH1, CH3, CH4 in HDMI Mode for VCCA = 1.65 V to 5.5 V and VCCB = 4.5 V to 5.5 V;

CH3, CH4 in CRT Mode for VCCA = 1.65 V to 5.5 V and VCCB = 4.5 V to 5.5 V.

(R

_

= 10 kW, C

= 15 pF, driver output impedance ≤ 50 W, R

= 50 kW, unless otherwise specified.

PU INT

LOAD

See Figures 9, 10, 13, 14 and 15.)

−405C to +855C

V

CCB

=

V

=

V

CCB

=

CCB

1.65 V to 1.95 V

3.0 V to 3.6 V

4.5 V to 5.5 V

Min

Max

Min

Max

Min

Max

Parameter

Symbol

Conditions

Unit

V

CCA

= 1.65 V to 1.95 V

A Side Rise Time

t

32

25

24

22.6

17

nS

RA

B Side Rise Time

RB

A Side Fall Time

t

FA

7

6

15

nS

B Side Fall Time

t

4.7

20

12.2

14

25

nS

FB

A Side to B Side Propagation Delay

B Side to A Side Propagation Delay

Translator Enable Time (Note 11)

Translator Disable Time (Note 11)

Maximum Data Rate

t

13

nS

PDA−B

PDB−A

20

15

12

nS

t

, t

CH_EN = H

CH_EN = L

100

220

90

120

500

nS

PZH PZL

, t

370

nS

PHZ PLZ

MDR

20

Mbps

V

CCA

= 3.0 V to 3.6 V

A Side Rise Time

t

16

25

9

13

14

4

12.3

9

nS

RA

B Side Rise Time

RB

A Side Fall Time

t

3.5

5

nS

FA

B Side Fall Time

t

6

4

nS

FB

A Side to B Side Propagation Delay

B Side to A Side Propagation Delay

Translator Enable Time (Note 11)

Translator Disable Time (Note 11)

Maximum Data Rate

t

15

14

80

600

3.5

4

6.3

3

nS

PDA−B

PDB−A

nS

t

, t

CH_EN = H

CH_EN = L

30

200

30

330

nS

PZH PZL

, t

nS

PHZ PLZ

MDR

20

Mbps

V

CCA

= 4.5 V to 5.5 V

A Side Rise Time

t

17

23

13

20

13

85

200

13.5

13.3

5

10.5

8

nS

RA

B Side Rise Time

RB

A Side Fall Time

t

3

nS

FA

B Side Fall Time

t

9.6

4

3

nS

FB

A Side to B Side Propagation Delay

B Side to A Side Propagation Delay

Translator Enable Time (Note 11)

Translator Disable Time (Note 11)

Maximum Data Rate

t

6.5

7

nS

PDA−B

PDB−A

6

nS

t

, t

CH_EN = H

CH_EN = L

20

350

20

260

nS

PZH PZL

, t

nS

PHZ PLZ

MDR

20

Mbps

11. These parameters apply to the LT, HDMI and CRT modes only. The power switch turn−on time should be added to translator enable time

for HDMI and CRT modes. Maximum CH_EN frequency is 10 kHz with minimum high pulse duration of 30 ms.

www.onsemi.com

14

NLPS591

Table 10. TIMING CHARACTERISTICS in Open Drain Driving Configuration for Bidirectional Transfer Channels:

CH1, CH2, CH3, CH4 in LT Mode for VCCA = 1.65 V to 5.5 V and VCCB = 1.65 V to 5.5 V;

CH3, CH4 in DP1 Mode for VCCA = 1.65 V to 5.5 V and VCCB = 3.0 V to 3.6 V;

CH1, CH3, CH4 in HDMI Mode for VCCA = 1.65 V to 5.5 V and VCCB = 4.5 V to 5.5 V;

CH3, CH4 in CRT Mode for VCCA = 1.65 V to 5.5 V and VCCB = 4.5 V to 5.5 V.

(R

_

= 10 kW, C

= 15 pF, driver output impedance ≤ 50 W, R

= 1 MW, unless otherwise specified.

PU INT

LOAD

See Figures 11, 12, 13, 14 and 15.)

−405C to +855C

V

CCB

=

V

=

V

CCB

=

CCB

1.65 V to 1.95 V

3.0 V to 3.6 V

4.5 V to 5.5 V

Min

Max

Min

Max

Min

Max

Parameter

Symbol

Conditions

Unit

V

CCA

= 1.65 V to 1.95 V

A Side Rise Time

t

R

=

145

155

20

10

50

10

50

30

60

110

15

28

15

40

10

25

82

200

20

38

17

40

14

12

22

80

nS

RA

PU_INT

10 kW

B Side Rise Time

RB

A Side Fall Time

t

FA

B Side Fall Time

t

FB

A Side to B Side Propagation Delay

t

PHLA−B

PLHA−B

PHLB−A

PLHB−A

B Side to A Side Propagation Delay

nS

Translator Enable Time (Note 12)

Translator Disable Time (Note 12)

Maximum Data Rate

t

, t

CH_EN = H

CH_EN = L

nS

PZH PZL

, t

PHZ PLZ

MDR

2

Mbps

V

CCA

= 3.0 V to 3.6 V

A Side Rise Time

t

R

=

105

135

25

10

20

15

30

34

72

130

20

10

25

10

15

80

105

170

20

30

15

17

15

10

16

80

nS

RA

PU_INT

10 kW

B Side Rise Time

RB

A Side Fall Time

t

FA

B Side Fall Time

t

FB

A Side to B Side Propagation Delay

t

PHLA−B

PLHA−B

PHLB−A

PLHB−A

B Side to A Side Propagation Delay

nS

Translator Enable Time (Note 12)

Translator Disable Time (Note 12)

Maximum Data Rate

t

, t

CH_EN = H

CH_EN = L

nS

PZH PZL

, t

PHZ PLZ

MDR

2

Mbps

V

CCA

= 4.5 V to 5.5 V

A Side Rise Time

t

R

=

85

120

40

90

110

30

20

11

125

130

30

20

5

nS

RA

PU_INT

10 kW

B Side Rise Time

RB

A Side Fall Time

t

FA

B Side Fall Time

t

25

FB

A Side to B Side Propagation Delay

t

12

PHLA−B

PLHA−B

PHLB−A

PLHB−A

10

15

10

13

75

B Side to A Side Propagation Delay

25

20

8

nS

30

Translator Enable Time (Note 12)

Translator Disable Time (Note 12)

Maximum Data Rate

t

, t

CH_EN = H

CH_EN = L

30

10

70

nS

PZH PZL

, t

100

PHZ PLZ

MDR

2

Mbps

12.These parameters apply to the LT, HDMI and CRT modes only. The power switch turn−on time should be added to translator enable time

for HDMI and CRT modes. Maximum CH_EN frequency is 10 kHz with minimum high pulse duration of 30 ms.

www.onsemi.com

15

NLPS591

Table 11. TIMING CHARACTERISTICS for HSYNC/VSYNC Drivers (CH1, CH2 in CRT Mode)

(VCCA = 1.65 V to 5.5 V, VCCB = 4.5 V, C

= 15 pF, driver output impedance ≤ 50 W, R = 50 kW, t v 3 ns and t v 3 ns,

LOAD R F

LOAD

unless otherwise specified. See Figures 9, 13, 14 and 15.)

−405C to +855C

V

CCB

=

V

=

V

CCB

=

CCB

1.65 V to 1.95 V

3.0 V to 3.6 V

4.5 V to 5.5 V

Min Max

Min

Max

Parameter

Symbol

Conditions

Unit

V

CCA

= 1.65 V to 1.95 V

A Side to B Side Propagation Delay

B Side Rise Time

t

13

5

nS

PDA−B

t

RB

B Side Fall Time

t

FB

4

nS

Output Enable Time (Note 13)

Output Disable Time

t

, t

CH_EN = H

CH_EN = L

1.2

130

mS

nS

PZH PZL

, t

PHZ PLZ

Maximum Data Rate

MDR

90

Mbps

V

CCA

= 3.0 V to 3.6 V

A Side to B Side Propagation Delay

B Side Rise Time

t

6

nS

PDA−B

t

RB

B Side Fall Time

t

FB

4

nS

Output Enable Time (Note 13)

Output Disable Time

t

, t

CH_EN = H

CH_EN = L

0.65

130

mS

nS

PZH PZL

, t

PHZ PLZ

Maximum Data Rate

MDR

100

Mbps

V

CCA

= 4.5 V to 5.5 V

A Side to B Side Propagation Delay

B Side Rise Time

t

6

5

nS

PDA−B

t

RB

B Side Fall Time

t

FB

4

nS

Output Enable Time (Note 13)

Output Disable Time

t

, t

CH_EN = H

CH_EN = L

0.61

130

mS

nS

PZH PZL

, t

PHZ PLZ

Maximum Data Rate

MDR

120

Mbps

13.Output Enable Time takes into account turn−on time of the power switch. Maximum CH_EN frequency is 10 kHz with minimum high pulse

duration of 30 ms.

Table 12. TIMING CHARACTERISTICS for AUX_A/AUX#_A to AUX_B/AUX#_B (AUX−CH3B [AUX_A−AUX_B],

AUX#−CH4B [AUX_A#−AUX_B#] in DP0 Mode) (VCCA = 1.65 V to 5.5 V and VOUT = 3.0 V to 3.6 V. See Figures 16 and 17.)

−405C to +855C

V

OUT

=

V

=

V

OUT

=

OUT

1.65 V to 1.95 V

3.0 V to 3.6 V

4.5 V to 5.5 V

Min Max

Min

100

Max

Min Max

Parameter

Symbol

Conditions

Unit

V

= 1.65 V to 1.95 V

CCA

B Side Rise Time

t

V

= 0.65 V,

= 0.25 V

2.5

0.2

nS

RB

IH

IL

B Side Fall Time

t

FB

A Side to B Side Propagation Delay

Maximum Data Rate

t

nS

PDA−B

MDR

Mbps

V

CCA

= 3.0 V to 3.6 V

B Side Rise Time

t

V

= 2.0 V,

= 1.6 V

2.5

0.1

nS

RB

IH

IL

B Side Fall Time

t

FB

A Side to B Side Propagation Delay

Maximum Data Rate

nS

PDA−B

MDR

Mbps

V

CCA

= 4.5 V to 5.5 V

B Side Rise Time

t

V

= 3.5 V,

= 3.1 V

2.5

nS

RB

IH

IL

B Side Fall Time

t

FB

A Side to B Side Propagation Delay

Maximum Data Rate

0.05

nS

PDA−B

MDR

Mbps

www.onsemi.com

16

NLPS591

Test Setups

NLPS591

Figure 9. Rail−to−Rail Driving A−side I/O

Figure 10. Rail−to−Rail Driving B−side I/O

NLPS591

Figure 11. Open−Drain Driving A−side I/O

Figure 12. Open−Drain Driving B−side I/O

Figure 13. Definition of Timing Specification Parameters

www.onsemi.com

17

NLPS591

Figure 14. Test Circuit for Translator Enable/Disable Time Measurements

Figure 15. LT, HDMI, CRT Mode Translator Enable/Disable Time Definition

www.onsemi.com

18

NLPS591

VIN

VOUT

50 W

100 kW

AUX_A

AUX_B

VOUT

10 pF

0.5 pF

50 W

100 W

AUX#_A

AUX_B#

100 kW

VOUT

Figure 16. DP0 Mode AUX Channels Test Circuit

Figure 17. DP0 Mode AUX Channels Propagation Delay Definition

www.onsemi.com

19

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WQFN16, 1.8x2.6, 0.4P

CASE 488AP−01

ISSUE B

DATE 25 JUN 2008

1

SCALE 5:1

L

D

A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

L1

2. CONTROLLING DIMENSION: MILLIMETERS

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30 MM

FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

PIN 1 REFERENCE

E

5. EXPOSED PADS CONNECTED TO DIE FLAG.

USED AS TEST CONTACTS.

MILLIMETERS

A3

EXPOSED Cu

MOLD CMPD

DIM MIN

MAX

0.80

0.15

C

2X

A

A1

A3

b

0.70

0.00

0.050

0.20 REF

C

2X

0.15

0.25

B

A1

D

1.80 BSC

E

2.60 BSC

0.40 BSC

DETAIL B

e

A

ALTERNATE

DETAIL B

L

0.30

0.50

0.15

0.60

0.10

0.08

C

CONSTRUCTIONS

0.00

0.40

L1

L2

C

SEATING

PLANE

A1

DETAIL A

C

A3

MOUNTING FOOTPRINT

5

8

0.562

0.0221

15 X L

0.400

0.0157

4

1

9

0.225

1

e

0.0089

12

2.900

0.1142

16

L2

16 X

0.10 C A B

0.05 C

0.463

0.0182

b

NOTE 3

1.200

0.0472

2.100

0.0827

mm

inches

ǒ

Ǔ

SCALE 20:1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON20790D

WQFN16, 1.8 X 2.6, 0.4P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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


型号：	NLPS591MNTWG
厂家：	ONSEMI
描述：	用于显示屏的完全可配置端口伴随接口集成电路
文件：	总21页 (文件大小：391K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NLPS591MNTWG [ONSEMI]

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