NLSX0102FC2T2G [ONSEMI]
2-Bit 20 Mb/s Dual-Supply Level Translator;
| 型号： | NLSX0102FC2T2G |
| 厂家： | 
ONSEMI |
| 描述： | 2-Bit 20 Mb/s Dual-Supply Level Translator |
| 文件： | 总10页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSX0102
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX0102 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The I/O V and I/O V ports are designed to track two different
CC
L
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MARKING
power supply rails, V and V respectively. Both the V and V
CC
L
CC
L
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the V side to be translated into lower, higher or equal
L
DIAGRAM
value voltage logic signals on the V side, and vice−versa.
CC
A2
The NLSX0102 translator has integrated 10 kW pull−up resistors on
the I/O lines. The integrated pull−up resistors are used to pull−up the
AAG
AYWW
A1
I/O lines to either V or V . The NLSX0102 is an excellent match
L
CC
2
D1
FLIP−CHIP 8
CASE 499BF
A1
for open−drain applications such as the I C communication bus.
Features
• V can be Less than, Greater than or Equal to V
L
CC
AAG
A
Y
= Specific Device Code
= Assembly Location
= Year
• Wide V Operating Range: 1.5 V to 5.5 V
CC
Wide V Operating Range: 1.5 V to 5.5 V
L
WW
= Work Week
• High−Speed with 24 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
PIN ASSIGNMENTS
• Enable Input and I/O Pins are
Overvoltage Tolerant (OVT) to 5.5 V
• Non−preferential Power−up Sequencing
• Integrated 10 kW Pull−up Resistors
• Small Space Saving Package
− 1.9 mm x 0.9 mm x 0.5 mm Flipchip8
• This is a Pb−Free Device
A1
B1
C1
D1
A2
B2
C2
D2
I/O V
2
I/O V
1
CC
CC
GND
V
CC
EN
V
L
I/O V 2
I/O V 1
L
L
Typical Applications
2
• I C, SMBus
(Top View)
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
LOGIC DIAGRAM
V
V
CC
GND
L
EN
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 7000 V
I/O V 1
I/O V
I/O V
1
2
L
CC
I/O V 2
L
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
July, 2018 − Rev. 2
NLSX0102/D
NLSX0102
V
L
V
CC
One−Shot
Block
One−Shot
Block
PU1
PU2
Gate
Bias
R
10 kW
R
Pullup
10 kW
Pullup
EN
EN
I/O V
I/O V
CC
L
N
Figure 1. Block Diagram (1 I/O Line)
FUNCTION TABLE
PIN ASSIGNMENT
Pins
Description
Supply Voltage
CC
EN
Operating Mode
V
CC
V
L
Hi−Z
V
L
V Supply Voltage
L
H
I/O Buses Connected
GND
EN
Ground
Output Enable, referenced to V
L
I/O V
n
I/O Port, referenced to V
I/O Port, referenced to V
CC
CC
L
I/O V n
L
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
High−side DC Supply Voltage
Low−side DC Supply Voltage
−referenced DC Input / Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
50
CC
V
V
L
I/O V
V
CC
V
CC
I/O V
V −referenced DC Input / Output Voltage
L
V
L
V
Enable Control Pin DC Input Voltage
V
EN
I/O_SC
I
Short−Circuit Duration (I/O V and I/O V to GND)
Continuous
mA
mA
°C
L
CC
I
Input / Output Clamping Current (I/O V and I/O V
)
−50
V
I/O
< 0
I/OK
L
CC
T
STG
Storage Temperature
−65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
NLSX0102
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.5
Max
5.5
5.5
5.5
5.5
10
Unit
V
V
CC
High−side Positive DC Supply Voltage
Low−side Positive DC Supply Voltage
Enable Control Pin Voltage
V
L
1.5
V
V
EN
GND
GND
V
V
IO
I/O Pin Voltage
V
Dt/DV
Input Transition Rise and Fall Rate
ns/V
I/O V and I/O V Ports, Push−Pull Driving
L
CC
Control Input
10
T
A
Operating Temperature Range
−40
+85
°C
DC ELECTRICAL CHARACTERISTICS (T = −40 to +85 °C, unless otherwise specified)
A
−40 5C to +855C
Typ
Test Conditions
(Notes 1, 2)
(Note 1)
Min
Max
Symbol
Parameter
I/O V Input HIGH Voltage
V
V
Unit
L
CC
V
IHC
1.5 to
5.5
1.5 to
5.5
V
–
−
V
CC
CC
0.4
V
ILC
V
IHL
I/O V Input LOW Voltage
1.5 to
5.5
1.5 to
5.5
0.15
−
V
V
CC
I/O V Input HIGH Voltage
1.5 to
5.5
1.5 to V – 0.4
5.5
L
L
V
I/O V Input LOW Voltage
1.5 to
5.5
1.5 to
5.5
0.15
−
V
ILL
L
V
Control Pin Input HIGH Voltage
Control Pin Input LOW Voltage
1.5 to
5.5
1.5 to
5.5
0.65 *
V
IH
V
L
V
1.5 to
5.5
1.5 to
5.5
0.35 *
V
IL
V
L
V
OHC
I/O V Output HIGH Voltage
I/O V source
current = −20 mA
1.5 to
5.5
1.5 to
5.5
2/3 *
−
V
CC
CC
V
CC
V
I/O V Output LOW Voltage
I/O V sink current = 1.5 to
1.5 to
5.5
0.4
−
V
OLC
CC
CC
1 mA
5.5
V
OHL
I/O V Output HIGH Voltage
I/O V source current
1.5 to
5.5
1.5 to
5.5
2/3 * V
L
V
L
L
= −20 mA
V
I/O V Output LOW Voltage
I/O V sink current =
1.5 to
5.5
1.5 to
5.5
0.4
2.0
V
OLL
L
L
1 mA
I
V Supply Current
I/O V and I/O V
L
1.5 to
5.5
1.5 to
5.5
mA
QVL
L
CC
Supply Current
unconnected, V
=
EN
V
L
5.5
0
0
2.0
−1.0
2.0
5.5
I
V Supply Current
Supply Current
I/O V and I/O V
unconnected,
1.5 to
5.5
1.5 to
5.5
mA
QVCC
L
CC
L
V
= V
EN
L
5.5
0
0
2.0
−1.0
1.0
5.5
I
V
Tri−state Output Mode
I/O V and I/O V
1.5 to
5.5
1.5 to
5.5
mA
mA
TS−VCC
CC
CC
L
unconnected,
V
= GND
EN
I
V Tri−state Output Mode Supply
I/O V and I/O V
1.5 to
5.5
1.5 to
5.5
1.0
TS−VL
L
CC
L
Current
unconnected,
V
EN
= GND
1. Typical values are for V = +3.3 V, V = +1.8 V and T = +25°C.
CC
L
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
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3
NLSX0102
DC ELECTRICAL CHARACTERISTICS (T = −40 to +85 °C, unless otherwise specified)
A
−40 5C to +855C
Typ
Test Conditions
(Notes 1, 2)
Min
Max
(Note 1)
Symbol
Parameter
V
L
V
CC
Unit
I
I
Enable Pin Input Leakage Current
1.5 to
5.5
1.5 to
5.5
1.0
mA
I
I/O Tri−state Output Mode Leakage
Current
1.5 to
5.5
1.5 to
5.5
1.0
mA
kW
OZ
R
Pull−Up Resistors I/O V and V
C
10
PU
L
1. Typical values are for V = +3.3 V, V = +1.8 V and T = +25°C.
CC
L
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
Timing Characteristics − Rail−to−Rail Driving Configuration
(I/O test circuits of Figures 2, 3 and 7, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW, unless otherwise specified)
LOAD
LOAD
−405C to +855C
CC
V
CC
= 2.3 to 2.7 V
V
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Min
Max
Min
Max
Min
Max
Symbol
V = 1.65 to 1.95 V
Parameter
Conditions
Unit
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
Figure 2
0.6
9.5
10.8
9.7
13.8
5.6
6.5
4.8
4.8
50
2.3
12.5
9.1
8.1
16.2
7.1
7.1
5.3
5.0
40
0.8
7.6
7.6
13.3
16.2
6.8
7.4
2.0
3.5
35
nS
nS
nS
nS
nS
RVL
L
t
t
I/O V Rise Time
4.0
2.0
2.9
2.7
1.9
2.8
2.7
1.7
2.8
RVCC
CC
t
I/O V Fall Time
L
FVL
I/O V Fall Time
FVCC
CC
t
t
t
t
Propagation Delay
PHL−VL−VCC
PLH−VL−VCC
PHL−VCC−VL
PLH−VCC−VL
(Driving I/O V , V to V )
L
L
CC
Propagation Delay
(Driving I/O V , V to V )
Figure 3
nS
CC
CC
L
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
316
0.7
225
0.7
215
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
21
22
24
Mbps
V = 2.3 to 2.7 V
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
Figure 2
2.8
3.2
1.9
2.2
7.7
9.2
8.3
8.3
3.2
4.8
2.5
4.5
50
2.6
2.9
1.9
2.4
8.1
8.8
7.8
8.0
3.7
5.3
1.6
4.3
40
1.8
2.4
1.8
2.6
10.3
6.4
7.4
10.0
3.9
6.0
1.0
3.4
35
nS
nS
nS
nS
nS
RVL
L
t
t
I/O V Rise Time
CC
RVCC
t
I/O V Fall Time
L
FVL
FVCC
I/O V Fall Time
CC
t
t
t
t
Propagation Delay
PHL−VL−VCC
PLH−VL−VCC
PHL−VCC−VL
PLH−VCC−VL
(Driving I/O V , V to V )
L
L
CC
Propagation Delay
(Driving I/O V , V to V )
Figure 3
nS
CC
CC
L
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
225
0.7
225
0.7
215
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
20
22
24
Mbps
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4
NLSX0102
Timing Characteristics − Rail−to−Rail Driving Configuration
(I/O test circuits of Figures 2, 3 and 7, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW, unless otherwise specified)
LOAD
LOAD
−405C to +855C
CC
V
CC
= 2.3 to 2.7 V
V
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Min
Max
Min
Max
Min
Max
Symbol
V = 3.0 to 3.6 V
Parameter
Conditions
Unit
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
Figure 2
2.3
6.5
6.5
7.2
8.0
2.4
3.8
2.5
3.6
40
1.9
8.0
7.4
5.9
9.3
3.1
3.8
2.6
3.1
35
nS
nS
nS
nS
nS
RVL
L
t
I/O V Rise Time
2.5
2.0
2.3
2.1
1.9
2.4
RVCC
CC
t
I/O V Fall Time
L
FVL
FVCC
t
I/O V Fall Time
CC
t
t
t
t
Propagation Delay
PHL−VL−VCC
PLH−VL−VCC
PHL−VCC−VL
PLH−VCC−VL
(Driving I/O V , V to V )
L
L
CC
Propagation Delay
(Driving I/O V , V to V )
Figure 3
nS
CC
CC
L
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
225
0.7
235
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
23
24
Mbps
Timing Characteristics – Open Drain Driving Configuration
(I/O test circuits of Figures 4, 5 and 7, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW, unless otherwise specified)
LOAD
LOAD
−405C to +855C
CC
V
CC
= 2.3 to 2.7 V
V
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Min
Max
Min
Max
Min
Max
Symbol
V = 1.65 to 1.95 V
Parameter
Conditions
Unit
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
Figure 2
38
340
330
11.1
11
30
245
218
12.0
16.2
20.0
208
22.0
150
70
22.0
10.0
4.2
134
120
14.2
16.2
23.0
208
22.0
112
35
nS
nS
nS
nS
nS
RVL
L
t
t
I/O V Rise Time
34
4.4
6.9
2.3
45
23
4.3
7.5
2.4
36.0
1.1
36
RVCC
CC
t
I/O V Fall Time
L
FVL
FVCC
I/O V Fall Time
7.0
CC
t
Propagation Delay
27
2.6
PHLVL−VCC
PLHVL−VCC
(Driving I/O V , V to V )
L
L
CC
t
260
22
27.0
1.2
t
Propagation Delay
(Driving I/O V , V to V )
Figure 3
1.9
45.0
nS
PHLVCC−VL
PLHVCC−VL
CC
CC
L
t
200
80
27.0
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
250
0.7
277
0.7
290
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
2
2
2
Mbps
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5
NLSX0102
Timing Characteristics – Open Drain Driving Configuration
(I/O test circuits of Figures 4, 5 and 7, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW, unless otherwise specified)
LOAD
LOAD
−405C to +855C
CC
V
CC
= 2.3 to 2.7 V
V
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Min
Max
Min
Max
Min
Max
Symbol
V = 2.3 to 2.7 V
Parameter
Conditions
Unit
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
34
400
352
6.9
28.0
24.0
4.3
300
280
6.2
24.0
12.0
4.2
208
180
7.8
nS
nS
nS
nS
RVL
L
t
I/O V Rise Time
35.0
4.4
RVCC
CC
t
I/O V Fall Time
L
FVL
FVCC
t
I/O V Fall Time
4.3
8.8
4.9
9.4
5.4
10.4
14.0
210
13.0
144
35
CC
t
1.7
14.0
250
13.0
225
50
2.0
14.0
210
13.0
180
40
2.1
PHLVL−VCC
PLHVL−VCC
Propagation Delay
Figure 2
Figure 3
nS
nS
(Driving I/O V , V to V )
L
L
CC
t
43.0
1.8
36.0
2.6
27.0
1.2
t
PHLVCC−VL
PLHVCC−VL
Propagation Delay
(Driving I/O V , V to V )
CC
CC
L
t
44.0
37.0
27.0
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
265
0.7
230
0.7
215
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
2
2
2
Mbps
V = 3.0 to 3.6 V
L
t
I/O V Rise Time
Figure 8
Figure 8
Figure 8
Figure 8
25.0
26.0
2.8
400
375
6.1
19.0
14.0
2.6
278
247
5.7
nS
nS
nS
nS
RVL
L
t
t
I/O V Rise Time
CC
RVCC
t
I/O V Fall Time
L
FVL
FVCC
I/O V Fall Time
2.6
7.6
3.1
8.3
CC
t
1.3
10.0
255
124
185
40
1.4
8.0
PHLVL−VCC
PLHVL−VCC
Propagation Delay
Figure 2
Figure 3
nS
nS
(Driving I/O V , V to V )
L
L
CC
t
36.0
1.0
28.0
1.0
243
97.0
136
35
t
PHLVCC−VL
PLHVCC−VL
Propagation Delay
(Driving I/O V , V to V )
CC
CC
L
t
3.0
3.0
t
Enable Time
Disable Time
Figure 7
Figure 7
nS
nS
EN
t
250
0.7
205
0.7
DIS
t
Part−to−Part Skew
Maximum Data Rate
nS
PPSKEW
MDR
2
2
Mbps
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NLSX0102
TEST SETUPS
NLSX0102
NLSX0102
V
L
V
CC
V
L
V
CC
EN
EN
I/O V
I/O V
L
I/O V
L
I/O V
CC
CC
Source
C
LOAD
C
LOAD
Source
R
R
LOAD
LOAD
Figure 2. Rail−to−Rail Driving I/O VL
Figure 3. Rail−to−Rail Driving I/O VCC
NLSX0102
NLSX0102
V
L
V
L
V
CC
V
CC
EN
EN
I/O V
CC
I/O V
L
I/O V
CC
V
CC
C
LOAD
C
LOAD
R
R
LOAD
LOAD
Figure 4. Open−Drain Driving I/O VL
Figure 5. Open−Drain Driving I/O VCC
t
v
I/O V
t
v 3 ns
RISE/FALL
I/O V
CC
RISE/FALL
L
3 ns
90%
50%
10%
90%
50%
10%
t
L
t
t
t
PD_VCC−VL
PD_VCC−VL
PD_VL−VCC
PD_VL−
I/O V
I/O V
CC
VCC
90%
50%
10%
90%
50%
10%
t
t
R−VCC
t
t
R−VL
F−VCC
F−VL
Figure 6. Definition of Timing Specification Parameters
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NLSX0102
V
L
V
CC
2 x V*
OPEN
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
V* = V or V
L
CC
Test
Switch
t
t
, t
Open
2 x V*
PZH PHZ
, t
PZL PLZ
C = 15 pF or equivalent (Includes jig and probe capacitance)
L
R = R = 50 kW or equivalent
L
1
R = Z
of pulse generator (typically 50 W)
T
OUT
V* = V or V for I/O_VL or I/O_VCC measurements,
L
CC
respectively.
Figure 7. Test Circuit for Enable/Disable Time Measurement
t
t
F
V
R
L
50%
EN
V
CC
90%
50%
10%
Input
GND
GND
t
t
PLZ
PZL
t
t
PHL
PLH
HIGH
90%
50%
IMPEDANCE
50%
Output
Output
10%
90%
V
OL
10%
t
t
PHZ
PZH
t
t
F
V
OH
R
50%
Output
HIGH
IMPEDANCE
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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NLSX0102
APPLICATIONS INFORMATION
Level Translator Architecture
of the device that is connected to the translator. The timing
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 kW.
The NLSX0102 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two supply
voltages, VL and VCC, which set the logic levels on the input
and output sides of the translator. When used to transfer data
from the VL to the VCC ports, input signals referenced to the
VL supply are translated to output signals with a logic level
matched to VCC. In a similar manner, the VCC to VL
translation shifts input signals with a logic level compatible
to VCC to an output signal matched to VL.
The NLSX0102 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits are
used to detect the rising or falling input signals. In addition,
the one shots decrease the rise and fall time of the output
signal for high−to−low and low−to−high transitions. Each
input/output channel has an internal 10 kW pull−up. The
magnitude of the pull−up resistors can be reduced by
connecting external resistors in parallel to the internal 10 kW
resistors.
Enable Input (EN)
The NLSX0102 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin to
a low logic level minimizes the power consumption of the
device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs when
the EN pin is equal to a logic high signal. The EN pin is
referenced to the VL supply and has Overvoltage Tolerant
(OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage VL can be
greater than, less than or equal to VCC. The sequencing of the
power supplies will not damage the device during the power
up operation. For optimal performance, 0.01 mF to 0.1 mF
decoupling capacitors should be used on the VL and VCC
power supply pins. Ceramic capacitors are a good design
choice to filter and bypass any noise signals on the voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (tPD), skew
(tPSKEW) and maximum data rate depend on the impedance
ORDERING INFORMATION
Device
†
Package
Shipping
NLSX0102FCT1G
Flip−Chip 8
(Pb−Free)
3000 / Tape & Reel
NLSX0102FCT2G
NLSX0102FC2T2G
Flip−Chip 8
(Pb−Free)
3000 / Tape & Reel
(4mm Pitch Carrier Tape)
Flip−Chip 8
(Pb−Free)
3000 / Tape & Reel
(2mm Pitch Carrier Tape)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
9
NLSX0102
PACKAGE DIMENSIONS
8 PIN FLIP−CHIP, 0.9x1.9, 0.5P
CASE 499BF
ISSUE O
B
E
A
D
NOTES:
PIN A1
REFERENCE
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
MILLIMETERS
DIM MIN
MAX
0.50
0.19
0.25
A
A1
b
0.44
0.15
0.21
TOP VIEW
0.90 BSC
1.90 BSC
D
E
A1
e
0.50 BSC
0.10
C
A
8X
0.05
C
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 3
C
SIDE VIEW
0.50 PITCH
A1
0.50 PITCH
e
e/2
8X
0.25
D
C
8X
b
e
0.05
0.03
C
C
A B
PACKAGE
OUTLINE
B
A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
e/2
1
2
BOTTOM VIEW
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