NLSX4402_17 [ONSEMI]
2-Bit 20 Mb/s Dual-Supply Level Translator;
| 型号： | NLSX4402_17 |
| 厂家： | 
ONSEMI |
| 描述： | 2-Bit 20 Mb/s Dual-Supply Level Translator |
| 文件： | 总14页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSX4402
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4402 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The V I/O and V I/O ports are designed to track two different
CC
L
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power supply rails, V and V respectively. Both the V and V
CC
L
CC
L
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the V side to be translated into lower, higher or
MARKING
DIAGRAMS
L
equal value voltage logic signals on the V side, and vice−versa.
CC
UDFN8
1.45 x 1.0
CASE 517BZ
The NLSX4402 translator has internal pull−up resistors on the I/O
lines. The pull−up resistors are used to pull up the I/O lines to either
J M
1
V or V . The NLSX4402 is an excellent match for open−drain
L
CC
2
applications such as the I C communication bus.
J
M
= Specific Device Code
= Date Code
Features
• V can be Less than, Greater than or Equal to V
L
CC
X2DFN8
1.8 x 1.2
CASE 716AC
AAMG
• Wide V Operating Range: 1.5 V to 5.5 V
CC
G
Wide V Operating Range: 1.5 V to 5.5 V
L
• Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V
• Non−preferential Powerup Sequencing
• Power−Off Protection
AA = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
• Small Space Saving Packages:
1.45 mm x 1.0 mm UDFN8
1.8 mm x 1.2 mm X2DFN8
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
LOGIC DIAGRAM
Compliant
V
L
V
CC
GND
Typical Applications
EN
2
• I C, SMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
I/O V 1
I/O V
1
2
L
CC
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 5000 V
I/O V 2
I/O V
L
CC
ORDERING INFORMATION
†
Device
Package
Shipping
NLSX4402FMUTCG
UDFN8
(Pb−Free)
3000 / Tape &
Reel
NLSX4402MX2ATAG
(In Development)
X2DFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2017 − Rev. 3
NLSX4402/D
NLSX4402
Figure 1. Block Diagram (1 I/O Line)
1
2
3
4
8
7
6
5
V
V
CC
L
I/O V 1
I/O V
I/O V
EN
1
2
L
CC
I/O V 2
L
CC
GND
UDFN8 / X2DFN8
(Top Through View)
Figure 2. Pinout Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
Supply Voltage
EN
L
Operating Mode
Hi−Z
V
V
CC
CC
L
V
V Supply Voltage
L
H
I/O Buses Connected
GND
EN
Ground
Output Enable, Referenced to V
L
I/O V
n
I/O Port, Referenced to V
I/O Port, Referenced to V
CC
CC
L
I/O V n
L
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2
NLSX4402
MAXIMUM RATINGS
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
50
Condition
Unit
V
V
High−side DC Supply Voltage
High−side DC Supply Voltage
−Referenced DC Input/Output Voltage
CC
L
V
V
I/O V
I/O V
V
CC
V
CC
V −Referenced DC Input/Output Voltage
L
V
L
V
EN
Enable Control Pin DC Input Voltage
V
I
I
Short−Circuit Duration (I/O V and I/O V to GND)
Continuous
V < 0
I/O
mA
mA
°C
I/O_SC
I/OK
L
CC
Input/Output Clamping Current (I/O VL and I/O VCC)
Storage Temperature
−50
T
−65 to +150
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
High−side Positive DC Supply Voltage
Min
1.5
Max
5.5
5.5
5.5
5.5
5.5
Unit
V
V
CC
V
L
High−side Positive DC Supply Voltage
Enable Control Pin Voltage
1.5
V
V
EN
GND
GND
GND
V
V
I/O Pin Voltage (Side referred to V
)
CC
V
IO_VCC
V
IO_VL
I/O Pin Voltage (Side referred to V )
V
L
Dt/DV
Input Transition Rise and Fall Rate
A− or B−Ports, Push−Pull Driving
Control Input
10
10
ns/V
T
A
Operating Temperature Range
−40
+85
°C
Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
RecommendedOperating Ranges limits may affect device reliability.
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3
NLSX4402
DC ELECTRICAL CHARACTERISTICS (V = 1.5 V to 5.5 V and V = 1.5 V to 5.5 V, unless otherwise specified) (Note 1)
L
CC
−405C to +855C
Min
V – 0.4
CC
Typ
Max
Symbol
Parameter
I/O V Input HIGH Voltage
Test Conditions (Note 2)
Unit
V
V
−
−
−
−
−
−
−
−
−
−
−
0.15
−
IHC
CC
V
V
I/O V Input LOW Voltage
−
V
ILC
CC
I/O VL Input HIGH Voltage
I/O VL Input LOW Voltage
Control Pin Input HIGH Voltage
Control Pin Input LOW Voltage
I/O VCC Output HIGH Voltage
I/O VCC Output LOW Voltage
V – 0.4
V
IHL
L
V
ILL
−
0.15
−
V
V
0.65 * V
−
V
IH
L
V
0.35 * V
−
V
IL
L
V
OHC
I/O V source current = 20 mA
2/3 * V
−
V
CC
CC
V
OLC
I/O V sink current = 1 mA
0.4
−
V
CC
V
OHL
I/O V
I/O VL Output LOW Voltage
Supply Current
L
Output HIGH Voltage
I/O V source current = 20 mA
2/3 * V
−
V
L
L
V
OLL
I/O V sink current = 1 mA
0.4
V
L
I
V
CC
I/O V and I/O V unconnected, V = V
−
−
−
0.5
−
−
2.0
1.0
−1.0
mA
QVCC
CC
L
EN
L
V = 5.5 V, V = 0 V
L
CC
Supply Current
VL Supply Current
Supply Current
V = 0 V, V = 5.5 V
L
CC
I
I/O V and I/O V unconnected, V = V
−
−
−
0.3
−
−
1.5
−1.0
1.0
mA
QVL
CC
L
EN
L
V = 5.5 V, V = 0 V
L
L
CC
V
V
= 0 V,
= 5.5 V
CC
I
V
Tristate Output Mode
I/O V and I/O V unconnected, V = GND
−
−
0.1
0.1
1.0
1.0
mA
mA
TS−VCC
CC
CC
L
EN
I
V Tristate Output Mode Supply Cur- I/O V and I/O V unconnected, V = GND
L
TS−VL
CC
L
EN
rent
I
Enable Pin Input Leakage Current
−
−
−
−
−
−
1.0
1.0
1.0
1.0
mA
mA
I
I
I/O Power-Off Leakage Current
I/O V Port, V = 0 V, V = 0 to 5.5 V
CC CC L
OFF
I/O VL Port, VCC = 0 to 5.5 V, V = 0 V
−
L
I
I/O Tristate Output Mode
Leakage Current
0.1
mA
kΩ
OZ
R
PU
Pull−Up Resistors
−
10
−
I/O V and V
L
C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performancemay not be indicated by the Electrical Characteristics if operated under different conditions.
1. Typical values are for V = +1.8 V, V = +3.3 V and T = +25°C.
L
CC
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
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4
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 1.5 V, V = 1.5 V
L
CC
t
I/O V Rise Time
9
32
20
30
13
16
15
50
300
2
ns
ns
RVCC
CC
t
I/O V Fall Time
11
20
10
7
FVCC
CC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
12
ns
CC CC
L
t
Enable Time
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
15
Mbps
V = 1.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
9
17
2
12
30
4
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
3
7
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
14
3
24
5
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
Enable Time
40
250
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
20
Mbps
V = 1.8 V, V = 2.8 V
L
CC
t
I/O V Rise Time
11
10
12
5
18
15
15
8
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
7
10
9
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
5
ns
CC CC
L
t
Enable Time
50
300
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
20
Mbps
V = 2.5 V, V = 3.6 V
L
CC
t
I/O V Rise Time
8
12
ns
RVCC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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5
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 2.5 V, V = 3.6 V
L
CC
t
I/O V Fall Time
8
7
5
7
5
12
10
7
ns
ns
FVCC
CC
t
I/O V Rise Time
L
RVL
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
10
8
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
Enable Time
40
225
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 2.8 V, V = 1.8 V
L
CC
t
I/O V Rise Time
13
7
20
10
13
15
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
8
ns
RVL
L
t
I/O V Fall Time
9
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
7
12
60
250
2
ns
CC CC
L
t
Enable Time
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 3.6 V, V = 2.5 V
L
CC
t
I/O V Rise Time
9
6
6
7
5
6
12
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
12
12
7
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
9
ns
CC CC
L
t
Enable Time
50
250
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 5.5 V, V = 1.5 V
L
CC
t
I/O V Rise Time
13
6
20
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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6
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 5.5 V, V = 1.5 V
L
CC
t
I/O V Rise Time
8
20
5
10
27
8
ns
ns
RVL
L
t
I/O V Fall Time
L
FVL
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
14
24
ns
CC CC
L
t
Enable Time
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
2
ns
PPSKEW
MDR
20
Mbps
V = 5.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
5
6
5
4
4
4
7
8
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
7
ns
RVL
L
t
I/O V Fall Time
7
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
ns
CC CC
L
t
Enable Time
30
225
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
V = 1.5 V, V = 1.5 V
Parameter
Test Conditions
Unit
L
CC
t
I/O V Rise Time
55
7
70
14
65
12
ns
ns
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
50
7
RVL
L
t
I/O V Fall Time
L
FVL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
7
NLSX4402
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 1.5 V, V = 1.5 V
L
CC
t
t
Propagation Delay (Driving I/O V , V to V )
CC
20
19
34
34
ns
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
CC CC
L
t
Enable Time
100
300
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 1.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
22
20
43
6
34
27
55
12
26
24
80
250
2
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
13
19
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
Enable Time
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 1.8 V, V = 3.3 V
L
CC
t
I/O V Rise Time
34
1
40
15
48
2
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
40
1
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
9
15
11
70
300
2
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
ns
CC CC
L
t
Enable Time
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
7
Mbps
V = 5.5 V, V = 1.5 V
L
CC
t
I/O V Rise Time
44
1
52
2
ns
ns
ns
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
7
30
23
17
RVL
L
t
I/O V Fall Time
17
10
FVL
PDVL−VCC
L
t
Propagation Delay (Driving I/O V , V to V
)
CC
L
L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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8
NLSX4402
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 5.5 V, V = 1.5 V
L
CC
t
Propagation Delay (Driving I/O V , V to V )
12
24
100
300
2
ns
ns
PDVCC−VL
CC CC
L
t
Enable Time
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 5.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
42
2
50
3
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
44
2
48
3
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
4
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
9
ns
CC CC
L
t
Enable Time
60
225
2
ns
EN
t
Disable Time
ns
DIS
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
7
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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9
NLSX4402
TEST SETUP
NLSX4402
NLSX4402
V
L
V
CC
V
L
V
CC
EN
EN
I/O V
I/O V
L
I/O V
L
I/O V
CC
CC
Source
C
LOAD
C
LOAD
Source
R
LOAD
R
LOAD
Figure 3. Rail−to−Rail Driving I/O VL,
VL to VCC
Figure 4. Rail−to−Rail Driving I/O VCC
VCC to VL
,
NLSX4402
NLSX4402
V
V
L
V
L
V
CC
CC
EN
EN
I/O V
CC
I/O V
L
I/O V
CC
V
CC
C
LOAD
C
LOAD
R
LOAD
R
LOAD
Figure 5. Open−Drain Driving I/O VL,
VL to VCC
Figure 6. Open−Drain Driving I/O VCC
VCC to VL
,
t
v
I/O V
t
RISE/FALL
v 3 ns
RISE/FALL
I/O V
CC
L
3 ns
90%
50%
10%
90%
50%
10%
t
L
t
t
t
PD_VCC−VL
PD_VCC−VL
PD_VL−VCC
PD_VL−VCC
I/O V
I/O V
CC
90%
50%
10%
90%
50%
10%
t
t
R−VCC
t
t
R−VL
F−VCC
F−VL
Figure 7. Definition of Timing Specification Parameters
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10
NLSX4402
V
CC
2xV
CC
OPEN
R
1
PULSE
GENERATOR
DUT
R
T
C
L
R
L
Test
Switch
t
t
, t
Open
PZH PHZ
, t
2 x V
CC
PZL PLZ
C = 15 pF or equivalent (Includes jig and probe capacitance)
L
R = R = 50 kW or equivalent
L
1
OUT
R = Z
T
of pulse generator (typically 50 W)
Figure 8. Test Circuit for Enable/Disable Time Measurement
t
t
F
V
R
L
50%
EN
V
CC
90%
50%
10%
Input
GND
GND
t
t
PLZ
PZL
t
t
PHL
PLH
HIGH
90%
50%
IMPEDANCE
50%
Output
Output
10%
90%
V
OL
10%
t
t
PHZ
PZH
t
t
F
V
OH
R
50%
Output
HIGH
IMPEDANCE
Figure 9. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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11
NLSX4402
APPLICATIONS INFORMATION
Level Translator Architecture
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 kW.
The NLSX4402 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
Enable Input (EN)
supply voltages, V and V , which set the logic levels on
L
CC
The NLSX4402 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the input and output sides of the translator. When used to
transfer data from the V to the V ports, input signals
L
CC
referenced to the V supply are translated to output signals
L
the device and drives the I/O V and I/O V pins to a high
CC
L
with a logic level matched to V . In a similar manner, the
CC
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
V
CC
to V translation shifts input signals with a logic level
L
compatible to V to an output signal matched to V .
CC
L
is referenced to the V supply and has Overvoltage
L
The NLSX4402 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel has an internal 10 kW pull.
The magnitude of the pullup resistors can be reduced by
connecting external resistors in parallel to the internal
10 kW resistors.
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage V can be
L
greater than, less than or equal to V . The sequencing of
CC
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the V and V power supply
L
CC
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (t ) and fall (t ) timing parameters of the open
R
F
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (t ), skew
PD
(t
) and maximum data rate depend on the impedance
PSKEW
of the device that is connected to the translator. The timing
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12
NLSX4402
PACKAGE DIMENSIONS
UDFN8, 1.45x1, 0.35P
CASE 517BZ
ISSUE O
NOTES:
A B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
PIN ONE
REFERENCE
E
2X
0.10
C
MILLIMETERS
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.13 REF
2X
0.10
C
TOP VIEW
SIDE VIEW
0.15
0.25
A3
0.05
C
C
D
1.45 BSC
E
e
1.00 BSC
0.35 BSC
A
L
L1
0.25
0.30
0.35
0.40
0.05
A1
SEATING
PLANE
C
RECOMMENDED
SOLDERING FOOTPRINT*
7X
e/2
8X
0.48
0.22
e
7X L
4
5
1
8
L1
1.18
8X b
1
0.53
0.35
PITCH
M
0.10
C A B
PKG
OUTLINE
M
NOTE 3
C
0.05
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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13
NLSX4402
PACKAGE DIMENSIONS
X2DFN8 1.8x1.2, 0.4P
CASE 716AC
ISSUE O
NOTES:
A B
E
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
TOP VIEW
MILLIMETERS
DIM MIN
NOM MAX
A
A1
A3
b
D
E
e
K
L
0.34
−−−
0.37
−−−
0.127 REF
0.20
1.80
1.20
0.40 BSC
0.20 REF
0.50
0.40
0.05
DETAIL B
A3
0.05
C
C
0.15
1.70
1.10
0.25
1.90
1.30
0.05
A1
DETAIL B
SEATING
PLANE
NOTE 4
C
SIDE VIEW
0.45
0.55
8X
L
RECOMMENDED
SOLDERING FOOTPRINT*
4
5
1
8X
0.65
K
8
8X b
PACKAGE
OUTLINE
e
0.10
0.05
C
C
A B
e/2
BOTTOM VIEW
NOTE 3
1.50
1
8X
0.30
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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