概述
规格参数
数据手册NLU1GT32MUTCG 概述
Single 2-Input OR Gate, TTL Level 单路2输入或门， TTL电平 栅极
NLU1GT32MUTCG 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | DFN |
| 包装说明： | VSON, SOLCC6,.04,16 | 针数： | 6 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 1 week | 风险等级： | 5.73 |
| 系列： | 1G | JESD-30 代码： | R-PDSO-N6 |
| JESD-609代码： | e4 | 长度： | 1.2 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | OR GATE |
| 最大I（ol）： | 0.002 A | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 输入次数： | 2 |
| 端子数量： | 6 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | VSON | 封装等效代码： | SOLCC6,.04,16 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, VERY THIN PROFILE |
| 包装方法： | TAPE AND REEL | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 1.8/5 V | Prop。Delay @ Nom-Sup： | 26.7 ns |
| 传播延迟（tpd）： | 26.7 ns | 认证状态： | Not Qualified |
| 施密特触发器： | NO | 座面最大高度： | 0.55 mm |
| 子类别： | Gates | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 1.65 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | MILITARY | 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) |
| 端子形式： | NO LEAD | 端子节距： | 0.4 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 1 mm | Base Number Matches： | 1 |
NLU1GT32MUTCG 数据手册
通过下载NLU1GT32MUTCG数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载NLU1GT32
Single 2-Input OR Gate,
TTL Level
LSTTL−Compatible Inputs
The NLU1GT32 MiniGatet is an advanced CMOS high−speed
http://onsemi.com
2−input OR gate in ultra−small footprint.
The device input is compatible with TTL−type input thresholds and
the output has a full 5.0 V CMOS level output swing.
The NLU1GT32 input and output structures provide protection
when voltages up to 7.0 V are applied, regardless of the supply
voltage.
MARKING
DIAGRAMS
UDFN6
MU SUFFIX
CASE 517AA
5M
5M
5M
1
1
Features
• High Speed: t = 3.7 ns (Typ) @ V = 5.0 V
PD
CC
ULLGA6
1.0 x 1.0
CASE 613AD
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Input: V = 0.8 V; V = 2.0 V
IL
IH
• CMOS−Compatible Output:
V
OH
> 0.8 V ; V < 0.1 V @ Load
CC OL CC
ULLGA6
1.2 x 1.0
CASE 613AE
• Power Down Protection Provided on inputs
• Balanced Propagation Delays
• Ultra−Small Packages
1
• These are Pb−Free Devices
ULLGA6
1.45 x 1.0
5M
CASE 613AF
1
IN B
IN A
GND
1
2
3
6
5
V
CC
5
M
= Device Marking
= Date Code
NC
PIN ASSIGNMENT
1
IN B
IN A
GND
2
3
4
5
6
4
OUT Y
OUT Y
NC
Figure 1. Pinout (Top View)
V
CC
FUNCTION TABLE
IN A
IN B
≥ 1
OUT Y
Input
Output
Y
A
B
Figure 2. Logic Symbol
L
L
H
H
L
H
L
L
H
H
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
July, 2009 − Rev. 4
NLU1GT32/D
NLU1GT32
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
−0.5 to +7.0
V
IN
DC Input Voltage
−0.5 to +7.0
V
V
OUT
DC Output Voltage
−0.5 to +7.0
V
I
DC Input Diode Current
V
< GND
< GND
OUT
−20
mA
mA
mA
mA
mA
°C
IK
IN
I
DC Output Diode Current
V
20
OK
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
12.5
O
I
25
CC
I
25
GND
T
−65 to +150
STG
T
260
°C
L
T
150
Level 1
°C
J
MSL
F
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
500
R
I
Latchup Performance Above V and Below GND at 125°C (Note 2)
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
5.5
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
V
IN
5.5
V
V
OUT
Output Voltage
0
5.5
V
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
−55
+125
°C
ns/V
A
Dt/DV
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
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2
NLU1GT32
DC ELECTRICAL CHARACTERISTICS
T
= −555C
A
to +1255C
T
A
= 25 5C
Typ
T
= +855C
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Conditions
V
CC
(V)
Unit
V
IH
Low−Level Input
Voltage
1.8
3.0
4.5 to 5.5
1.2
1.4
2.0
1.2
1.4
2.0
1.2
1.4
2.0
V
V
Low−Level Input
1.8
3.0
0.3
0.53
0.8
0.3
0.53
0.8
0.3
0.53
0.8
V
V
IL
Voltage
4.5 to 5.5
V
OH
High−Level Output
Voltage
V
OH
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
IN
IH
IL
I
= −50 mA
V
= V or V
IN
OH
OH
OH
IH
IL
I
I
I
= −2 mA
= −4 mA
= −8 mA
1.8
3.0
4.5
1.40
2.58
3.94
1.38
2.48
3.80
1.37
2.34
3.66
V
OL
Low−Level Output
Voltage
V
OL
= V or V
3.0
4.5
0
0
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
IL
I
= 50 mA
V
= V or V
IN
OL
OL
OL
IH
IL
I
I
I
= 2 mA
= 4 mA
= 8 mA
1.8
3.0
4.5
0.36
0.36
0.36
0.44
0.44
0.44
0.52
0.52
0.52
I
Input Leakage
Current
0 v V v 5.5 V
0 to 5.5
0.1
1.0
1.0
mA
mA
mA
mA
IN
IN
I
Quiescent Supply
Current
0 v V v V
5.5
2.0
20
40
CC
IN
CC
I
Quiescent Supply
Current
V = 3.4 V
IN
5.5
1.35
0.5
1.50
5.0
1.65
10
CCT
OPD
I
Output Leakage
Current
V
OUT
= 5.5 V
0.0
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
= −555C
A
to +1255C
T
A
= 25 5C
T
= +855C
A
Test
Condition
Min
Typ
Max
15.4
23.8
10.4
14.5
7.9
Min
Max
16.9
25.2
11.2
15.5
9.5
Min
Max
Symbol
Parameter
V
CC
(V)
Unit
t
,
Propagation Delay, Input
A or B to Y
1.65 to
1.95
C = 15 pF
L
18.7
26.7
13.2
17.9
11.5
15.5
8.0
ns
PLH
t
PHL
C = 50 pF
L
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
C = 15 pF
L
C = 50 pF
L
C = 15 pF
L
4.8
6.1
3.7
4.4
5.5
11
C = 50 pF
L
11.4
5.5
13.0
6.5
C = 15 pF
L
C = 50 pF
L
7.5
8.5
10.0
10.0
C
Input Capacitance
10
10
pF
pF
IN
C
Power Dissipation
Capacitance (Note 3)
5.0
PD
3. C is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without
PD
load. Average operating current can be obtained by the equation I
= C • V • f + I . C is used to determine the no−load
CC(OPR)
PD CC in CC PD
2
dynamic power consumption: P = C • V
• f + I • V
D
PD
CC
in CC CC.
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3
NLU1GT32
50%
50% V
CC
Input A or B
Output Y
GND
t
PLH
t
PHL
V
V
OH
50% V
CC
OL
Figure 3. Switching Waveforms
V
CC
OUTPUT
INPUT
C
L*
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended
for propagation delay tests.
Figure 4. Test Circuit
Package
ORDERING INFORMATION
Device
†
Shipping
NLU1GT32MUTCG
UDFN6
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NLU1GT32AMX1TCG
NLU1GT32BMX1TCG
NLU1GT32CMX1TCG
ULLGA6, 1.45 x 1.0, 0.5P
(Pb−Free)
ULLGA6, 1.2 x 1.0, 0.4P
(Pb−Free)
ULLGA6, 1.0 x 1.0, 0.35P
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NLU1GT32
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA−01
ISSUE B
EDGE OF PACKAGE
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
E
DETAIL A
REFERENCE
Bottom View
MILLIMETERS
2X
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
(Optional)
A
0.10
C
MOLD CMPD
EXPOSED Cu
TOP VIEW
A3
b
D
E
0.127 REF
2X
0.15
0.25
0.10
C
C
1.20 BSC
1.00 BSC
0.40 BSC
A3
e
L
0.30
0.40
0.15
0.50
(A3)
L1 0.00
L2 0.40
0.10
0.08
A1
DETAIL B
Side View
(Optional)
A
MOUNTING FOOTPRINT*
SEATING
PLANE
10X
C
6X
0.42
SIDE VIEW
6X
0.22
C
A1
5X L
3
1
L2
6X b
0.40
PITCH
1.07
6
4
0.10
0.05
C
A B
e
DIMENSIONS: MILLIMETERS
C
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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5
NLU1GT32
PACKAGE DIMENSIONS
ULLGA6 1.0x1.0, 0.35P
CASE 613AD−01
ISSUE A
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
REFERENCE
E
MILLIMETERS
DIM MIN
−−−
A1 0.00
MAX
0.40
0.05
0.22
0.10
C
A
TOP VIEW
SIDE VIEW
b
D
E
e
0.12
1.00 BSC
1.00 BSC
0.35 BSC
0.25
0.10
C
0.05
0.05
C
C
L
0.35
0.40
L1 0.30
A
SEATING
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
6X
PLANE
05.4X8
C
A1
6X
0.22
e
NOTE 4
5X L
3
1
1.18
L1
1
0.35
0.53
PKG
PITCH
OUTLINE
6
4
6X b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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6
NLU1GT32
PACKAGE DIMENSIONS
ULLGA6 1.2x1.0, 0.4P
CASE 613AE−01
ISSUE A
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
E
REFERENCE
MILLIMETERS
DIM MIN
−−−
A1 0.00
MAX
0.40
0.05
0.25
0.10
C
A
TOP VIEW
SIDE VIEW
b
D
E
e
0.15
1.20 BSC
1.00 BSC
0.40 BSC
0.25
0.10
C
0.05
0.05
C
C
L
0.35
0.45
L1 0.35
A
SEATING
PLANE
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
6X
C
05.4X9
A1
6X
0.26
e
NOTE 4
5X L
3
1
1.24
L1
1
0.53
0.40
PITCH
PKG
OUTLINE
6
4
6X b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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7
NLU1GT32
PACKAGE DIMENSIONS
ULLGA6 1.45x1.0, 0.5P
CASE 613AF−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
E
REFERENCE
MILLIMETERS
DIM MIN
−−−
A1 0.00
MAX
0.40
0.05
0.25
A
0.10
C
TOP VIEW
SIDE VIEW
b
D
E
e
0.15
1.45 BSC
1.00 BSC
0.50 BSC
0.25
0.10
C
L
0.35
0.40
0.05
0.05
C
C
L1 0.30
A
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
SEATING
PLANE
6X
05.4X9
6X
0.30
A1
C
e
NOTE 4
5X L
3
1
6
1.24
L1
1
0.53
PKG
0.50
PITCH
OUTLINE
4
6X b
DIMENSIONS: MILLIMETERS
0.10
C
C
A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
0.05
BOTTOM VIEW
MiniGate is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NLU1GT32/D
NLU1GT32MUTCG CAD模型
引脚图
封装焊盘图
NLU1GT32MUTCG 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| NLU1GT32_16 | ONSEMI | Single 2-Input OR Gate, TTL Level | 获取价格 |
|
| NLU1GT50 | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50AMUTCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50AMX1TCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50BMX1TCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50CMUTCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50CMX1TCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50MUTCG | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50_12 | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
| NLU1GT50_16 | ONSEMI | Single Buffer, Non-Inverting, TTL Level | 获取价格 |
|
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