NLV14012BDG [ONSEMI]
Dual 4-Input NAND Gates;
| 型号： | NLV14012BDG |
| 厂家： | 
ONSEMI |
| 描述： | Dual 4-Input NAND Gates 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14012B
Dual 4-Input NAND Gates
The MC14012B dual 4−input NAND gates are constructed with
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure (Complementary MOS). Their primary use is
where low power dissipation and/or high noise immunity is desired.
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Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin−for−Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
SOIC−14
D SUFFIX
CASE 751A
MARKING DIAGRAM
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
14
14012BG
AWLYWW
• This Device is Pb−Free and is RoHS Compliant
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
V
DD
DC Supply Voltage Range
WW, W = Work Week
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
G
= Pb−Free Package
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
P
D
Power Dissipation, per Package
(Note 1)
500
mW
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
T
Lead Temperature
L
(8−Second Soldering)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V ≤ (V or V ) ≤ V .
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2014 − Rev. 11
MC14012B/D
MC14012B
MC14012B
Dual 4−Input NAND Gate
OUT
1
2
3
4
5
6
14
V
DD
A
2
3
4
5
9
10
11
12
IN 1
13 OUT
1
A
B
IN 2
12 IN 4
A
B
IN 3
11
IN 3
IN 4
B
A
13
10 IN 2
A
B
B
IN 1
NC
9
8
NC
NC = 6, 8
= PIN 14
V
SS
7
V
DD
V
SS
= PIN 7
NC = NO CONNECTION
Figure 1. Pin Assignment
Figure 2. Logic Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
MC14012BDG
SOIC−14
(Pb−Free)
55 Units / Rail
55 Units / Rail
NLV14012BDG*
MC14012BDR2G
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
NLV14012BDR2G*
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14012B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
−55_C
25_C
Typ
125_C
V
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
–3.0
–0.64
–1.6
−
−
−
−
–2.4
–0.51
–1.3
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
–4.2
–3.4
–2.4
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
I
T
5.0
10
15
I = (0.3 mA/kHz) f + I /N
T DD
I = (0.6 mA/kHz) f + I /N
T
DD
Per Gate, C = 50 pF)
I = (0.9 mA/kHz) f + I /N
T
L
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised
T
L
DD
SS
gates per package.
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3
MC14012B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Vdc
(Note 6)
Output Rise Time
t
ns
TLH
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
L
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/PF) C + 20 ns
TLH
TLH
TLH
5.0
10
15
−
−
−
100
50
40
200
100
80
L
L
Output Fall Time
t
ns
ns
t
t
t
= (1.35 ns/pF) C + 33 ns
L
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
THL
THL
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
L
L
Propagation Delay Time
t
, t
PLH PHL
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
= (0.36 ns/pF) C + 47 ns
L
5.0
10
15
−
−
−
160
65
50
300
130
100
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
INPUT
20 ns
V
DD
14
V
DD
90%
50%
10%
INPUT
*
0 V
PULSE
GENERATOR
OUTPUT
t
t
PHL
PLH
90%
50%
10%
V
V
OH
C
L
OUTPUT
INVERTING
OL
t
t
THL
TLH
t
t
PHL
PLH
V
OUTPUT
OH
V
SS
7
90%
NON−INVERTING
50%
10%
V
*All unused inputs of AND, NAND gates must be connected to V
.
OL
DD
t
t
THL
TLH
All unused inputs of OR, NOR gates must be connected to V
.
SS
Figure 3. Switching Time Test Circuit and Waveforms
V
DD
14
V
DD
2, 9
*
3, 10
V
SS
1, 13
4, 11
5, 12
SAME AS
ABOVE
7
V
SS
*Inverter omitted
Figure 4. Circuit Schematic − One of Two Gates Shown
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4
MC14012B
TYPICAL B−SERIES GATE CHARACTERISTICS
N−CHANNEL DRAIN CURRENT (SINK)
P−CHANNEL DRAIN CURRENT (SOURCE)
−10
5.0
4.0
3.0
−9.0
−8.0
−7.0
−6.0
−5.0
−4.0
T = −55°C
A
T = −55°C
A
−40°C
−40°C
+25°C
+25°C
+85°C
+85°C
+125°C
2.0
+125°C
−3.0
−2.0
−1.0
1.0
0
0
0
1.0
2.0
3.0
4.0
5.0
0
−1.0
−2.0
−3.0
−4.0
−5.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 5. VGS = 5.0 Vdc
Figure 6. VGS = − 5.0 Vdc
20
18
16
−50
−45
−40
−35
−30
−25
−20
T = −55°C
A
−40°C
14
12
10
T = −55°C
A
+25°C
+85°C
−40°C
+ 25°C
+125°C
8.0
+85°C
+125°C
6.0
4.0
−15
−10
−5.0
2.0
0
0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
−1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10
0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 7. VGS = 10 Vdc
Figure 8. VGS = − 10 Vdc
- 100
- 90
- 80
- 70
- 60
- 50
- 40
50
45
40
35
30
25
T = −55°C
A
−40°C
T = −55°C
A
−40°C
+25°C
+85°C
+25°C
20
15
10
5.0
0
+85°C
+125°C
- 30
- 20
- 10
0
+125°C
0
−20
2.0 4.0 6.0 8.0 10
12
14 16
18 20
0
−2.0 −4.0 −6.0 −8.0 −10 −12 −14 −16 −18
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 9. VGS = 15 Vdc
Figure 10. VGS = − 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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5
MC14012B
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
10
8.0
6.0
4.0
5.0
4.0
3.0
2.0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
1.0
0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 11. VDD = 5.0 Vdc
Figure 12. VDD = 10 Vdc
DC NOISE MARGIN
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
16
14
12
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V and V for the output(s) to
IL
IH
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, A
be at a fixed voltage V are given in the Electrical
10
O
Characteristics table. V and V are presented graphically
IL
IH
8.0
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
6.0
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
Figure 13. VDD = 15 Vdc
V
DD
V
out
V
DD
V
out
V
O
V
O
O
V
O
V
V
V
V
V
DD
DD
0
0
in
in
V
IL
V
IH
V
IL
V
IH
V
SS
= 0 VOLTS DC
(a) Inverting Function
(b) Non−Inverting Function
Figure 14. DC Noise Immunity
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6
MC14012B
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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For additional information, please contact your local
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MC14012B/D
相关型号：
NLV14013BDTR2G
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-14
ROCHESTER
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