NLV74VHC594DTR2G [ONSEMI]
8-Bit Shift Register with Output Register;
| 型号： | NLV74VHC594DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Shift Register with Output Register |
| 文件： | 总9页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit Shift Register with
Output Register
MC74VHC594
The MC74VHC594 is an 8−bit shift register designed for 2.0 V to
5.5 V VCC operation. The device contain an 8−bit serial−in,
parallel−out shift register that feeds an 8−bit D−type storage register.
Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR,
SRCLR) inputs are provided on the shift and storage registers. A serial
output (QH’) is provided for cascading purposes.
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MARKING DIAGRAM
The shift−register (SRCLK) and storage−register (RCLK) clocks
are positive−edge triggered. If the clocks are tied together, the shift
register always is one clock pulse ahead of the storage register.
16
9
VHC
594
TSSOP−16
DT SUFFIX
CASE 948F
ALYWG
Features
G
8
1
• 2.0 V to 5.5 V V Operation
CC
• High Speed: f
= 185 MHz (Typ) at V = 5 V
CC
max
A
WL
Y
= Assembly Location
= Wafer Lot
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
= Year
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
• Low Noise: V
= 1.0 V (Max)
OLP
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
PIN ASSIGNMENT
Q
Q
1
2
3
4
5
6
7
8
16
15
V
CC
B
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Q
Compliant
C
D
A
Q
14 SER
Q
13 RCLR
12 RCLK
11 SRCLK
E
Q
Q
F
G
Q
10
SRCLR
H
GND
9
Q '
H
ORDERING INFORMATION
†
Device
MC74VHC594DTR2G TSSOP−16 2500 Tape &
(Pb−Free) Reel
NLV74VHC594DTR2G* TSSOP−16 2500 Tape &
(Pb−Free) Reel
Package
Shipping
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
August, 2021 − Rev. 1
MC74VHC594/D
MC74VHC594
FUNCTION TABLE
INPUT
SER
X
SRCLK
SRCLR
RCLK
RCLR
FUNCTION
X
L
X
X
X
X
Shift register is cleared.
L
°
H
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
°
H
X
X
First stage of shift register goes high
Other stages store the data of previous stage, respectively.
L
X
X
X
±
H
X
X
X
X
X
°
X
L
Shift register state is not changed.
Storage register is cleared.
X
X
X
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
±
Figure 1. Logic Diagram
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2
MC74VHC594
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH'
Figure 2. Timing Diagram
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3
MC74VHC594
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
−0.5 to +6.5
−0.5 to +6.5
V
IN
DC Input Voltage
V
V
DC Output Voltage
−0.5 to V + 0.5
V
O
IK
CC
I
DC Input Clamp Current
DC Output Clamp Current
DC Input Current
−20
mA
mA
mA
mA
mA
mA
°C
I
20
OK
I
IN
20
I
O
DC Output Source / Sink Current
DC Supply Current per Supply Pin
25
I
50
CC
I
DC Ground Current per Ground Pin
Storage Temperature Range
50
GND
T
STG
−65 to +150
T
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
Thermal Resistance (Note 1)
260
°C
L
T
+150
°C
J
q
62.2
°C/W
W
JA
P
D
Power Dissipation in Still Air
2
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 30% − 35%
UL−94−VO (0.125 in)
V
ESD
ESD Withstand Voltage (Note 2)
Human Body Model
Charged Device Model
2000
1000
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 3)
100
mA
Latchup
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2
1. Measured with minimum pad spacing on an FR4 board, using 254 mm , 2 ounce copper trace no air flow per JESD51−7.
2. HBM tested to EIA / JESD22−A114−A. CDM tested to JESD22−C101−A. JEDEC recommends that ESD qualification to EIA/JESD22−A115A
(Machine Model) be discontinued.
3. Tested to EIA/JESD78 Class II.
RECOMMENDED OPERATING CONDITIONS (Note 4)
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
Operating Free−Air Temperature
Min
2.0
0
Max
5.5
Unit
V
V
CC
V
IN
5.5
V
V
O
0
V
CC
V
T
A
−55
0
+125
20
°C
nS/V
t , t
Input Rise or Fall Rate
V
CC
= 2.0 V
r
f
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
0
20
0
10
0
5
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. All unused inputs of the device must be held at V or GND to ensure proper device operation.
CC
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4
MC74VHC594
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
3 85°C
T 3 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
Maximum Low−Level
2.0
3.0
4.5
5.5
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
V
V
IL
Input Voltage
V
OH
Minimum High−Level
Output Voltage
V
I
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
IN
OH
IH
IL
IL
IL
IL
= − 50 μA
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Low−Level Output
Voltage
V
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
IN
IH
I
= 50 μA
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Input Leakage
Current
V
= 5.5 V or
2.0 to
5.5
0.1
0.1
4.0
1.0
1.0
μA
μA
μA
IN
IN
GND
I
Power Off Leakage
Current
V
IN
= 5.5 V
0
1.0
1.0
OFF
I
Maximum Supply
Current
V = V or
5.5
40.0
40.0
CC
I
CC
O
GND, I = 0 A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
TIMING REQUIREMENTS (Input t = t = 3.0 ns, Figures 3 to 7)
r
f
T
A
= 25°C
T
A
3
85°C
T 3 125°C
A
Symbol
Parameter
V
(V)
Typ
−
Limit
Limit
3.5
3.0
8.5
5.0
9.0
5.0
2.0
2.0
0.0
0.0
3.0
2.5
3.0
2.5
5.0
5.0
5.0
5.0
Limit
3.5
3.0
8.5
5.0
9.0
5.0
2.0
2.0
1.0
1.0
3.0
2.5
3.0
2.5
5.0
5.0
5.0
5.0
Unit
CC
t
su
Setup Time, SER before SRCLK↑↓
Setup Time, SRCLK↑ to RCLK↑
Setup Time, SRCLR low to RCLK↑
Hold Time, SER before SRCLK↑↓
Hold Time, SRCLR low to RCLK↑
Recovery Time, SRCLR high to SRCLK↑
Recovery Time, RCLR high to RCLK↑
Pulse Width, SRCLK or RCLK
3.3
3.5
3.0
8.0
5.0
8.0
5.0
2.0
2.0
0.0
0.0
3.0
2.5
3.0
2.5
5.0
5.0
5.0
5.0
ns
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
−
−
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
t
h
−
−
−
−
t
−
rec
−
−
−
t
W
−
−
Pulse Width, SRCLR or RCLR
−
−
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5
MC74VHC594
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns, Figures 3 to 8)
r
f
T
A
= 25°C
Typ
T
= ≤ 85°C
T = ≤ 125°C
A
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Conditions
V
CC
(V)
Unit
f
Maximum Clock
Frequency (50%
Duty Cycle)
MHz
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
80
150
70
70
max
135
185
115
115
t
,
Propagation
Delay, SRCLK to
Q ’
H
ns
ns
ns
ns
pF
C = 15pF
C = 50pF
L
8.8
11.3
13.0
16.5
1.0
1.0
15.0
18.5
1.0
1.0
15.0
18.5
PLH
L
t
PHL
C = 15pF
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
6.2
7.7
8.2
10.2
1.0
1.0
9.4
11.4
1.0
1.0
9.4
11.4
L
C = 50pF
L
t
,
Propagation
Delay, RCLK to
C = 15pF
7.7
10.2
11.9
15.4
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
PLH
L
t
C = 50pF
L
PHL
Q −Q
A
H
C = 15pF
5.4
6.9
7.4
9.4
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
L
C = 50pF
L
t
Propagation
Delay,
C = 15pF
8.4
10.9
12.8
16.3
1.0
1.0
13.7
17.2
1.0
1.0
13.7
17.2
PHL
L
C = 50pF
L
SRCLR to Q ’
H
C = 15pF
5.9
7.4
8.0
10.0
1.0
1.0
9.1
11.1
1.0
1.0
9.1
11.1
L
C = 50pF
L
t
Propagation
Delay,
C = 15pF
7.7
10.2
11.9
15.4
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
PHL
L
C = 50pF
L
RCLR to Q −Q
A
H
C = 15pF
5.4
6.9
7.4
9.4
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
L
C = 50pF
L
C
Input Capacitance
4
10
10
10
IN
Symbol
Parameter
Power Dissipation Capacitance (Note 1)
V
(V)
Typ (T = 25°C)
Unit
CC
A
C
5.0
87
pF
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption: P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, V = 5.0 V, C = 50 pF, T = 25°C)
r
f
CC
L
A
Symbol
Characteristic
Min
Typ
0.8
Max
Unit
V
V
OLP
Quiet Output, Dynamic V
1.0
OL
OL
V
OLV
Quiet Output, Dynamic V
−1.0
−0.8
V
V
High−Level Dynamic Input Voltage
Low−Level Dynamic Input Voltage
3.5
V
IHD
V
1.5
V
ILD
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6
MC74VHC594
SWITCHING WAVEFORMS
t
w
V
CC
V
CC
50% V
CC
SRCLR
SRCLK
50% V
t
CC
GND
GND
t
PHL
w
1/f
max
50% V
CC
Q '
H
t
t
PHL
PLH
t
rec
Q '
H
V
CC
50% V
CC
50% V
SRCLK
CC
GND
Figure 3.
Figure 4.
V
CC
V
SRCLR
SER
50% V
CC
CC
RCLK
50% V
CC
GND
VALID
GND
V
CC
50% V
CC
t
t
PLH
PHL
GND
t
su
t
h
Q -Q
A
H
V
CC
50% V
CC
SRCLK or
RCLK
50% V
CC
GND
Figure 5.
Figure 6.
V
CC
SRCLK
50% V
CC
GND
t
su
V
CC
50% V
CC
RCLK
t
w
GND
Figure 7.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 8. Test Circuit
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
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