NPC1247CD065R2G [ONSEMI]
Fixed Frequency Current Mode Controller for Flyback Converters; 用于回扫转换器的固定频率电流模式控制器
| 型号： | NPC1247CD065R2G |
| 厂家： | 
ONSEMI |
| 描述： | Fixed Frequency Current Mode Controller for Flyback Converters |
| 文件： | 总42页 (文件大小：1929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1247
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1247 is a new fixed−frequency current−mode controller
featuring the Dynamic Self−Supply. This function greatly simplifies
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MARKING
the design of the auxiliary supply and the V capacitor by activating
CC
the internal startup current source to supply the controller during
start−up, transients, latch, stand−by etc. This device contains a special
HV detector which detect the application unplug from the AC input
line and triggers the X2 discharge current. This HV structure allows
the brown−out detection as well.
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum
power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for the robust power supply designs.
A dedicated Off mode allows to reach the extremely low no load
input power consumption via “sleeping” whole device and thus
minimize the power consumption of the control circuitry.
DIAGRAM
8
47Xff
ALYWX
G
SOIC−7
CASE 751U
1
47Xff = Specific Device Code
X = A, B, C or D
ff = 65 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
A
L
Y
W
G
PIN CONNECTIONS
Features
Latch
FB
1
2
3
4
8
HV
• Fixed−Frequency Current−Mode Operation (65 kHz and 100 kHz
frequency options)
• Frequency Foldback then Skip Mode for Maximized Performance in
Light Load and Standby Conditions
V
CC
6
5
CS
GND
DRV
(Top View)
• Timer−Based Overload Protection with Latched (Options A/C) or
Auto−Recovery (Options B/D) Operation
• High−voltage Current Source with Brown−Out Detection and
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 41 of this data sheet.
Dynamic Self−Supply, Simplifying the Design of the V Circuitry
CC
• Frequency Modulation for Softened EMI Signature
• Adjustable Overpower Protection Dependant on the Bulk Voltage
• Latch−off Input Combined with the Overpower Protection Sensing
Input
• V Operation up to 28 V, With Overvoltage Detection
CC
Typical Applications
• 500/800 mA Source/Sink Drive Peak Current
Capability
• AC−DC Adapters for Notebooks, LCD, and Printers
• Offline Battery Chargers
• Consumer Electronic Power Supplies
• Auxiliary/Housekeeping Power Supplies
• Offline Adapters for Notebooks
• 10 ms Soft−Start
• Internal Thermal Shutdown
• No−Load Standby Power < 30 mW
• X2 Capacitor in EMI Filter Discharging Feature
• These Devices are Pb−Free and Halogen Free/BFR Free
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
October, 2013 − Rev. 0
NCP1247/D
NCP1247
TYPICAL APPLICATION EXAMPLE
Figure 1. Flyback Converter Application Using the NCP1247
OPTIONS
Part
Option
Frequency
65 kHz
OCP Fault
Latched
V
V
HV(stop)
HV(start)
A
A
B
B
C
C
D
D
111 V
103 V
100 kHz
65 kHz
Latched
111 V
111 V
111 V
95 V
95 V
95 V
95 V
103 V
103 V
103 V
87 V
Autorecovery
Autorecovery
Latched
100 kHz
65 kHz
NCP1247
100 kHz
65 kHz
Latched
87 V
Autorecovery
Autorecovery
87 V
100 kHz
87 V
PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
LATCH
Latch−Off Input
Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection.
2
3
FB
CS
Feedback + Shutdown pin
Current Sense
An optocoupler collector to ground controls the output regulation. The part
goes to the low consumption Off mode if the FB input pin is pulled to GND.
This Input senses the Primary Current for current−mode operation, and
offers an overpower compensation adjustment.
4
5
6
GND
DRV
VCC
−
The controller ground
Drive output
VCC input
Drives external MOSFET
This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage. It is not allowed to connect
another circuit to this pin to keep low input power consumption.
8
HV
High−voltage pin
Connects to the rectified AC line to perform the functions of Start−up
Current Source, Self−Supply, brown−out detection and X2 capacitor
discharge function and the HV sensing for the overpower protection
purposes. It is not allowed to connect this pin to DC voltage.
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2
NCP1247
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Figure 2. Simplified Internal Block Schematic
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3
NCP1247
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DRV
(pin 5)
Maximum voltage on DRV pin
(Dc−Current self−limited if operated within the allowed range) (Note 1)
–0.3 to 20
1000 (peak)
V
mA
V
V
Power Supply voltage, V pin, continuous voltage
–0.3 to 28
30 (peak)
V
mA
CC
CC
CC
(pin 6)
Power Supply voltage, V pin, continuous voltage (Note 1)
CC
HV
(pin 8)
Maximum voltage on HV pin
(Dc−Current self−limited if operated within the allowed range)
–0.3 to 500
20
V
mA
V
max
Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
(Dc−Current self−limited if operated within the allowed range) (Note 1)
–0.3 to 10
10 (peak)
V
mA
R
Thermal Resistance SOIC−7
°C/W
q
J−A
Junction-to-Air, low conductivity PCB (Note 2)
Junction-to-Air, medium conductivity PCB (Note 3)
Junction-to-Air, high conductivity PCB (Note 4)
162
147
115
R
Thermal Resistance Junction−to−Case
Operating Junction Temperature
Storage Temperature Range
73
°C/W
°C
q
J−C
T
JMAX
−40 to +150
−60 to +150
> 2000
T
°C
STRGMAX
ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22,
Method A114E
V
ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A
> 200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCP1247
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V,
J
J
HV
V
CC
= 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source
operation
V
−
30
40
V
HV(min)
Current flowing out of V pin
V
= 0 V
CC(on)
I
I
0.2
5
0.5
8
0.8
11
mA
CC
CC
start1
start2
(X2 discharge current value is equal to I
)
V
CC
= V
− 0.5 V
start2
Off−state leakage current
V
= 500 V, V = 15 V
I
start(off)
10
25
50
mA
mA
HV
CC
Off−mode HV supply current
V
HV
V
HV
= 141 V,
= 325 V,
I
−
−
45
50
60
70
HV(off)
V
CC
loaded by 4.7 mF cap
SUPPLY
HV current source regulation threshold
V
8
11
−
V
V
CC(reg)
Turn−on threshold level, V going up
V
11.0
12.0
13.0
CC
CC(on)
HV current source stop threshold
HV current source restart threshold
Turn−off threshold
V
9.5
8.5
25
−
10.5
8.9
11.5
9.3
28
V
V
CC(min)
V
CC(off)
Overvoltage threshold
V
26.5
10
V
CC(ovp)
Blanking duration on V
detection
and V
t
VCC(blank)
−
ms
CC(off)
CC(ovp)
V
decreasing level at which the internal
V
4.8
0.2
7.0
0.8
7.7
V
CC
CC(reset)
logic resets
V
CC
level for I
to I transition
START2
V
1.25
V
START1
CC(inhibit)
Internal current consumption (Note 5)
DRV open, V = 3 V, 65 kHz
I
I
1.3
1.3
1.85
1.85
2.2
2.2
mA
FB
CC1
CC1
DRV open, V = 3 V, 100 kHz
FB
Cdrv = 1 nF, V = 3 V, 65 kHz
I
I
1.8
2.3
2.6
2.9
3.0
3.5
FB
CC2
CC2
Cdrv = 1 nF, V = 3 V, 100 kHz
FB
I
0.67
0.3
0.9
0.6
1.13
0.9
CC3
CC4
Off mode (skip or before start−up)
I
Fault mode (fault or latch)
BROWN−OUT
Brown−Out thresholds (A/B versions)
V
HV
going up
V
102
94
111
103
120
112
V
V
HV
HV(start)
HV(stop)
V
going down
V
Brown−Out thresholds (C/D versions)
V
HV
going up
going down
V
V
87
79
95
87
103
95
HV
HV(start)
HV(stop)
V
Timer duration for line cycle drop−out
X2 DISCHARGE
t
52
73
94
ms
HV
Comparator hysteresis observed at HV pin
HV signal sampling period
Timer duration for no line detection
Discharge timer duration
V
1.5
−
3.5
1.0
32
5
−
V
HV(hyst)
T
ms
ms
ms
sample
t
21
21
43
43
DET
t
32
DIS
OSCILLATOR
Oscillator frequency
f
58
87
65
100
72
109
kHz
OSC
Maximum on time for T = 25°C to +125°C
f
= 65 kHz
= 100 kHz
t
ONmax(65kHz)
ONmax(100kHz)
11.5
7.5
12.3
8.0
13.1
8.5
ms
J
OSC
only
f
t
OSC
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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NCP1247
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V,
J
J
HV
V
CC
= 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Maximum on time
f
= 65 kHz
= 100 kHz
t
11.3
7.4
12.3
8.0
13.1
8.5
ms
OSC
ONmax(65kHz)
f
t
OSC
ONmax(100kHz)
Maximum duty cycle (corresponding to
maximum on time at maximum switching
frequency)
f
= 65 kHz
= 100 kHz
D
−
80
−
%
OSC
MAX
f
OSC
Frequency jittering amplitude, in percentage
A
F
4
6
8
%
jitter
of F
OSC
Frequency jittering modulation frequency
85
125
165
Hz
jitter
FREQUENCY FOLDBACK
Feedback voltage threshold below which
frequency foldback starts
V
V
1.8
0.8
23
2.0
0.9
27
2.2
1.0
32
V
V
FB(foldS)
FB(foldE)
OSC(min)
Feedback voltage threshold below which
frequency foldback is complete
Minimum switching frequency
V
FB
= V
+ 0.1
f
kHz
skip(in)
OUTPUT DRIVER
Rise time, 10% to 90% of V
V
V
= V
DRV
+ 0.2 V,
+ 0.2 V,
+ 0.2 V,
t
rise
−
−
40
40
70
70
ns
ns
CC
CC
CC(min)
C
= 1 nF
Fall time, 90% to 10% of V
= V
DRV
t
fall
CC
CC
CC(min)
C
= 1 nF
Current capability
V
= V
mA
CC
CC(min)
C
= 1 nF
DRV
DRV high, V
DRV low, V
= 0 V
I
−
−
500
800
−
−
DRV
DRV
DRV(source)
DRV(sink)
= V
I
CC
Clamping voltage (maximum gate voltage)
V
CC
R
= V
DRV
– 0.2 V, DRV high,
V
11
13.5
16
V
V
CCmax
DRV(clamp)
= 33 kW, C
= 220 pF
load
High−state voltage drop
V
DRV
= V
+ 0.2 V,
V
DRV(drop)
−
−
1
CC
CC(min)
R
= 33 kW, DRV high
CURRENT SENSE
Input Pull−up Current
V
= 0.7 V
> 3.5 V
I
−
0.66
−
1
−
mA
V
CS
bias
Maximum internal current setpoint
V
V
V
0.70
80
0.74
110
FB
ILIM
Propagation delay from V
DRV off
detection to
= V
t
ns
Ilimit
CS
ILIM
delay
Leading Edge Blanking Duration for V
t
200
250
320
ns
V
ILIM
LEB
Threshold for immediate fault protection
activation
V
0.95
1.05
1.15
CS(stop)
Leading Edge Blanking Duration for V
(Note 6)
t
90
120
150
ns
CS(stop)
BCS
st
Soft−start duration
From 1 pulse to V = V
t
SSTART
8
11
14
ms
CS
ILIM
Frozen current setpoint
V
275
300
325
mV
I(freeze)
INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp
S
−
−
−32.5
−50
−
−
mV /
ms
comp(65kHz)
S
comp(100kHz)
FEEDBACK
Internal pull−up resistor
T = 25°C
J
R
15
20
25
kW
FB(up)
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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NCP1247
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V,
J
J
HV
V
CC
= 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
FEEDBACK
to internal current setpoint division ratio
V
FB
K
4.7
4.5
5
5
5.3
5.5
−
FB
Internal pull−up voltage on the FB pin
(Note 6)
V
V
FB(ref)
Feedback voltage below which the peak
current is frozen
V
1.35
1.5
1.65
V
FB(freeze)
SKIP CYCLE MODE
Feedback voltage thresholds for skip mode
V
going down
FB
V
0.63
0.72
0.70
0.80
0.77
0.88
V
FB
skip(in)
V
going up
V
skip(out)
REMOTE CONTROL ON FB PIN
The voltage above which the part enters the
on mode
V
V
> V
, V = 60 V
V
ON
−
2.2
0.40
−
−
0.45
−
V
V
CC
CC(off) HV
The voltage below which the part enters the
off mode
V
CC
> V
V
OFF
0.35
500
CC(off)
Minimum hysteresis between the V and
> V
, V = 60 V
V
HYST
mV
ON
CC
CC(off) HV
V
OFF
Pull−up current in off mode
Go To Off mode timer
V
V
> V
> V
I
−
5
−
mA
CC
CC(off)
OFF
t
100
150
300
ms
CC
CC(off)
GTOM
OVERLOAD PROTECTION
Fault timer duration
t
108
128
178
ms
s
fault
Autorecovery mode latch−off time duration
OVERPOWER PROTECTION
t
0.85
1.00
1.35
autorec
V
to I
conversion ratio
K
OPC
−
0.54
−
mA / V
mA
HV
OPC
Current flowing out of CS pin (Note 7)
V
= 125 V
= 162 V
= 325 V
= 365 V
I
I
I
I
−
−
−
0
20
110
130
−
−
−
HV
HV
HV
HV
OPC(125)
OPC(162)
OPC(325)
OPC(365)
V
V
V
105
150
FB voltage above which I
is applied
V
V
= 365 V
= 365 V
V
V
2.12
2.35
2.15
2.58
V
V
OPC
HV
HV
FB(OPCF)
FB voltage below which is no I
LATCH−OFF INPUT
High threshold
applied
−
−
OPC
FB(OPCE)
V
Latch
going up
V
V
2.35
0.76
2.5
0.8
2.65
0.84
V
V
OVP
Low threshold
V
going down
Latch
OTP
Current source for direct NTC connection
During normal operation
V
Latch
= 0 V
mA
I
65
130
95
190
105
210
NTC
During soft−start
I
NTC(SSTART)
Blanking duration on high latch detection
65 kHz version
100 kHz version
t
35
20
50
35
70
50
ms
Latch(OVP)
Blanking duration on low latch detection
Clamping voltage
t
−
350
−
ms
Latch(OTP)
I
I
= 0 mA
= 1 mA
V
V
1.0
1.8
1.2
2.4
1.4
3.0
V
Latch
Latch
clamp0(Latch)
clamp1(Latch)
TEMPERATURE SHUTDOWN
Temperature shutdown
T going up
T
−
−
150
30
−
−
°C
°C
J
TSD
T
TSD(HYS)
Temperature shutdown hysteresis
T going down
J
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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NCP1247
TYPICAL CHARACTERISTIC
40
38
36
34
32
30
28
26
24
22
20
32
30
28
26
24
22
20
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Minimum Current Source Operation
VHV(min)
Figure 4. Off−State Leakage Current Istart(off)
50
45
40
35
30
25
20
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
I
I
@ V = 325 V
HV
HV(off)
@ V = 141 V
HV(off)
HV
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Off−Mode HV Supply Current IHV(off)
Figure 6. High Voltage Startup Current
Flowing Out of VCC Pin Istart2
120
118
116
114
112
110
108
106
104
102
100
120
118
116
114
112
110
108
106
104
102
100
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Brown−out Device Start Threshold
Figure 8. Brown−out Device Stop Threshold
VHV(start)
VHV(stop)
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NCP1247
TYPICAL CHARACTERISTIC
0.75
0.74
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.65
310
308
306
304
302
300
298
296
294
292
290
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Maximum Internal Current Setpoint
VILIM
Figure 10. Frozen Current Setpoint VI(freeze) for
the Light Load Operation
1.15
1.13
1.11
1.09
1.07
1.05
1.03
1.01
0.99
0.97
0.95
110
100
90
80
70
60
50
40
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Threshold for Immediate Fault
Protection Activation VCS(stop)
Figure 12. Propagation Delay tdelay
130
125
120
115
110
105
100
300
290
280
270
260
250
240
230
220
210
200
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Leading Edge Blanking Duaration
tLEB
Figure 14. Maximum Overpower
Compensating Current IOPC(365) Flowing Out
of CS Pin
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NCP1247
TYPICAL CHARACTERISTIC
24
23
22
21
20
19
18
17
16
15
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. FB Pin Internal Pull−up Resistor
Figure 16. FB Pin Open Voltage VFB(ref)
RFB(up)
0.85
2.65
2.60
2.55
2.50
2.45
2.40
2.35
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Latch Pin High Threshold VOVP
Figure 18. Latch Pin Low Threshold VOTP
220
210
200
190
180
170
160
150
140
110
105
100
95
90
85
80
75
70
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Current INTC Sourced from the
Latch Pin, Allowing Direct NTC Connection
Figure 20. Current INTC(SSTART) Sourced from
the Latch Pin, During Soft−Start
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NCP1247
TYPICAL CHARACTERISTIC
70
69
68
67
66
65
64
63
62
61
60
100
99
98
97
96
95
94
93
92
91
90
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Oscillator fOSC for the 65 kHz
Version
Figure 22. Oscillator fOSC for the 100 kHz
Version
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12.0
11.9
8.4
8.3
8.2
8.1
8.0
7.9
7.8
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Maximum ON Time tONmax for the
65 kHz Version
Figure 24. Maximum ON Time tONmax for the
100 kHz Version
85
84
83
82
81
80
79
78
77
76
75
30
29
28
27
26
25
24
23
22
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Maximum Duty Ratio DMAX
Figure 26. Minimum Switching Frequency
fOSC(min)
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NCP1247
TYPICAL CHARACTERISTIC
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS)
Figure 28. FB Pin Voltage Below Which
Frequency Foldback Complete VFB(foldE)
0.77
0.75
0.73
0.71
0.69
0.67
0.65
0.63
0.88
0.86
0.84
0.82
0.80
0.78
0.76
0.74
0.72
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. FB Pin Skip−In Level Vskip(in)
Figure 30. FB Pin Skip−Out Level Vskip(out)
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. FB Pin Level VFB(OPCF) Above
Which is the Overpower Compensation
Applied
Figure 32. FB Pin Level VFB(OPCE) Below
Which is No Overpower Compensation
Applied
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NCP1247
TYPICAL CHARACTERISTIC
13.0
12.8
12.6
12.4
12.2
12.0
11.8
11.6
11.4
11.2
11.0
11.5
11.3
11.1
10.9
10.7
10.5
10.3
10.1
9.9
9.7
9.5
−50
−50
−25
0
25
50
75
100 125
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. VCC Turn−on Threshold Level, VCC
Going Up HV Current Source Stop Threshold
VCC(on)
Figure 34. HV Current Source Restart
Threshold VCC(min)
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
−50
−25
0
25
50
75
100 125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. VCC Turn−off Threshold (UVLO)
Figure 36. VCC Decreasing Level at Which the
Internal Logic Resets VCC(reset)
VCC(off)
2.0
1.9
1.9
1.8
1.8
1.7
1.7
3.2
3.0
2.8
2.6
2.4
2.2
2.0
I
CC2(100kHz)
I
CC1(100kHz)
I
CC1(65kHz)
I
CC2(65kHz)
−50
−25
0
25
50
75
100 125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. Internal Current Consumption when
DRV Pin is Unloaded
Figure 38. Internal Current Consumption when
DRV Pin is Loaded by 1 nF
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NCP1247
TYPICAL CHARACTERISTIC
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
−50
−25
0
25
50
75
100 125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. X2 Discharge Comparator
Hysteresis Observed at HV Pin VHV(hyst)
Figure 40. HV Signal Sampling Period Tsample
2.6
2.6
2.5
2.5
2.4
2.4
2.3
2.3
2.2
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
0.35
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. FB Pin Voltage Level Above Which
is Entered On Mode VON
Figure 42. FB Pin Voltage Level Below Which
is Entered Off Mode VOFF
150
145
140
135
130
125
120
300
280
260
240
220
200
180
160
140
120
100
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. Fault Timer Duration tfault
Figure 44. Go To Off Mode Timer Duration
tGTOM
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NCP1247
APPLICATION INFORMATION
Functional Description
For loads that are between approximately 32% and 10%
of full rated power, the converter operates in frequency
foldback mode (FFM). If the feedback pin voltage is lower
than 1.5 V the peak switch current is kept constant and the
output voltage is regulated by modulating the switching
The NCP1247 includes all necessary features to build a
safe and efficient power supply based on a fixed−frequency
flyback converter. The NCP1247 is a multimode controller
as illustrated in Figure 45. The mode of operation depends
upon line and load condition. Under all modes of operation,
the NCP1247 terminates the DRV signal based on the switch
current. Thus, the NCP1247 always operates in current
mode control so that the power MOSFET current is always
limited.
Under normal operating conditions, the FB pin commands
the operating mode of the NCP1247 at the voltage
thresholds shown in Figure 45. At normal rated operating
loads (from 100% to approximately 33% full rated power)
the NCP1247 controls the converter in fixed frequency
PWM mode. It can operate in the continuous conduction
mode (CCM) or discontinuous conduction mode (DCM)
depending upon the input voltage and loading conditions. If
the controller is used in CCM with a wide input voltage
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.
frequency for a given and fixed input voltage V
.
HV
Effectively, operation in FFM results in the application of
constant volt−seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by
varying the switching frequency in the range from 65 kHz
(or 100 kHz) to 27 kHz. For extremely light loads (below
approximately 6% full rated power), the converter is
controlled using bursts of 27 kHz pulses. This mode is called
as skip mode. The FFM, keeping constant peak current and
skip mode allows design of the power supplies with
increased efficiency under the light loading conditions.
Keep in mind that the aforementioned boundaries of
steady−state operation are approximate because they are
subject to converter design parameters.
Low consumption off mode
ON
OFF
Fixed Ipeak
FFM
PWM at fOSC
Skip mode
0 V
3.5 V
VFB
0.4 V 0.7 V 1.1 V
0.8 V
1.5V
2.0 V 2.2 V
Figure 45. Mode Control with FB pin voltage
There was implemented the low consumption off mode
allowing to reach extremely low no load input power. This
mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply
shut−down. Most of the device internal circuitry is unbiased
in the low consumption off mode. Only the FB pin control
circuitry and X2 cap discharging circuitry is operating in the
low consumption off mode. If the voltage at feedback pin
decreases below the 0.4 V the controller will enter the low
consumption off mode. The controller can start if the FB pin
voltage increases above the 2.2 V level.
See the detailed status diagrams for the versions fully
latched A/C and the autorecovery B/D on the following
figures. The basic status of the device after wake–up by the
V
CC
is the off mode and mode is used for the overheating
protection mode if the thermal shutdown protection is
activated.
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NCP1247
V
> V
CCreset
CC
(V > V )*Latch
FB
ON
(V
+MaxDC)*t
fault
ILIM
Figure 46. Operating Status Diagram for the Fully Latched Versions A/C of the Device
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NCP1247
V
> V
CCreset
CC
(V > V )*Latch
FB
ON
BO+t
autorec
(V
+ MaxDC)*t
fault
ILIM
Figure 47. Operating Status Diagram for the Autorecovery Versions B/D of the Device
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NCP1247
The information about the fault (permanent Latch or
Even though the Dynamic Self−Supply is able to maintain
the V voltage between V and V by turning
the HV start−up current source on and off, it can only be used
in light load condition, otherwise the power dissipation on
the die would be too much. As a result, an auxiliary voltage
Autorecovery) is kept during the low consumption off mode
due the safety reason. The reason is not to allow unlatch the
device by the remote control being in off mode.
CC
CC(on)
CC(min)
Start−up of the Controller
At start−up, the current source turns on when the voltage
source is needed to supply V during normal operation.
CC
The Dynamic Self−Supply is useful to keep the controller
alive when no switching pulses are delivered, e.g. in
brown−out condition, or to prevent the controller from
on the HV pin is higher than V , and turns off when
HV(min)
V
V
reaches V , then turns on again when V reaches
CC(on) CC
CC
, until the input voltage is high enough to ensure a
CC(min)
stopping during load transients when the V might drop.
CC
proper start−up, i.e. when V
reaches V
. The
HV
HV(start)
The NCP1247 accepts a supply voltage as high as 28 V, with
controller actually starts the next time V reaches V
.
CC
CC(on)
an overvoltage threshold V
off.
that latches the controller
CC(ovp)
The controller then delivers pulses, starting with a soft−start
period t during which the peak current linearly
SSTART
increases before the current−mode control takes over.
VHV
VHV(start)
VHV(min)
Waits next
before starting
VCC(on)
time
VCC
VCC(on)
VCC(min)
HV current
source = Istart1
HV current
source = Istart2
VCC(inhibit)
time
time
DRV
Figure 48. VCC Start−up Timing Diagram
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NCP1247
For safety reasons, the start−up current is lowered when
is below V , to reduce the power dissipation in
threshold and an autorecovery brown−out protection; both
V
CC
of them independent of the ripple on the input voltage. It is
allowed only to work with an unfiltered, rectified ac input to
ensure the X2 capacitor discharge function as well, which is
described in following. The brown−out protection
thresholds are fixed, but they are designed to fit most of the
standard ac−dc conversion applications.
CC(inhibit)
case the V pin is shorted to GND (in case of V capacitor
CC
CC
failure, or external pull−down on V
to disable the
CC
controller). There is only one condition for which the current
source doesn’t turn on when V reaches V : the
CC
CC(inhibit)
voltage on HV pin is too low (below V
).
HV(min)
When the input voltage goes below V
, a
HV(stop)
HV Sensing of Rectified AC Voltage
The NCP1247 features on its HV pin a true ac line
monitoring circuitry. It includes a minimum start−up
brown−out condition is detected, and the controller stops.
The HV current source maintains V at V level until
CC
CC(min)
the input voltage is back above V
.
HV(start)
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NCP1247
Figure 49. Ac Line Drop−out Timing Diagram
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NCP1247
Figure 50. Ac Line Drop−out Timing Diagram with the Parasitic Spike
When V crosses the V
can start immediately. When it crosses V
threshold, the controller
immediately after the device is stopped by the residual
energy in the EMI filter. The device restart is allowed only
after the 1st watch dog signal event. The basic principle is
shown at Figure 49 and detail of the device restart is shown
at Figure 51.
HV
HV(start)
, it triggers
HV(stop)
a timer of duration t , this ensures that the controller
HV
doesn’t stop in case of line cycle drop−out. The device restart
after the ac line voltage drop-out is protected to the parasitic
restart initiated e.g. the spikes induced at HV pin
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NCP1247
Figure 51. Detailed Timing Diagram of the Device Restart After the Short ac Line Drop−out
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NCP1247
X2 Cap Discharge Feature
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal during the presence of this signal. No edges are
present at the output of the comparator, that’s why the
detection timer is not reset and dc detect signal appears.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
The X2 capacitor discharging feature is offered by usage
of the NCP1247. This feature save approx. 16 mW − 25 mW
input power depending on the EMI filter X2 capacitors
volume and it saves the external components count as well.
The discharge feature is ensured via the start−up current
source with a dedicated control circuitry for this function.
The X2 capacitors are being discharged by current defined
as I
when this discharge event is detected.
start2
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 52 for the block diagram for this structure and
Figures 53, 54, 55 and 56 for the timing diagrams. The basic
idea of ac line unplug detector lies in comparison of the
direct sample of the high voltage obtained via the high
voltage sensing structure with the delayed sample of the high
voltage. The delayed signal is created by the sample & hold
structure.
HV pin V
and the sampling time:
HV(hyst),max
VHV(hyst),max
(eq. 1)
Smin
+
Tsample
Than it can be derived the relationship between the
minimum detectable slope and the amplitude and frequency
of the sinusoidal input voltage:
VHV(hyst),max
2 @ p @ f @ Tsample
5
2 @ p @ 35 @ 1 @ 10−3
Vmax
+
+
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
(eq. 2)
+ 22.7 V
sampling time T
These parameters ensure the noise immunity as well. The
additional offset is added to the picture of the sampled HV
and additional internal offset N
.
SAMPLE
OS
The minimum detectable AC RMS voltage is 16 V at
frequency 35 Hz, if the maximum hysteresis is 5 V and
sampling time is 1 ms.
The X2 capacitor discharge feature is available in any
controller operation mode to ensure this safety feature. The
detection timer is reused for the time limiting of the
discharge phase, to protect the device against overheating.
The discharging process is cyclic and continues until the ac
line is detected again or the voltage across the X2 capacitor
signal and its analog sum is stored in the C storage
1
capacitor. If the voltage level of the HV sensing structure
output crosses this level the comparator CMP output signal
resets the detection timer and no dc signal is detected. The
additional offset N can be measured as the V
on
OS
HV(hyst)
the HV pin. If the comparator output produces pulses it
means that the slope of input signal is higher than set
resolution level and the slope is positive. If the comparator
output produces the low level it means that the slope of input
signal is lower than set resolution level or the slope is
negative. There is used the detection timer which is reset by
any edge of the comparator output. It means if no edge
comes before the timer elapses there is present only dc signal
or signal with the small ac ripple at the HV pin. This type of
the ac detector detects only the positive slope, which fulfils
the requirements for the ac line presence detection.
is lower than V
). This feature ensures to discharge
HV(min
quite big X2 capacitors used in the input line filter to the safe
level. It is important to note that it is not allowed to
connect HV pin to any dc voltage due this feature. e.g.
directly to bulk capacitor.
During the HV sensing or X2 cap discharging the V net
CC
is kept above the V
voltage by the Self−Supply in any
CC(off)
mode of device operation to supply the control circuitry.
During the discharge sequence is not allowed to start−up the
device.
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NCP1247
Figure 52. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System
Figure 53. The ac Line Unplug Detector Timing Diagram
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NCP1247
Figure 54. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects
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NCP1247
Figure 55. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under Extremely Low Line Condition
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NCP1247
Figure 56. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line Condition
The Low Consumption Off Mode
Only the X2 cap discharge and Self−Supply features is
enabled in the low consumption off mode. The X2 cap
discharging feature is enable due the safety reasons and the
There was implemented the low consumption off mode
allowing to reach extremely low no load input power as
described in previous chapters. If the voltage at feedback pin
decreases below the 0.4 V the controller enters the off mode.
Self−Supply is enabled to keep the V supply, but only
CC
very low V consumption appears in this mode. Any other
CC
The internal V is turned−off, the IC consumes extremely
features are disabled in this mode.
CC
low V
current and only the voltage at external V
The information about the latch status of the device is kept
in the low consumption off mode and this mode is used for
the TSD protection as well. The protection timer
CC
CC
capacitor is maintained by the Self−Supply circuit. The
Self−Supply circuit keeps the V voltage at the V
CC
CC(reg)
level. The supply for the FB pin watch dog circuitry and FB
pin bias is provided via the low consumption current sources
GoToOffMode t
is used to protect the application
GTOM
against the false activation of the low consumption off mode
by the fast drop outs of the FB pin voltage below the 0.4 V
level. E.g. in case when is present high FB pin voltage ripple
during the skip mode.
from the external V capacitor. The controller can only
CC
start, if the FB pin voltage increases above the 2.2 V level.
See Figure 57 for timing diagrams.
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NCP1247
Figure 57. Start−up, Shutdown and AC Line Unplug Time Diagram
Oscillator with Maximum On Time and Frequency
Jittering
The NCP1247 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum on time is 12.3 ms (for 65 kHz
version) or 8 ms (for 100 kHz version) with an accuracy of
7%. The maximum on time corresponds to maximum duty
cycle of the DRV pin is 80% at full switching frequency. In
order to improve the EMI signature, the switching frequency
jitters 6 % around its nominal value, with a triangle−wave
shape and at a frequency of 125 Hz. This frequency jittering
is active even when the frequency is decreased to improve
the efficiency in light load condition.
Figure 58. Frequency Modulation of the Maximum
Switching Frequency
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NCP1247
Low Load Operation Modes: Frequency Foldback
Mode (FFM) and Skip Mode
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
frequency foldback mode to provide the natural transformer
core anti−saturation protection. The frequency jittering is
still active while the oscillator frequency decreases as well.
The current setpoint is fixed to 300 mV in the frequency
foldback mode if the feedback voltage decreases below the
from its nominal value down to f . This frequency
OSC(min)
foldback starts when the voltage on FB pin goes below
, and is complete when V reaches V
V
level. This feature increases efficiency under the
FB(freeze)
V
.
FB(foldE)
FB(foldS)
FB
light loads conditions as well.
The maximum on−time duration control is kept during the
Figure 59. Frequency Foldback Mode Characteristic
Figure 60. Current Setpoint Dependency on the Feedback Pin Voltage
When the FB voltage reaches V
while decreasing,
below V , the controller remains in this state; but as
skip(out)
skip(in)
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While V is
soon as V crosses the skip out threshold, the DRV pin
starts to pulse again.
FB
FB
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NCP1247
Figure 61. Skip Mode Timing Diagram
Figure 62. Technique Preventing Short Pulses in Skip Mode
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NCP1247
Clamped Driver
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off. The maximum value for the
current sense is 0.7 V, and it is set by a dedicated comparator.
Each time the controller is starting, i.e. the controller was
The supply voltage for the NCP1247 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical capability of 500 mA for source current
and 800 mA for sink current.
off and starts – or restarts – when V reaches V
, a
CC
CC(on)
Current−Mode Control With Slope Compensation and
Soft−Start
NCP1247 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
soft−start is applied: the current sense setpoint is increased
by 15 discrete steps from 0 (the minimum level can be
higher than 0 because of the LEB and propagation delay)
until it reaches V
(after a duration of t ), or until
SSTART
ILIM
the FB loop imposes a setpoint lower than the one imposed
by the soft−start (the two comparators outputs are OR’ed).
Figure 63. Soft−Start Feature
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above V
,
ILIM
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
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NCP1247
voltage on CS pin reaches V
as soon as this comparator toggles, the controller
immediately enters the protection mode.
In order to allow the NCP1247 to operate in CCM with a
duty cycle above 50%, the fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
( = 1.5 x V
), does:
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version. The slope
compensation can be observable as a value of the peak
current at CS pin.
The internal slope compensation circuitry uses a sawtooth
signal synchronized with the internal oscillator is subtracted
CS(stop)
ILIM
from the FB voltage divided by K
.
FB
Figure 64. Slope Compensation Block Diagram
Figure 65. Slope Compensation Timing Diagram
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NCP1247
Internal Overpower Protection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current in
discontinuous conduction mode:
1
2
2
(eq. 3)
POUT
+
@ h @ LP @ FSW @ IP
Figure 66. Needs for Line Compensation For True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V
. However, because the HV pin is
FB(OPCE)
being connected to ac voltage, there is needed an additional
circuitry to read or at least closely estimate the actual voltage
on the bulk capacitor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
Figure 67. Overpower Protection Current Relation to Feedback Voltage
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NCP1247
Figure 68. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
Figure 69. Block Schematic of Overpower Protection Circuit
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the output from the ac
line unplug detector. The sensed HV pin voltage peak value
is validated when no HV edges from comparator are present
after last falling edge during two sample clocks. See
Figure 70 for details.
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NCP1247
Overcurrent Protection with Fault timer
the latch release are the brown−out condition or the V
CC
The overload protection depends only on the current
sensing signal, making it able to work with any transformer,
even with very poor coupling or high leakage inductance.
When an overcurrent occurs on the output of the power
supply, the FB loop asks for more power than the controller
power on reset. The timer is reset when the CS setpoint goes
back below V before the timer elapses. The fault timer
is also started if the driver signal is reset by the maximum on
time. The controller also enters the same protection mode if
the voltage on the CS pin reaches 1.5 times the maximum
ILIM
can deliver, and the CS setpoint reaches V . When this
ILIM
internal setpoint V
(allows to detect winding
CS(stop)
event occurs, an internal t
timer is started: once the timer
short−circuits) or there appears low V
supply. See
fault
CC
times out, DRV pulses are stopped and the controller is either
latched off (latched protection, options A/C) or this latch can
be released in autorecovery mode (options B/D), the
Figures 71 and 72 for the timing diagram.
In autorecovery mode if the fault has gone, the supply
resumes operation; if not, the system starts a new burst cycle.
controller tries to restart after t
. Other possibilities of
autorec
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NCP1247
VHVSAMPLE
TSAMPLE
VHV(hyst)
time
time
time
1st HV edge
resets the watch
dog and starts
the peak
detection of HV
pin signal
Comparator
Output
Sample clock
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
2nd sample clock
Watch dog
signal
pulse after last
HV edge initiates
the watch dog
signal
time
Peak detector
Reset
Reset
time
time
Sample
Sample
IOPC
Figure 70. Overpower Compensation Timing Diagram
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NCP1247
PROTECTION MODES AND THE LATCH MODE RELEASES
Event
Timer Protection
Next Device Status
Release to Normal Operation Mode
Overcurrent
ILIM
Fault timer
Latch
Autorecovery – B/D version
V
> 0.7 V
Brown−out
V
CC
< V
CC(reset)
Maximum on time
Fault timer
Immediate reaction
10 ms timer
Latch
Latch
Latch
Autorecovery – B/D version
Brown−out
V
CC
< V
CC(reset)
Winding short
Autorecovery – B/D version
V
> V
Brown−out
sense
CS(stop)
V
< V
CC
CC(reset)
Low supply
< V
Autorecovery – B/D version
V
CC
Brown−out
CC(off)
V
V
V
< V
CC
CC(reset)
External OTP, OVP
55 ms (35 ms at 100 kHz)
10 ms timer
Latch
Latch
Brown−out
< V
CC
CC(reset)
High supply
CC
Brown−out
< V
CC(reset)
V
> V
CC(ovp)
CC
Brown−out
< V
HV timer
Device stops
(V > V
) & (V > V
)
HV
HV(start)
CC
CC(on)
V
HV
HV(stop)
Internal TSD
10 ms timer
Device stops, HV start−up
current source stops
(V > V
) & (V > V
) & TSDb
CC(on)
HV
HV(start)
CC
Off mode
150 ms timer
Device stops and internal
(V > V
) & (V > V
) &
CC(on)
HV
HV(start)
CC
V
< V
V
is turned off
(V > V
)
FB
OFF
CC
FB
ON
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NCP1247
V
CC(on)
V
CC(min)
Figure 71. Latched Timer−Based Overcurrent Protection (Options A/C)
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NCP1247
V
CC(on)
V
CC(min)
Figure 72. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Options B/D)
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NCP1247
Latch−Off Input
Figure 73. Latch Detection Schematic
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run, but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
Reset occurs when a brown−out condition is detected or
the V is cycled down to a reset voltage, which in a real
CC
application can only happen if the power supply is
unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
source I
.
NTC
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I current. To
before the controller is ready to start: once V reaches
CC
V , the latch pin High latch state is taken into account
CC(on)
NTC
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft−start is finished. In
1.5 mA at V ).
OVP
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
addition, the NTC current is doubled to I
during
NTC(SSTART)
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
t
SSTART min @ INTC(SSTART) min
8.0 @ 10−3 @ 130 @ 10−6
(eq. 4)
F + 1.04 mF
CLATCH max
+
+
1.0
Vclamp0 min
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NCP1247
V
CC(on)
V
CC(min)
Figure 74. Latch Timing Diagram
Temperature Shutdown
The NCP1247 includes
low power consumption. There is kept the V supply to
keep the TSD information. When the temperature falls
CC
a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the controller stops switching
instantaneously, and goes to the off mode with extremely
below the low threshold, the start−up of the device is enabled
again, and a regular start−up sequence takes place. See the
status diagrams at the Figures 46 and 47.
ORDERING INFORMATION
†
Ordering Part No.
NCP1247AD065R2G
NCP1247BD065R2G
NPC1247CD065R2G
NCP1247DD065R2G
NCP1247AD100R2G
NCP1247BD100R2G
NCP1247CD100R2G
NCP1247DD100R2G
Overload Protection
Latched
Switching Frequency
Package
Shipping
Autorecovery
Latched
SOIC−7
(Pb−Free)
65 kHz
2500 / Tape & Reel
Autorecovery
Latched
Autorecovery
Latched
SOIC−7
(Pb−Free)
100 kHz
2500 / Tape & Reel
Autorecovery
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1247
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
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NCP1247/D
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