NTB18N06T4G [ONSEMI]
Power MOSFET 15 A, 60 V, N−Channel TO−220 & D2PAK; 功率MOSFET 15 A， 60 V ， N沟道TO- 220和D2PAK
| 型号： | NTB18N06T4G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 15 A, 60 V, N−Channel TO−220 & D2PAK |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTP18N06, NTB18N06
Power MOSFET
15 A, 60 V, N−Channel TO−220 & D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
N−Channel
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Typical Applications
• Power Supplies
D
V
R
DS(on)
TYP
I MAX
D
(BR)DSS
• Converters
60 V
90 mW @ 10 V
15 A
• Power Motor Controls
• Bridge Circuits
G
• Pb−Free Packages are Available
S
4
4
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol Value Unit
1
2
3
Drain−to−Source Voltage
V
60
60
Vdc
Vdc
Vdc
DSS
DGR
2
Drain−to−Gate Voltage (R = 10 mW)
V
TO−220AB
CASE 221A
STYLE 5
D PAK
CASE 418AA
STYLE 2
GS
1
Gate−to−Source Voltage
− Continuous
V
GS
2
ꢁ 20
ꢁ 30
3
− Non−Repetitive (t
ꢀ
10 ms)
p
Drain Current
− Continuous @ T = 25°C
I
I
15
8.0
45
Adc
Adc
A
pk
C
D
D
MARKING DIAGRAMS
& PIN ASSIGNMENTS
− Continuous @ T = 100°C
C
− Single Pulse (t ꢀ 10 ms)
I
p
DM
4
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
48.4
0.32
W
W/°C
C
D
Drain
4
Drain
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
J
stg
NTx
18N06G
AYWW
Single Pulse Drain−to−Source Avalanche
E
61
mJ
AS
Energy − Starting T = 25°C
J
NTx18N06G
AYWW
(V = 25 Vdc, V = 10 Vdc, V = 60 Vdc,
DD
GS
DS
I
= 11 A, L = 1.0 mH, R = 25 W)
G
L(pk)
1
Gate
3
1
2
3
Thermal Resistance
− Junction−to−Case
°C/W
°C
Source
Gate Drain Source
R
R
3.1
72.5
q
JC
− Junction−to−Ambient
q
JA
2
Drain
Maximum Lead Temperature for Soldering
T
260
L
Purposes, (1/8″ from case for 10 s)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
NTx18N06 = Device Code
x
= B or P
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 4
NTP18N06/D
NTP18N06, NTB18N06
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 1)
(V = 0 Vdc, I = 250 mAdc)
V
Vdc
(BR)DSS
60
−
67
62.4
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
I
DSS
GSS
(V = 0 Vdc, V = 60 Vdc)
−
−
−
−
1.0
10
GS
DS
(V = 0 Vdc, V = 60 Vdc, T = 150°C)
GS
DS
J
Gate−Body Leakage Current (V
=
20 Vdc, V = 0 Vdc)
−
−
100
nAdc
Vdc
GS
DS
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage (Note 1)
V
GS(th)
(V = V
I = 250 mAdc)
GS, D
2.0
−
2.9
6.2
4.0
−
DS
Threshold Temperature Coefficient (Negative)
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 1)
(V = 10 Vdc, I = 7.5 Adc)
GS
R
V
DS(on)
−
76
90
D
Static Drain−to−Source On−Voltage (Note 1)
(V = 10 Vdc, I = 15 Adc)
Vdc
DS(on)
−
−
1.2
1.08
1.62
−
GS
D
(V = 10 Vdc, I = 7.5 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 1) (V = 7.0 Vdc, I = 6.0 Adc)
g
FS
−
6.8
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
−
−
−
325
108
34
450
150
70
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
t
−
−
−
−
−
−
−
10
25
14
13
12
4.1
4.5
15
70
50
50
22
−
ns
d(on)
(V = 30 Vdc, I = 15 Adc,
DD
D
t
r
V
= 10 Vdc,
GS
Turn−Off Delay Time
Fall Time
t
d(off)
R
G
= 9.1 W) (Note 1)
t
f
Gate Charge
Q
nC
t
(V = 48 Vdc, I = 15 Adc,
DS
D
Q
Q
1
2
V
= 10 Vdc) (Note 1)
GS
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Diode Forward On−Voltage
(I = 15 Adc, V = 0 Vdc) (Note 1)
V
SD
−
−
0.95
0.84
1.15
−
Vdc
ns
S
GS
(I = 15 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
35
27
−
−
−
−
rr
t
a
(I = 15 Adc, V = 0 Vdc,
S
GS
t
7.4
b
dI /dt = 100 A/ms) (Note 1)
S
Reverse Recovery Stored
Charge
Q
0.050
mC
RR
1. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
2. Switching characteristics are independent of operating junction temperature.
ORDERING INFORMATION
†
Device
Package
Shipping
NTP18N06
TO−220AB
50 Units / Rail
50 Units / Rail
NTP18N06G
TO−220AB
(Pb−Free)
2
NTB18N06
50 Units / Rail
50 Units / Rail
D PAK
2
NTB18N06G
D PAK
(Pb−Free)
2
NTB18N06T4
800 Units / Tape & Reel
800 Units / Tape & Reel
D PAK
2
NTB18N06T4G
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTP18N06, NTB18N06
32
24
16
32
V
= 10 V
GS
V
≥ 10 V
DS
8 V
9 V
7 V
24
6.5 V
16
6 V
T = 25°C
J
5.5 V
8
0
8
0
5 V
T = 100°C
J
4.5 V
T = −55°C
J
0
1
2
3
4
5
3
4
5
6
7
8
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.2
0.2
V
= 10 V
V
= 15 V
GS
GS
0.16
0.16
T = 100°C
J
T = 100°C
J
0.12
0.08
0.12
0.08
T = 25°C
J
T = 25°C
J
T = −55°C
J
T = −55°C
J
0.04
0
0.04
0
0
4
8
12
16
20
24
28
32
0
4
8
12
16
20
24
28
32
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1.8
1.6
1000
100
I
V
= 7.5 A
D
V
= 0 V
GS
= 10 V
GS
T = 150°C
J
1.4
1.2
1
10
1
T = 100°C
J
0.8
0.6
−50 −25
0
25
50
75 100 125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTP18N06, NTB18N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
900
V
= 0 V
V
= 0 V
GS
DS
800
700
600
500
400
300
200
T = 25°C
J
C
C
iss
rss
C
C
iss
oss
100
0
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTP18N06, NTB18N06
1000
12
10
8
V
= 30 V
= 15 A
= 10 V
DS
GS
I
D
Q
T
V
V
GS
t
r
Q
Q
t
2
1
d(on)
t
d(off)
10
6
t
f
4
2
0
I
= 15 A
D
T = 25°C
J
1
0
2
4
6
8
10
12
1
10
R , GATE RESISTANCE (W)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
V
= 0 V
GS
T = 25°C
J
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTP18N06, NTB18N06
SAFE OPERATING AREA
100
10
80
I
= 11 A
V
= 20 V
D
GS
SINGLE PULSE
10 ms
T
= 25°C
C
60
100 ms
1 ms
40
10 ms
1
dc
20
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
0.1
1
10
100
25
50
75
100
125
150
175
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
t, TIME (s)
0.01
0.1
1
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
NTP18N06, NTB18N06
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
−B−
W
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.92
1.40
−−−
A
S
1
2
3
0.310
−−−
G
J
K
M
S
V
0.100 BSC
0.018 0.025
0.090 0.110
2.54 BSC
0.46
2.29
7.11
0.64
2.79
−−−
−T−
SEATING
PLANE
K
W
0.280
−−−
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
J
G
STYLE 2:
PIN 1. GATE
D 3 PL
M
M
0.13 (0.005)
T B
2. DRAIN
3. SOURCE
4. DRAIN
VARIABLE
CONFIGURATION
ZONE
U
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ꢂ
ꢃ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTP18N06, NTB18N06
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
−−− 0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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NTP18N06/D
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