NTD110N02R-1
更新时间：2024-09-18 19:09:41
品牌：ONSEMI
描述：32A, 24V, 0.0062ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 369D-01, DPAK-3
概述
规格参数
数据手册NTD110N02R-1 概述
32A, 24V, 0.0062ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 369D-01, DPAK-3 功率场效应晶体管
NTD110N02R-1 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 包装说明： | CASE 369D-01, DPAK-3 | 针数： | 3 |
| Reach Compliance Code： | not_compliant | HTS代码： | 8541.29.00.95 |
| 风险等级： | 5.92 | 雪崩能效等级（Eas）： | 120 mJ |
| 外壳连接： | DRAIN | 配置： | SINGLE WITH BUILT-IN DIODE |
| 最小漏源击穿电压： | 24 V | 最大漏极电流 (Abs) (ID)： | 32 A |
| 最大漏极电流 (ID)： | 32 A | 最大漏源导通电阻： | 0.0062 Ω |
| FET 技术： | METAL-OXIDE SEMICONDUCTOR | JESD-30 代码： | R-PSIP-T3 |
| JESD-609代码： | e0 | 元件数量： | 1 |
| 端子数量： | 3 | 工作模式： | ENHANCEMENT MODE |
| 最高工作温度： | 150 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 峰值回流温度（摄氏度）： | 240 | 极性/信道类型： | N-CHANNEL |
| 最大功率耗散 (Abs)： | 92.5 W | 最大脉冲漏极电流 (IDM)： | 110 A |
| 认证状态： | Not Qualified | 子类别： | FET General Purpose Power |
| 表面贴装： | NO | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | THROUGH-HOLE | 端子位置： | SINGLE |
| 处于峰值回流温度下的最长时间： | 30 | 晶体管应用： | SWITCHING |
| 晶体管元件材料： | SILICON | Base Number Matches： | 1 |
NTD110N02R-1 数据手册
通过下载NTD110N02R-1数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载NTD110N02R
Power MOSFET
110 Amps, 24 Volts
N-Channel DPAK
Features
http://onsemi.com
• Planar HD3e Process for Fast Switching Performance
• Low R
to Minimize Conduction Loss
DS(on)
V
R
TYP
I
MAX
(BR)DSS
DS(on)
D
• Low C to Minimize Driver Loss
iss
24 V
3.7 mW @ 4.5 V
110 A
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High-Efficiency DC-DC Converters
N-Channel
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
Unit
Drain-to-Source Voltage
V
24
Vdc
Vdc
DSS
G
4
Gate-to-Source Voltage - Continuous
Thermal Resistance - Junction-to-Case
Total Power Dissipation @ T = 25°C
V
±20
GS
R
P
1.35
92.5
°C/W
W
q
JC
S
A
D
4
Drain Current
- Continuous @ T = 25°C, Chip
I
I
110
110
A
A
A
D
1
2
1
- Continuous @ T = 25°C,
2
A
D
D
D
3
3
Limited by Package
- Continuous @ T = 25°C,
I
I
32
A
A
CASE 369D
DPAK
(Straight Lead)
STYLE 2
CASE 369C
DPAK
(Surface Mount)
STYLE 2
A
Limited by Wires
- Single Pulse (t = 10 ms)
110
p
Thermal Resistance
- Junction-to-Ambient (Note 1)
R
P
I
52
2.4
17
°C/W
W
A
q
JA
- Total Power Dissipation @ T = 25°C
A
D
MARKING DIAGRAM
& PIN ASSIGNMENTS
- Drain Current - Continuous @ T = 25°C
A
D
Thermal Resistance
4
- Junction-to-Ambient (Note 2)
R
P
I
100
1.25
12
°C/W
W
A
q
JA
4
Drain
- Total Power Dissipation @ T = 25°C
A
D
Drain
- Drain Current - Continuous @ T = 25°C
A
D
Operating and Storage
Temperature Range
T , T
- 55 to
150
°C
J
stg
Single Pulse Drain-to-Source Avalanche
E
AS
120
mJ
Energy - Starting T = 25°C
J
(V = 50 Vdc, V = 10 Vdc,
DD
GS
2
1
Gate
3
I = 15.5 Apk, L = 1.0 mH, R = 25 W)
L
G
Drain
Source
1
2
3
Maximum Lead Temperature for Soldering
T
L
260
°C
Gate Drain Source
Purposes, 1/8″ from case for 10 seconds
Y
WW
= Year
= Work Week
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
110N02R = Device Code
ORDERING INFORMATION
Device
Package
Shipping
NTD110N02R
DPAK
DPAK
75 Units/Rail
NTD110N02RT4
2500/Tape & Reel
DPAK
Straight Lead
NTD110N02R-1
75 Units/Rail
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
May, 2003 - Rev. 2
NTD110N02R/D
NTD110N02R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 3)
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 250 mAdc)
Positive Temperature Coefficient
24
-
28
15
-
-
GS
D
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 20 Vdc, V = 0 Vdc)
-
-
-
-
1.5
10
DS
GS
(V = 20 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate-Body Leakage Current (V = ±20 Vdc, V = 0 Vdc)
I
-
-
±100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(V = V , I = 250 mAdc)
V
GS(th)
1.0
-
1.5
5.0
2.0
-
DS
GS
D
Negative Threshold Temperature Coefficient
Static Drain-to-Source On-Resistance (Note 3)
(V = 10 Vdc, I = 110 Adc)
mV/°C
mW
R
DS(on)
-
-
-
-
3.7
4.9
3.7
4.7
-
-
GS
D
(V = 4.5 Vdc, I = 55 Adc)
GS
D
(V = 10 Vdc, I = 20 Adc)
4.6
6.2
GS
D
(V = 4.5 Vdc, I = 20 Adc)
GS
D
Forward Transconductance (V = 10 Vdc, I = 15 Adc) (Note 3)
g
FS
-
44
-
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
C
-
-
-
2710
1105
227
3440
1670
640
iss
(V = 20 Vdc, V = 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
t
-
-
-
-
-
-
-
11
39
22
80
40
40
28
-
ns
d(on)
Rise Time
t
r
(V = 10 Vdc, V = 10 Vdc,
GS
DD
I
D
= 40 Adc, R = 3.0 W)
G
Turn-Of f Delay Time
Fall Time
t
27
d(off)
t
f
21
Gate Charge
Q
23.6
5.1
11
nC
T
(V = 4.5 Vdc, I = 40 Adc,
GS
D
Q1
Q2
V
DS
= 10 Vdc) (Note 3)
-
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage
V
-
-
-
0.82
0.99
0.65
1.2
-
-
Vdc
ns
(I = 20 Adc, V = 0 Vdc) (Note 3)
SD
S
GS
(I = 55 Adc, V = 0 Vdc)
S
GS
(I = 20 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
t
-
-
-
-
36.5
17.7
-
-
-
-
rr
(I = 30 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 3)
S
t
18.8
b
Reverse Recovery Stored Charge
Q
0.024
mC
rr
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD110N02R
200
160
120
80
200
4.0 V
4.5 V
3.5 V
V
DS
≥ 10 V
160
120
80
5.0 V
6.0 V
8.0 V
10 V
3.0 V
T = 125°C
J
V
GS
= 2.5 V
T = 25°C
J
40
0
40
0
T
J
= -55°C
0
2
4
6
8
10
0
0.8
1.6
2.4
3.2
4.0
V
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
, GATE-T O-SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.01
0.008
0.006
0.01
0.008
0.006
V
= 4.5 V
= 10 V
GS
GS
T = 125°C
J
T = 125°C
J
T = 25°C
J
T = 25°C
J
T
J
= -55°C
0.004
0.002
0.004
0.002
T
J
= -55°C
0
40
80
120
160
200
0
40
80
120
160
200
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On-Resistance versus Drain Current
and Temperature
Figure 4. On-Resistance versus Drain Current
and Temperature
100,000
10,000
1.8
1.6
1.4
1.2
1.0
V
GS
= 0 V
I
V
= 55 A
D
= 4.5 V
GS
T = 150°C
J
T = 125°C
J
1000
100
10
T = 100°C
J
0.8
0.6
-50 -25
0
25
50
75
100
125 150
0
4.0
8.0
12
16
20
24
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with
Temperature
Figure 6. Drain-to-Source Leakage Current
versus Voltage
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3
NTD110N02R
10
7000
6000
5000
4000
3000
2000
V
= 0 V
= 0 V
V
DS
GS
C
C
iss
8.0
6.0
V
GS
rss
Q
T
C
iss
4.0
Q
Q
2
1
C
C
oss
2.0
0
I
= 40 A
D
1000
0
T = 25°C
J
rss
T = 25°C
J
10
5
0
5
10
15
20
0
8
16
24
32
40
48
V
GS
V
DS
Q , TOTAL GATE CHARGE (nC)
g
GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and
Drain-to-Source Voltage versus Total Charge
1000
60
50
40
30
20
10
0
V
= 10 V
= 40 A
= 10 V
DS
V
GS
= 0 V
I
D
T = 25°C
J
V
GS
100
t
r
t
d(off)
t
f
t
d(on)
10
1
10
R , GATE RESISTANCE (Ω)
100
0
0.2
0.4
0.6
0.8
1.0
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
V
GS
= 20 V
SINGLE PULSE
= 25°C
T
C
100
1 ms
10 ms
10
R
Limit
dc
DS(on)
Thermal Limit
Package Limit
1.0
0.1
1.0
10
100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NTD110N02R
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.0001
0.01
0.00001
0.001
0.01
0.1
1.0
10
t, TIME (s)
Figure 12. Thermal Response
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5
NTD110N02R
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
6.20
3.0
0.244
0.118
2.58
0.101
5.80
1.6
6.172
0.243
0.228
0.063
mm
inches
ǒ
Ǔ
SCALE 3:1
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6
NTD110N02R
PACKAGE DIMENSIONS
DPAK
CASE 369C-01
ISSUE O
SEATING
PLANE
-T-
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
---
1.27
---
L
H
0.020
0.035 0.050
0.155 ---
---
D 2 PL
M
STYLE 2:
PIN 1. GATE
2. DRAIN
G
0.13 (0.005)
T
3. SOURCE
4. DRAIN
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7
NTD110N02R
PACKAGE DIMENSIONS
DPAK
CASE 369D-01
ISSUE O
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
-T-
2.29 BSC
SEATING
PLANE
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
---
J
F
H
0.155
---
D 3 PL
STYLE 2:
G
M
PIN 1. GATE
0.13 (0.005)
T
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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NTD110N02R/D
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