NTD3055L104-001 [ONSEMI]
单 N 沟道逻辑电平功率 MOSFET 60V，12A，104mΩ;
| 型号： | NTD3055L104-001 |
| 厂家： | 
ONSEMI |
| 描述： | 单 N 沟道逻辑电平功率 MOSFET 60V，12A，104mΩ 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD3055L104,
NTDV3055L104
Power MOSFET
12 A, 60 V, Logic Level N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in power
supplies, converters and power motor controls and bridge circuits.
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Features
• Lower R
DS(on)
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
• Lower V
DS(on)
60 V
104 mW
12 A
• Tighter V Specification
SD
• Lower Diode Reverse Recovery Time
D
• Lower Reverse Recovery Stored Charge
• NTDV and STDV Prefixes for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q101 Qualified and PPAP Capable
N−Channel
G
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Supplies
• Converters
S
4
• Power Motor Controls
• Bridge Circuits
4
1
2
3
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
3
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
DPAK
CASE 369C
STYLE 2
IPAK
CASE 369D
STYLE 2
Drain−to−Source Voltage
V
V
60
60
DSS
Drain−to−Gate Voltage (R = 10 MW)
GS
DGR
Gate−to−Source Voltage, Continuous
V
V
"15
"20
GS
GS
MARKING DIAGRAMS
& PIN ASSIGNMENTS
− Non−Repetitive (t v10 ms)
p
Drain Current
− Continuous @ T = 25°C
I
12
10
45
Adc
Apk
A
D
4
4
− Continuous @ T = 100°C
I
D
A
Drain
Drain
− Single Pulse (t v10 ms)
I
DM
p
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
48
0.32
2.1
W
W/°C
W
A
Total Power Dissipation @ T = 25°C (Note 1)
A
Total Power Dissipation @ T = 25°C (Note 2)
1.5
W
A
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
2
J
stg
1
Gate
3
Drain
Source
1
2
3
Single Pulse Drain−to−Source Avalanche
E
AS
61
mJ
Gate Drain Source
Energy − Starting T = 25°C
J
(V = 25 Vdc, V = 5.0 Vdc, L = 1.0 mH
DD
GS
A
= Assembly Location*
= Device Code
= Year
= Work Week
= Pb−Free Package
I
= 11 A, V = 60 Vdc)
DS
L(pk)
55L104
Y
WW
G
Thermal Resistance, − Junction−to−Case
− Junction−to−Ambient (Note 1)
R
R
R
3.13
71.4
100
°C/W
°C
q
JC
JA
JA
q
− Junction−to−Ambient (Note 2)
q
Maximum Lead Temperature for Soldering
T
260
L
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
Purposes, 1/8″ from case for 10 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size,
2
(Cu Area 1.127 in ).
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
2. When surface mounted to an FR4 board using the minimum recommended
2
pad size, (Cu Area 0.412 in ).
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2016 − Rev. 10
NTD3055L104/D
NTD3055L104, NTDV3055L104
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V = 0 Vdc, I = 250 mAdc)
V
Vdc
(BR)DSS
60
−
70
62.9
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V = 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
GS(th)
(V = V , I = 250 mAdc)
Threshold Temperature Coefficient (Negative)
1.0
−
1.6
4.2
2.0
−
DS
GS
D
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 3)
R
V
DS(on)
(V = 5.0 Vdc, I = 6.0 Adc)
−
89
104
GS
D
Static Drain−to−Source On−Voltage (Note 3)
(V = 5.0 Vdc, I = 12 Adc)
Vdc
DS(on)
−
−
0.98
0.86
1.50
−
GS
D
(V = 5.0 Vdc, I = 6.0 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 3) (V = 8.0 Vdc, I = 6.0 Adc)
g
FS
−
9.1
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
316
105
35
440
150
70
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
−
−
−
−
−
−
−
9.2
104
19
20
210
40
80
20
−
ns
d(on)
Rise Time
t
r
(V = 30 Vdc, I = 12 Adc,
= 5.0 Vdc, R = 9.1 W) (Note 3)
G
DD
D
V
GS
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
40.5
7.4
2.0
4.0
Gate Charge
Q
T
Q
1
Q
2
nC
(V = 48 Vdc, I = 12 Adc,
DS
D
V
GS
= 5.0 Vdc) (Note 3)
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 12 Adc, V = 0 Vdc) (Note 3)
V
SD
−
−
0.95
0.82
1.2
−
Vdc
ns
S
GS
(I = 12 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
35
21
−
−
−
−
(I = 12 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 3)
S
t
b
14
Reverse Recovery Stored Charge
Q
0.04
mC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD3055L104, NTDV3055L104
TYPICAL CHARACTERISTICS
24
24
5 V
V
8 V
6 V
= 10 V
GS
V
DS
≥ 10 V
20
16
12
8
20
16
4.5 V
4 V
12
8
3.5 V
3 V
T = 25°C
J
4
4
0
T = 100°C
J
T = −55°C
J
0
0
1
2
3
4
5
6
7
8
1
1.5
2
2.5
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
3
3.5
4
4.5
5
5.5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.32
0.28
0.24
0.20
0.16
0.12
0.08
V
GS
= 10 V
V
GS
= 5 V
T = 100°C
J
T = 100°C
J
T = 25°C
J
T = 25°C
J
T = −55°C
J
T = −55°C
J
0.04
0
0.04
0
0
4
8
12
16
20
24
0
4
8
12
16
20
24
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1.8
1.6
1.4
1.2
1
10,000
1000
100
V
GS
= 0 V
I
V
= 6 A
D
= 5 V
GS
T = 150°C
J
T = 100°C
J
10
1
0.8
0.6
−50 −25
0
25
50
75 100 125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTD3055L104, NTDV3055L104
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1000
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
C
C
800
600
400
iss
rss
C
C
iss
200
0
oss
C
5
rss
10
5
0
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTD3055L104, NTDV3055L104
6
1000
Q
T
5
4
3
2
Q
Q
2
1
100
t
r
t
f
V
GS
t
d(off)
10
1
t
d(on)
V
= 30 V
= 12 A
= 5 V
DS
I
= 12 A
D
1
0
I
D
T = 25°C
J
V
GS
0
2
4
6
8
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
V
GS
= 0 V
14
12
10
8
T = 150°C
J
T = 25°C
J
6
4
2
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C
qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTD3055L104, NTDV3055L104
SAFE OPERATING AREA
100
10
70
V
= 15 V
I
D
= 11 A
GS
10 ms
SINGLE PULSE
60
T
C
= 25°C
50
40
30
100 ms
1 ms
1
10 ms
dc
20
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
0.02
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
1
0.01
1
t
2
T
- T = P
C
R (t)
q
JC
J(pk)
(pk)
SINGLE PULSE
DUTY CYCLE, D = t /t
1 2
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
0.1
1
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
NTD3055L104, NTDV3055L104
ORDERING INFORMATION
Device
†
Package
Shipping
NTD3055L104G
DPAK
(Pb−Free)
75 Units / Rail
75 Units / Rail
NTD3055L104−1G
NTD3055L104T4G
NTDV3055L104−1G
IPAK
(Pb−Free)
DPAK
(Pb−Free)
2500 / Tape & Reel
75 Units / Rail
IPAK
(Pb−Free)
NTDV3055L104T4G*
STDV3055L104T4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NTDV and STDV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable.
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7
NTD3055L104, NTDV3055L104
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
L4
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
b2 0.028 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2 0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3 0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW
STYLE 2:
PIN 1. GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
NTD3055L104, NTDV3055L104
PACKAGE DIMENSIONS
IPAK
CASE 369D
ISSUE C
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
G
M
T
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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