NTD4970NT4G [ONSEMI]
单 N 沟道，功率 MOSFET，30V，36A，11mΩ;
| 型号： | NTD4970NT4G |
| 厂家： | 
ONSEMI |
| 描述： | 单 N 沟道，功率 MOSFET，30V，36A，11mΩ 开关 脉冲 晶体管 |
| 文件： | 总7页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD4970N
Power MOSFET
30 V, 36 A, Single N−Channel, DPAK/IPAK
Features
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
V
R
MAX
I
D
MAX
(BR)DSS
DS(ON)
11 mW @ 10 V
21 mW @ 4.5 V
30 V
Applications
36 A
• CPU Power Delivery
• DC−DC Converters
D
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
30
Unit
V
DSS
V
V
A
G
V
GS
20
Continuous Drain
Current R
I
D
T = 25°C
11.6
A
S
q
JA
N−CHANNEL MOSFET
T = 100°C
A
8.2
(Note 1)
Power Dissipation
(Note 1)
T = 25°C
A
P
2.55
W
A
D
D
D
4
4
R
q
JA
4
Continuous Drain
Current R
I
D
T = 25°C
A
8.5
6.0
q
JA
T = 100°C
A
Steady
State
(Note 2)
Power Dissipation
(Note 2)
2
1
1
T = 25°C
A
P
I
1.38
W
A
1
2
3
3
2
R
q
JA
3
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
36
25
CASE 369AC
3 IPAK
(Straight Lead)
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
CASE 369D
IPAK
(Straight Lead
DPAK)
D
C
q
JC
T
C
(Note 1)
Power Dissipation
T
C
P
24.6
W
A
R
(Note 1)
q
JC
Pulsed Drain
Current
t =10ms
p
T = 25°C
A
I
DM
130
38
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Current Limited by Package
T = 25°C
A
I
A
DmaxPkg
4
Drain
Operating Junction and Storage
Temperature
T ,
−55 to
+175
°C
J
4
4
T
STG
Drain
Drain
Source Current (Body Diode)
Drain to Source dV/dt
I
S
22
6.0
11
A
dV/dt
EAS
V/ns
mJ
Single Pulse Drain−to−Source Avalanche
Energy (T = 25°C, V = 24 V, V = 10 V,
J
DD
GS
I = 15 A , L = 0.1 mH, R = 25 W)
L
pk
G
2
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
T
L
260
°C
1
2
3
Drain
1
3
Gate Drain Source
Gate Source
1
2
3
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
Gate Drain Source
Y
WW
= Year
= Work Week
4970N = Device Code
= Pb−Free Package
G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 0
NTD4970N/D
NTD4970N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
6.1
Unit
Junction−to−Case (Drain)
R
°C/W
q
JC
Junction−to−TAB (Drain)
R
4.3
q
JC−TAB
Junction−to−Ambient – Steady State (Note 3)
Junction−to−Ambient – Steady State (Note 4)
R
R
58.9
108.9
q
q
JA
JA
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
30
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
17
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
= 24 V
T = 25°C
1.0
10
DSS
GS
DS
J
V
mA
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
= 0 V, V
=
20 V
100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.5
1.9
4.5
2.5
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
GS(TH) J
mV/°C
Drain−to−Source On Resistance
R
V
= 10 V
I
= 30 A
= 15 A
= 30 A
= 15 A
8.3
8.2
11
21
DS(on)
GS
D
I
D
mW
V
GS
= 4.5 V
I
D
14.6
13.2
34
I
D
Forward Transconductance
g
FS
V
= 1.5 V, I = 30 A
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
774
306
161
8.2
ISS
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
C
OSS
C
RSS
V
GS
= 0 V, f = 1.0 MHz, V = 15 V
pF
DS
Q
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
1.5
G(TH)
V
= 4.5 V, V = 15 V, I = 30 A
nC
nC
GS
DS
D
Q
3.0
GS
GD
Q
4.0
Q
t
V
GS
= 10 V, V = 15 V, I = 30 A
15.8
G(TOT)
DS
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
10
d(ON)
t
r
27.6
12.5
5.7
V
= 4.5 V, V = 15 V,
DS
GS
D
ns
I
= 15 A, R = 3.0 W
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
http://onsemi.com
2
NTD4970N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Symbol
Test Condition
Min
Typ
Max
Unit
t
6.3
19.5
16.2
3.7
d(ON)
Rise Time
t
r
V
= 10 V, V = 15 V,
DS
GS
D
ns
I
= 15 A, R = 3.0 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.97
0.88
19.6
10.2
9.4
1.1
SD
J
V
S
= 0 V,
GS
V
I
= 30 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
nC
nH
a
V
= 0 V, dIS/dt = 100 A/ms,
GS
I
S
= 30 A
Discharge Time
t
b
Reverse Recovery Charge
PACKAGE PARASITIC VALUES
Source Inductance (Note 7)
Drain Inductance, DPAK
Drain Inductance, IPAK (Note 7)
Gate Inductance (Note 7)
Gate Resistance
Q
7.0
RR
L
L
L
2.85
0.0164
1.88
4.9
S
D
D
G
T = 25°C
A
L
R
0.8
2.2
W
G
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
ORDERING INFORMATION
†
Device
Package
Shipping
NTD4970NT4G
NTD4970N−1G
NTD4970N−35G
DPAK
2500 / Tape & Reel
75 Units / Rail
(Pb−Free)
IPAK
(Pb−Free)
IPAK Trimmed Lead
75 Units / Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
3
NTD4970N
TYPICAL PERFORMANCE CURVES
50
50
40
30
20
10
10 V thru 4.5 V
V
GS
= 3.9 V
3.6 V
V
DS
= 10 V
40
30
20
10
T = 25°C
J
3.3 V
T = 25°C
J
3.0 V
2.7 V
T = 125°C
J
T = −55°C
J
0
0
0
1
2
3
4
5
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
19
18
17
16
15
14
13
12
11
10
9
21
20
19
18
17
16
15
14
13
12
11
10
9
I
= 30 A
T = 25°C
D
J
T = 25°C
J
V
= 4.5 V
GS
V
= 10 V
30
GS
8
8
7
7
3
4
5
6
7
8
9
10
10
15
20
25
35
40
45
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
10000
1000
100
I
V
= 30 A
D
= 10 V
GS
T = 150°C
J
T = 125°C
J
T = 85°C
J
V
= 0 V
GS
10
−50 −25
0
25
50
75 100 125 150 175
5
10
V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
15
20
25
30
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
http://onsemi.com
4
NTD4970N
TYPICAL PERFORMANCE CURVES
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
10
Q
T = 25°C
T
J
9
V
GS
= 0 V
8
7
6
5
4
3
2
C
iss
Q
Q
gd
gs
C
oss
I
= 30 A
D
T = 25°C
V
V
J
= 15 V
= 10 A
DD
GS
1
0
C
rss
0
5
10
15
20
25
30
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and Drain−to−Source
Voltage vs. Total Charge
1000
100
10
30
25
20
15
10
5
V
= 15 V
= 15 A
= 10 V
DD
V
GS
= 0 V
I
D
V
GS
T = 125°C
J
t
f
t
d(off)
t
r
t
d(on)
T = 25°C
J
0
1
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
R , GATE RESISTANCE (W)
G
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
12
11
10
9
1000
100
10
I
D
= 15 A
10 ms
100 ms
1 ms
8
7
6
10 ms
5
1
0 V < V < 10 V
Single Pulse
GS
4
T
C
= 25°C
3
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
2
dc
1
0.01
0
0.01
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
5
NTD4970N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
D
A
E
c2
b3
B
4
2
L3
L4
Z
H
DETAIL A
1
3
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
A
b2
c
b
b
b2 0.030 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2 0.018 0.024
GAUGE
SEATING
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
PLANE
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
L2
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
0.020 BSC
DETAIL A
L3 0.035 0.050
ROTATED 905 CW
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
3.00
0.244
0.118
2.58
0.102
5.80
1.60
0.063
6.17
0.228
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
NTD4970N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
B
R
C
V
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.09
A
B
C
D
E
F
G
H
J
K
R
V
W
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
A
K
SEATING PLANE
W
2.29 BSC
F
0.87
0.46
3.40
4.57
0.89
1.01
0.58
3.60
5.46
1.27
0.25
J
G
H
D 3 PL
0.000 0.010 0.000
0.13 (0.005) W
IPAK
CASE 369D−01
ISSUE C
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
S
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
2. DRAIN
G
M
T
0.13 (0.005)
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NTD4970N/D
相关型号：
NTD50N03R-1G
7.8A, 25V, 0.014ohm, N-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 369D-01, DPAK-3
ROCHESTER
©2020 ICPDF网 联系我们和版权申明