NTD5C668NLT4G [ONSEMI]
单 N 沟道，逻辑电平，功率 MOSFET，60V，48A，9.3mΩ;
| 型号： | NTD5C668NLT4G |
| 厂家： | 
ONSEMI |
| 描述： | 单 N 沟道，逻辑电平，功率 MOSFET，60V，48A，9.3mΩ |
| 文件： | 总7页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD5C668NL
Power MOSFET
60 V, 8.9 mW, 48 A, Single N−Channel
Features
• Low R
to Minimize Conduction Losses
• Low Q and Capacitance to Minimize Driver Losses
DS(on)
G
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• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
I
D
(BR)DSS
DS(on)
8.9 mW @ 10 V
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
60 V
49 A
12.8 mW @ 4.5 V
Parameter
Drain−to−Source Voltage
Symbol
Value
60
Unit
V
V
DSS
D
Gate−to−Source Voltage
Continuous Drain Cur-
V
GS
"20
48
V
T
= 25°C
= 100°C
= 25°C
I
D
A
C
rent R
(Notes 1 & 3)
q
JC
T
C
34
Steady
State
G
Power Dissipation R
(Note 1)
T
C
P
D
42
W
A
q
JC
T
C
= 100°C
21
S
Continuous Drain Cur-
T = 25°C
A
I
D
15
rent R
3)
(Notes 1, 2 &
N−CHANNEL MOSFET
q
JA
T = 100°C
A
10
Steady
State
Power Dissipation R
(Notes 1 & 2)
T = 25°C
A
P
D
4.0
2.0
250
W
4
q
JA
T = 100°C
A
2
1
Pulsed Drain Current
T = 25°C, t = 10 ms
A
I
DM
A
p
3
Operating Junction and Storage Temperature
T , T
−55 to
175
°C
J
stg
DPAK
CASE 369C
STYLE 2
Source Current (Body Diode)
I
25
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
104
mJ
Energy (I
= 3 A)
L(pk)
MARKING DIAGRAM
& PIN ASSIGNMENT
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
4
Drain
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case (Drain) (Note 1)
R
3.6
37
°C/W
q
q
JC
2
Junction−to−Ambient − Steady State (Note 2)
R
Drain
JA
1
3
Gate Source
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
A
Y
WW
= Assembly Location
= Year
= Work Week
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
5C668L = Device Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2018 − Rev. 1
NTD5C668NL/D
NTD5C668NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
27
mV/°C
(BR)DSS
Zero Gate Voltage Drain Current
I
mA
T = 25°C
10
DSS
J
V
V
= 0 V,
= 60 V
GS
DS
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
V
V
= V , I = 50 mA
1.2
2.1
V
GS(TH)
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
4.8
7.4
10.2
60
mV/°C
mW
GS(TH)
J
R
V
= 10 V, I = 25 A
8.9
DS(on)
GS
D
V
GS
= 4.5 V, I = 25 A
12.8
D
Forward Transconductance
g
FS
V
= 15 V, I = 25 A
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCES
pF
Input Capacitance
C
1300
580
18
iss
V
= 0 V, f = 1.0 MHz,
GS
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
C
oss
V
DS
= 25 V
C
rss
Q
nC
nC
V
= 4.5 V
= 10 V
8.7
G(TOT)
GS
V
= 30 V,
= 25 A
DS
I
D
V
18.7
2.4
GS
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
Q
4.1
GS
GD
GP
V
GS
= 4.5 V, V = 30 V,
DS
I
D
= 25 A
Q
V
2.0
3.1
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
ns
t
12
74
26
62
d(on)
Rise Time
t
r
V
= 4.5 V, V = 30 V,
GS
DS
I
D
= 25 A, R = 2.5 W
G
Turn−Off Delay Time
t
d(off)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
T = 25°C
0.87
0.76
32
1.2
SD
J
V
= 0 V,
= 20 A
GS
I
S
T = 125°C
J
ns
Reverse Recovery Time
Charge Time
t
RR
ta
15
V
= 0 V, dI /dt = 100 A/ms,
S
GS
I
S
= 25 A
Discharge Time
tb
16
Reverse Recovery Charge
Q
20
nC
RR
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NTD5C668NL
TYPICAL CHARACTERISTICS
100
80
100
V
GS
= 10 V to 5 V
V
DS
= 10 V
80
60
40
3.6 V
3.4 V
60
3.2 V
3.0 V
40
T = 25°C
J
20
0
20
0
2.8 V
2.6 V
T = 125°C
T = −55°C
J
J
0
0.5
1.0
1.5
2.0
2.5
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
35
30
25
20
15
10
14
12
T = 25°C
D
J
I
= 25 A
V
= 4.5 V
= 10 V
GS
10
8
V
GS
6
4
5
0
2
0
T = 25°C
J
3
4
5
6
7
8
9
10
10
20
30
40
50
60
70
80
90 100
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
1.8
1.6
1.4
1.2
1.0
100K
10K
1K
V
= 10 V
= 25 A
GS
I
D
T = 150°C
J
T = 125°C
J
T = 85°C
J
100
10
0.8
0.6
−50 −25
0
25
50
75 100 125 150 175
5
15
V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
25
35
45
55
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTD5C668NL
TYPICAL CHARACTERISTICS
10K
1K
10
V
= 30 V
= 25 A
DS
9
8
7
6
5
4
3
I
D
C
ISS
T = 25°C
J
C
OSS
100
Q
Q
GD
GS
C
RSS
10
1
V
= 0 V
GS
2
1
0
T = 25°C
J
f = 1 MHz
0
10
20
30
40
50
60
0
2
4
6
8
10 12 14
16 18 20
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
1000
100
10
100
10
V
GS
= 0 V
V
V
= 4.5 V
= 30 V
= 25 A
GS
DS
I
D
t
r
t
f
1
t
t
d(off)
T = 125°C
T = 25°C T = −55°C
J J
J
d(on)
0.1
1
10
R , GATE RESISTANCE (W)
100
0.3
0.4
0.5
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.6
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
1
T
= 25°C
J(initial)
T
= 100°C
J(initial)
V
≤ 10 V
GS
10 ms
0.5 ms
1 ms
Single Pulse
= 25°C
T
C
1
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
100
0.1
0.1
0.00001
0.1
1
10
1000
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NTD5C668NL
TYPICAL CHARACTERISTICS
10
1
Duty Cycle = 50%
20%
10%
5%
2%
0.1
1%
Single Pulse
0.01
0.001
1E−06
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NTD5C668NLT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE G
2
1
DATE 31 MAY 2023
3
SCALE 1:1
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX = Device Code
A
= Assembly Location
L
= Wafer Lot
STYLE 1:
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
Y
WW
G
= Year
= Work Week
= Pb−Free Package
PIN 1. BASE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. CATHODE
2. ANODE
3. GATE
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
2. COLLECTOR
3. EMITTER
3. SOURCE
4. DRAIN
4. COLLECTOR
4. CATHODE
4. ANODE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
PIN 1. GATE
STYLE 8:
PIN 1. N/C
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
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