NTGS4111PT2G [ONSEMI]
单 P 沟道，功率 MOSFET，-30V，-4.7A，60mΩ;
| 型号： | NTGS4111PT2G |
| 厂家： | 
ONSEMI |
| 描述： | 单 P 沟道，功率 MOSFET，-30V，-4.7A，60mΩ 开关 光电二极管 小信号场效应晶体管 |
| 文件： | 总5页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTGS4111P
Power MOSFET
−30 V, −4.7 A, Single P−Channel, TSOP−6
Features
• Leading −30 V Trench Process for Low R
DS(on)
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• Low Profile Package Suitable for Portable Applications
• Surface Mount TSOP−6 Package Saves Board Space
• Improved Efficiency for Battery Applications
• Pb−Free Package is Available
I
MAX
V
R
TYP
D
(BR)DSS
DS(on)
38 mW @ −10 V
68 mW @ −4.5 V
−30 V
−4.7 A
Applications
• Battery Management and Switching
• Load Switching
• Battery Protection
P−Channel
1 2 5 6
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol Value
Unit
V
3
V
−30
20
DSS
V
V
GS
Continuous Drain
Current (Note 1)
Steady
State
I
A
T = 25°C
−3.7
−2.7
−4.7
1.25
D
A
4
T = 85°C
A
MARKING DIAGRAM &
PIN ASSIGNMENT
t ≤ 5 s T = 25°C
A
Power Dissipation
(Note 1)
T = 25°C
A
P
W
Steady
State
D
Drain Drain Source
6
5
4
t ≤ 5 s
2.0
1
Continuous Drain
Current (Note 2)
Steady
State
I
A
T = 25°C
−2.6
−1.9
0.63
D
A
TG M G
G
T = 85°C
A
TSOP−6
CASE 318G
STYLE 1
Power Dissipation
(Note 2)
T = 25°C
A
P
W
D
1
2
3
Drain Drain Gate
Pulsed Drain Current
tp = 10 ms
I
−15
A
DM
Operating Junction and Storage Temperature
T ,
−55 to
150
°C
J
TG
M
= Specific Device Code
= Date Code*
T
STG
G
= Pb−Free Package
Source Current (Body Diode)
I
−1.7
260
A
S
(Note: Microdot may be in either location)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
°C
L
*Date Code orientation may vary depending
upon manufacturing location.
THERMAL RESISTANCE RATINGS
Rating
Symbol
Max
100
62.5
200
Unit
ORDERING INFORMATION
°C/W
Junction−to−Ambient – Steady State (Note 1)
Junction−to−Ambient – t ≤ 5 s (Note 1)
Junction−to−Ambient – Steady State (Note 2)
R
q
q
q
JA
JA
JA
†
R
R
Device
Package
Shipping
NTGS4111PT1
TSOP−6 3000 / Tape & Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.006 in sq).
NTGS4111PT1G TSOP−6 3000 / Tape& Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 2
NTGS4111P/D
NTGS4111P
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
= 0 V, I = −250 mA
−30
V
(BR)DSS
GS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
(BR)DSS
−17
mV/°C
J
Zero Gate Voltage Drain Current
I
mA
T = 25°C
−1.0
−100
100
DSS
J
V
= 0 V,
= −24 V
GS
V
DS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V =
GS
20 V
nA
GSS
DS
V
V
V
= V , I = −250 mA
−1.0
−3.0
V
GS(TH)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
5.0
38
mV/°C
mW
GS(TH)
J
R
DS(on)
= −10 V, I = −3.7 A
60
GS
GS
D
V
= −4.5 V, I = −2.7 A
68
110
D
Forward Transconductance
g
FS
V
= −10 V, I = −3.7 A
6.0
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCE
pF
Input Capacitance
C
750
140
130
15.25
0.8
ISS
V
= 0 V, f = 1.0 MHz,
GS
Output Capacitance
C
OSS
C
RSS
V
= −15 V
DS
Reverse Transfer Capacitance
Total Gate Charge
nC
ns
ns
Q
32
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
G(TH)
V
V
= −10 V, V = −15 V,
DD
GS
I
= −3.7 A
D
Q
2.6
GS
GD
Q
3.4
SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4)
Turn−On Delay Time
Rise Time
t
9.0
9.0
38
17
18
85
45
d(ON)
t
r
= −10 V, V = −15 V,
GS
DD
I
= −1.0 A, R = 6.0 W
D
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
22
f
SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4)
Turn−On Delay Time
Rise Time
t
11
15
28
22
20
28
56
50
d(ON)
t
r
V
= −4.5 V, V = −15 V,
DD
GS
I
= −1.0 A, R = 6.0 W
D
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN − SOURCE DIODE CHARACTERISTICS
Characteristic
Symbol
Test Condition
Min
Typ
−0.76
−0.60
24
Max
Unit
Forward Diode Voltage
V
V
T = 25°C
J
−1.2
DS
V
S
= 0 V,
GS
I = −1.0 A
T = 125°C
J
ns
Reverse Recovery Time
Charge Time
t
60
RR
t
t
9.0
a
V
= 0 V
GS
dI /dt = 100 A/ms, I = −1.0 A
S
S
Discharge Time
15
b
Reverse Recovery Charge
Q
12
nC
RR
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTGS4111P
TYPICAL PERFORMANCE CURVES (T = 25°C unless otherwise noted)
J
12
11
10
9
12
−4.5 V −4.2 V
−10V
V
≥ −10 V
−4 V
DS
11
10
9
−8 V
−6 V
−3.8 V
8
8
−5.5 V
7
7
−5 V
−3.6 V
−3.4 V
6
6
5
5
100°C
4
4
3
3
−3.2 V
−3 V
25°C
2
2
1
0
1
0
T = 25°C
J
T = −55°C
J
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
1
1.5
2
2.5
3
3.5
4
4.5
5
−V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.1
T = 25°C
J
T = 25°C
D
J
I
= −3.7 A
0.2
0.1
0
V
= −4.5 V
= −10 V
GS
0.05
V
GS
0
2.0
2
3
4
5
6
7
8
9
10
3.0
4.0
−V
GS,
GATE VOLTAGE (VOLTS)
−I DRAIN CURRENT (AMPS)
D,
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
100000
10000
I
V
= −3.7 A
V
= 0 V
GS
D
= −10 V
GS
T = 150°C
J
1.0
0.5
1000
100
T = 100°C
J
−50 −25
0
25
50
75
100
125
150
5
10
15
20
25
30
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTGS4111P
TYPICAL PERFORMANCE CURVES (T = 25°C unless otherwise noted)
J
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
12
20
C
C
iss
T = 25°C
J
QT
10
rss
V
V
GS
DS
8
6
4
C
iss
10
Q
1
Q
4
GS
GD
C
oss
2
0
I
= −3.7 A
D
T = 25°C
V
= 0 V
V
= 0 V
5
C
rss
J
DS
GS
0
9 10 11 12 13 14 15 16
10
5
0
10
15
20
25
30
0
2
3
5
6
7 8
−V
GS
−V
DS
Q , TOTAL GATE CHARGE (nC)
g
−GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
Figure 7. Capacitance Variation
100
10
V
= 0 V
GS
10
T = 150°C
J
100 ms
1 ms
1
1
T = 100°C
J
V
= −20 V
GS
10 ms
SINGLE PULSE
= 25°C
T
C
T = 25°C
J
0.1
R
LIMIT
DS(on)
dc
THERMAL LIMIT
PACKAGE LIMIT
T = −55°C
J
0.01
0.1
0.3
0.1
1
10
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0 1.1
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
−V , SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
Figure 10. Diode Forward Voltage vs. Current
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.01
0.001
0.0001
Single Pulse
1E−07
1E−06
1E−05
1E−04
1E−03
1E−02
t, TIME (s)
1E−01
1E+00
1E+01
1E+02
1E+03
Figure 11. FET Thermal Response
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4
NTGS4111P
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE P
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
6
5
2
4
E
H
E
1
3
b
MILLIMETERS
INCHES
DIM
A
A1
b
c
D
E
e
L
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
NOM
1.00
0.06
0.38
0.18
3.00
1.50
0.95
0.40
2.75
−
MAX
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
NOM
0.039
0.002
0.014
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
e
1.10
0.10
0.50
0.26
3.10
1.70
1.05
0.60
3.00
10°
q
c
A
0.05 (0.002)
L
A1
H
E
q
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.075
0.95
0.037
0.7
0.028
1.0
mm
inches
0.039
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTGS4111P/D
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