NTHC5513T1G [ONSEMI]
Power MOSFET 20 V, +3.9 A / −3.0 A, Complementary ChipFET-TM; 功率MOSFET的20 V ， 3.9 A / -3.0 A，互补ChipFET -TM
| 型号： | NTHC5513T1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 20 V, +3.9 A / −3.0 A, Complementary ChipFET-TM |
| 文件： | 总10页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTHC5513
Power MOSFET
20 V, +3.9 A / −3.0 A,
Complementary ChipFETt
Features
• Complementary N−Channel and P−Channel MOSFET
• Small Size, 40% Smaller than TSOP−6 Package
• Leadless SMD Package Featuring Complementary Pair
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V
R
TYP
I MAX
D
(BR)DSS
DS(on)
• ChipFET Package Provides Great Thermal Characteristics Similar to
60 mW @ 4.5 V
80 mW @ 2.5 V
N−Channel
20 V
Larger Packages
3.9 A
• Low R
in a ChipFET Package for High Efficiency Performance
DS(on)
130 mW @ −4.5 V
200 mW @ −2.5 V
P−Channel
−20 V
• Low Profile (< 1.10 mm) Allows Placement in Extremely Thin
Environments Such as Portable Electronics
• Pb−Free Package is Available
−3.0 A
S
D
2
1
Applications
• Load Switch Applications Requiring Level Shift
• DC−DC Conversion Circuits
• Drive Small Brushless DC Motors
G
2
G
1
• Designed for Power Management Applications in Portable, Battery
Powered Products
D
2
S
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
N−Channel MOSFET
P−Channel MOSFET
Parameter
Drain−to−Source Voltage
Symbol Value
Unit
V
V
20
±12
2.9
DSS
ChipFET
CASE 1206A
STYLE 2
Gate−to−Source Voltage
V
V
GS
Continuous Drain
Current (Note 1)
N−Ch
Steady
State
T = 25°C
I
D
A
A
T = 85°C
A
2.1
PIN
MARKING
DIAGRAM
t v 5
P−Ch
Steady
State
T = 25°C
A
3.9
CONNECTIONS
T = 25°C
A
I
−2.2
−1.6
−3.0
12
A
D
8
7
6
5
1
2
3
4
D
D
D
D
S
1
2
3
4
8
7
6
5
1
1
2
2
1
T = 85°C
A
G
S
1
t v 5
N−Ch
P−Ch
T = 25°C
A
Pulsed Drain Current
(Note 1)
t = 10 ms
t = 10 ms
I
A
DM
2
−9.0
1.1
G
2
Power Dissipation
(Note 1)
Steady
State
P
D
W
T = 25°C
A
C1 = Specific Device Code
M = Month Code
t v 5
T = 25°C
2.1
A
Operating Junction and Storage
Temperature
T ,
−55 to
150
°C
°C
J
T
STG
ORDERING INFORMATION
Lead Temperature for Soldering Purposes
(1/8” from case for 10 seconds)
T
L
260
†
Device
Package
Shipping
NTHC5513T1
ChipFET
3000/Tape & Reel
3000/Tape & Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
ChipFET
(Pb−Free)
NTHC5513T1G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 4
NTHC5513/D
NTHC5513
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
110
60
Unit
Junction−to−Ambient (Note 1)
Steady State
R
°C/W
q
JA
T = 25°C
A
t v 5
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
V
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage
V
N
P
N
P
N
P
I
= 250 mA
20
(BR)DSS
D
V
= 0 V
GS
I
D
= −250 mA
−20
Zero Gate Voltage Drain Current
I
V
= 0 V, V = 16 V
1.0
−1.0
5
mA
DSS
GS
DS
V
= 0 V, V = −16 V
DS
GS
V
= 0 V, V = 16 V, T = 85 °C
DS J
GS
V
= 0 V, V = −16 V, T = 85 °C
−5
GS
DS
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V = ±12 V
±100
nA
V
GSS
DS
GS
V
R
N
P
N
P
N
P
N
P
I
= 250 mA
0.6
1.2
GS(TH)
D
V
GS
= V
DS
I
D
= −250 mA
−0.6
−1.2
Drain−to−Source On Resistance
(on)
V
= 4.5 V , I = 2.9 A
0.058 0.080
0.130 0.155
0.077 0.115
0.200 0.240
6.0
DS
GS
D
V
GS
= −4.5 V , I = −2.2 A
D
W
V
= 2.5 V , I = 2.3 A
D
GS
V
GS
= −2.5 V, I = −1.7 A
D
Forward Transconductance
g
V
= 10 V, I = 2.9A
S
FS
DS
D
V
DS
= −10 V , I = −2.2 A
6.0
D
CHARGES AND CAPACITANCES
Input Capacitance
C
N
P
N
P
N
P
N
P
N
P
N
P
V
= 10 V
= −10 V
= 10 V
180
185
80
pF
ISS
DS
V
V
V
DS
Output Capacitance
C
V
OSS
DS
DS
f = 1 MHz, V = 0 V
GS
= −10 V
= 10 V
95
Reverse Transfer Capacitance
Total Gate Charge
C
V
25
RSS
DS
DS
= −10 V
30
Q
V
GS
= 4.5 V, V = 10 V, I = 2.9 A
2.6
3.0
0.6
0.5
0.7
0.9
4.0
6.0
nC
G(TOT)
DS
D
V
V
V
= −4.5 V, V = −10 V, I = −2.2 A
DS D
GS
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
Q
Q
V
= 4.5 V, V = 10 V, I = 2.9 A
GS DS D
GS
= −4.5 V, V = −10 V, I = −2.2 A
GS
DS
D
V
GS
= 4.5 V, V = 10 V, I = 2.9 A
DS D
GD
= −4.5 V, V = −10 V, I = −2.2 A
GS
DS
D
3. Pulse Test: Pulse Width v 250 ms, Duty Cycle v 2%.
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2
NTHC5513
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
t
5.0
9.0
10
10
18
20
6.0
12
25
50
40
ns
d(ON)
t
r
N
V
= 16 V, V = 4.5 V, I = 2.9 A,
GS D
DD
R
= 2.5 W
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
3.0
7.0
13
Turn−On Delay Time
Rise Time
t
d(ON)
t
r
V
= −16 V, V = −4.5 V, I = −2.2 A,
GS D
DD
P
R
= 2.5 W
G
Turn−Off Delay Time
Fall Time
t
33
d(OFF)
t
f
27
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 5)
Reverse Recovery Time (Note 4)
Charge Time
V
N
P
N
P
N
P
N
P
N
P
I
= 2.6 A
0.8
1.15
V
SD
RR
S
V
= 0 V
GS
I
I
I
I
I
= −2.1 A
= 1.5 A
= −1.5 A
= 1.5 A
= −1.5 A
= 1.5 A
= −1.5 A
= 1.5 A
= −1.5 A
−0.8 −1.15
S
t
I
S
12.5
32
ns
S
t
t
I
S
9.0
10
a
S
V
GS
= 0 V,
dI / dt = 100 A/ms
S
Discharge Time
I
S
3.5
22
b
S
Reverse Recovery Charge
Q
I
S
6.0
15
nC
RR
S
4. Switching characteristics are independent of operating junction temperatures.
5. Pulse Test: Pulse Width v 250 ms, Duty Cycle v 2%.
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3
NTHC5513
TYPICAL N−CHANNEL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
8
6
4
8
V
= 5 V to 3 V
= 2.4 V
GS
T = 25°C
J
V
DS
≥ 10 V
V
GS
2 V
2.2 V
6
1.8 V
4
2
0
1.6 V
1.4 V
2
0
T
C
= −55°C
25°C
100°C
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.15
0.1
I
= 2.7 A
T = 25°C
J
D
T = 25°C
J
V
= 2.5 V
= 4.5 V
GS
0.07
0.04
V
GS
0.05
0
1
3
5
7
0
1
2
3
4
5
6
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I
D,
DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.7
100
10
1
I
V
= 2.7 A
V
GS
= 0 V
D
= 4.5 V
GS
1.5
1.3
1.1
T = 100°C
J
0.9
0.7
−50 −25
0
25
50
75
100
125 150
2
4
6
8
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
12
14
16
18
20
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
NTHC5513
TYPICAL N−CHANNEL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
5
20
16
12
8
400
300
200
V
DS
= 0 V
V
GS
= 0 V
Q
G
T = 25°C
J
C
C
4.5
4
ISS
3.5
3
RSS
2.5
2
Q
GD
Q
GS
1.5
1
100
0
4
C
I
= 2.7 A
OSS
D
T = 25°C
0.5
0
J
0
0
0.5
1
1.5
2
2.5
3
10
5
0
5
10
15
20
V
GS
V
DS
Q , TOTAL GATE CHARGE (nC)
G
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
7
6
5
4
3
2
V = 0 V
GS
T = 25°C
J
V
= 16 V
= 2.7 A
= 4.5 V
DD
I
D
V
GS
t
r
10
t
d(OFF
)
t
d(ON)
t
f
1
0
1
1
10
R , GATE RESISTANCE (OHMS)
100
0.3
0.6
0.75
0.9
1.05
1.2
0.45
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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NTHC5513
TYPICAL P−CHANNEL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
4
3
2
4
T = 25°C
J
V
= −6 V to −3 V
= −2.4 V
GS
V
DS
≥ −10 V
−2 V
V
GS
−2.2 V
3
−1.8 V
−1.6 V
2
1
0
T
= −55°C
C
1
0
−1.4 V
−1.2 V
25°C
100°C
0
1
2
3
4
5
6
7
8
0.5
1
1.5
2
2.5
3
−V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. On−Region Characteristics
Figure 12. Transfer Characteristics
0.25
0.225
0.2
0.5
T = 25°C
J
I
= −2.1 A
D
T = 25°C
J
0.4
0.3
0.2
V
GS
= −2.5 V
0.175
0.15
0.125
0.1
V
GS
= −4.5 V
0.1
0
1
2
3
4
5
6
0.5
1.5
2.5
3.5
−V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
−I DRAIN CURRENT (AMPS)
D,
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
1.6
1.4
1.2
1
10000
I
V
= −2.1 A
V
GS
= 0 V
D
= −4.5 V
GS
T = 150°C
J
1000
100
10
T = 100°C
J
0.8
0.6
−50 −25
0
25
50
75
100
125 150
2
4
6
8
10
12
14
16
18
20
−T , JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 15. On−Resistance Variation with
Temperature
Figure 16. Drain−to−Source Leakage Current
vs. Voltage
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NTHC5513
TYPICAL P−CHANNEL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
5
15
12
9
600
500
400
300
200
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
Q
T
C
C
−V
ISS
−V
GS
DS
4
3
RSS
Q
GS
Q
GD
2
1
0
6
3
I
= −2.1 A
T = 25°C
C
D
100
0
OSS
J
0
10
5
0
5
10
15
20
0
1
2
3
4
−V
GS
−V
DS
Q , TOTAL GATE CHARGE (nC)
G
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 17. Capacitance Variation
1000
2.5
2
V
GS
= 0 V
T = 25°C
J
100
1.5
1
t
d(OFF)
t
f
t
10
r
t
d(ON)
V
= −16 V
= −2.1 A
= −4.5 V
DD
0.5
0
I
D
V
GS
1
1
10
R , GATE RESISTANCE (OHMS)
100
0.3
0.5
0.7
0.9
−V , SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
G
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
Figure 20. Diode Forward Voltage vs. Current
TYPICAL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
2
1
Duty Cycle = 0.5
Notes:
P
DM
0.2
t
1
0.1
t
2
1
2
0.1
t
0.05
0.02
1. Duty Cycle, D =
t
2. Per Unit Base = R
= 90°C/W
thJA
(t)
3. T
T = P
A
Z
q
JM −
DM JA
Single Pulse
4. Surface Mounted
0.01
−4
−3
10
−2
10
−1
10
10
1
10
100
600
Square Wave Pulse Duration (sec)
Figure 21. Thermal Response
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NTHC5513
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
1.092
0.043
0.635
0.025
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.254
0.010
0.66
0.66
0.026
0.026
Figure 23. Style 2
Figure 22. Basic
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 22. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 23 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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NTHC5513
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
A
M
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
K
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
S
B
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
L
D
J
MILLIMETERS
INCHES
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
G
DIM MIN
MAX
3.10
1.70
1.10
0.35
MIN
MAX
0.122
0.067
0.043
0.014
A
B
C
D
G
J
2.95
1.55
1.00
0.25
0.116
0.061
0.039
0.010
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
0.65 BSC
0.025 BSC
0.10
0.28
0.20
0.42
0.004 0.008
0.011 0.017
0.022 BSC
C
K
L
0.55 BSC
5 ° NOM
1.80 2.00
M
S
5 ° NOM
0.05 (0.002)
0.072
0.080
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NTHC5513
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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local Sales Representative.
NTHC5513/D
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HCMOS Output Clock Oscillator, 6MHz Min, 24MHz Max, FULL SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
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