NTHD5904N [ONSEMI]
Power MOSFET 20 V, 4.5 A, Dual N−Channel, ChipFET; 功率MOSFET的20 V ， 4.5 A ，双N沟道， ChipFET
| 型号： | NTHD5904N |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 20 V, 4.5 A, Dual N−Channel, ChipFET |
| 文件： | 总6页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTHD5904N
Power MOSFET
20 V, 4.5 A, Dual N−Channel, ChipFETt
Features
• Low R
and Fast Switching Speed
DS(on)
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• Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.
Ideal Device for Applications Where Board Space is at a Premium.
• ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for
Applications Where Heat Transfer is Required.
V
R
DS(on)
TYP
I MAX
D
(BR)DSS
40 mW @ 4.5 V
55 mW @ 2.5 V
• Pb−Free Packages are Available
20 V
4.5 A
Applications
• DC−DC Buck or Boost Converters
• Low Side Switching
• Optimized for Battery and Low Side Switching Applications in
Computing and Portable Equipment
N−Channel MOSFET
D , D
1
2
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
20
Unit
V
G , G
1
2
V
DSS
Gate−to−Source Voltage
V
8.0
V
GS
S , S
1
2
Continuous Drain
Current (Note 1)
I
A
T =25°C
3.3
D
A
Steady
State
T =85°C
A
2.4
t ≤ 5 s T =25°C
4.5
A
ChipFET
CASE 1206A
STYLE 2
Power Dissipation
(Note 1)
Steady
State
P
1.13
W
A
D
D
T =25°C
A
Continuous Drain
Current (Note 2)
I
T =25°C
A
2.5
1.8
D
T =85°C
A
Steady
State
Power Dissipation
(Note 2)
P
0.64
W
T =25°C
A
PIN
MARKING
DIAGRAM
Pulsed Drain Current
t =10 ms
p
I
10
A
DM
CONNECTIONS
Operating Junction and Storage Temperature
T ,
−55 to
150
°C
J
T
STG
8
7
6
5
1
2
3
4
D
1
D
1
D
2
D
2
S
1
2
3
4
8
7
6
5
1
Source Current (Body Diode)
I
2.6
A
S
G
S
1
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
T
260
°C
L
2
THERMAL RESISTANCE RATINGS
G
2
Parameter
Symbol
Max
110
60
Unit
°C/W
Junction−to−Ambient – Steady State (Note 1)
Junction−to−Ambient – t ≤ 5 s (Note 1)
Junction−to−Ambient – Steady State (Note 2)
R
q
q
q
JA
JA
JA
(Top View)
R
R
195
D3 = Specific Device Code
M
G
= Month Code
= Pb−Free Package
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).
3. ESD Rating Information: Human Body Model (HBM) Class 0.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 2
NTHD5904N/D
NTHD5904N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0 V
GS
20
V
(BR)DSS
I
mA
V
= 0 V, V = 16 V
1.0
10
DSS
GS
DS
V
= 0 V, V = 16 V, T = 125°C
DS J
GS
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = "8.0 V
"100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
0.6
0.75
40
1.2
65
V
GS(TH)
GS
DS
D
Drain−to−Source On−Resistance
R
DS(on)
mW
V
V
= 4.5 V, I = 3.3 A
D
GS
GS
= 2.5 V, I = 2.3 A
55
105
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
V
= 10 V, I = 3.3 A
6.0
S
FS
DS
D
pF
C
465
65
iss
V
= 0 V, f = 1.0 MHz,
GS
Output Capacitance
C
oss
V
= 16 V
DS
Reverse Transfer Capacitance
Total Gate Charge
C
30
rss
nC
nC
Q
Q
4.0
0.4
0.8
2.0
6.0
0.5
0.8
1.7
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
G(TH)
V
V
= 2.5 V, V = 16 V,
DS
GS
GS
I
= 3.3 A
D
Q
GS
Q
GD
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Q
G(TH)
= 4.5 V, V = 10 V,
DS
= 3.3 A
I
D
Q
GS
GD
Q
ns
t
6.0
17
d(on)
Rise Time
t
r
V
= 4.5 V, V = 16 V,
DS
GS
I
= 3.3 A, R = 2.5 W
D
G
Turn−Off Delay Time
t
17
d(off)
Fall Time
t
5.1
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
V
V
= 0 V, I = 2.6 A
0.8
19.5
6.0
13
1.15
V
SD
GS
S
ns
t
RR
t
t
a
V
= 0 V, I = 2.6 A,
S
dI /dt = 100 A/ms
S
GS
Discharge Time
b
Reverse Recovery Charge
Q
7.0
nC
RR
4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
NTHD5904NT1
Package
Shipping
ChipFET
3000 / Tape & Reel
3000 / Tape & Reel
NTHD5904NT1G
ChipFET
(Pb−Free)
NTHD5904NT3
ChipFET
10,000 / Tape & Reel
10,000 / Tape & Reel
NTHD5904NT3G
ChipFET
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTHD5904N
TYPICAL PERFORMANCE CURVES (T = 25°C unless otherwise noted)
J
11
10
11
T = 25°C
5 V
V
= 4 V
GS
J
V
≥ 10 V
DS
10
9
V
= 3 V
GS
1.8 V
9
8
7
6
5
4
2.4 V
2 V
8
7
6
5
1.6 V
4
3
3
2
1
0
125°C
1.4 V
1.2 V
2
1
0
25°C
T = −55°C
J
0
0.5
1
1.5
2
0
0.5
1
1.5
2
2.5
3
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.06
0.05
0.08
0.07
0.06
0.05
0.04
I
= 3.3 A
D
T = 25°C
J
T = 25°C
J
V
= 2.5 V
GS
0.04
0.03
V
= 4.5 V
GS
0.03
0.02
1
2
3
4
5
6
2
3
4
DRAIN CURRENT (AMPS)
5
6
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
I
D,
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
10000
1000
100
I
V
= 3.3 A
V
= 0 V
D
GS
= 2.5 V
GS
T = 150°C
J
1.4
1.2
1.0
T = 100°C
J
0.8
0.6
10
−50 −25
0
25
50
75
100
125 150
5
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
15
20
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTHD5904N
TYPICAL PERFORMANCE CURVES (T = 25°C unless otherwise noted)
J
1200
1000
800
10
8
5
V
= 0 V
V
= 0 V
GS
DS
T = 25°C
J
Q
G
C
iss
4
3
2
V
V
GS
DS
6
600
4
Q
Q
GD
GS
400
2
0
1
0
200
0
C
oss
I
= 3.3 A
D
T = 25°C
C
J
rss
10
5
0
5
10
15
20
0
1
2
3
4
5
6
V
V
DS
GS
Q , TOTAL GATE CHARGE (nC)
G
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
6
5
4
V
= 0 V
GS
V
= 16 V
= 3.3 A
= 4.5 V
DD
GS
T = 25°C
J
I
D
V
t
f
t
d(off)
t
r
10
3
2
t
d(on)
1
0
1
1
10
R , GATE RESISTANCE (OHMS)
100
0.3
0.5
0.6
0.7
0.8
0.9
1.0
0.4
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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4
NTHD5904N
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
NOTES:
D
q
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
L
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
H
E
E
MILLIMETERS
INCHES
NOM
0.041
0.012
0.006
DIM
A
b
c
D
E
e
e1
L
MIN
1.00
0.25
0.10
2.95
1.55
NOM
1.05
MAX
MIN
MAX
0.043
0.014
0.008
0.122
0.067
e1
b
1.10
0.35
0.20
3.10
1.70
0.039
0.010
0.004
0.116
0.061
c
0.30
e
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
0.15
3.05
0.120
0.065
1.65
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
0.65 BSC
0.55 BSC
0.35
1.90
5° NOM
0.025 BSC
0.022 BSC
0.014
0.075
5° NOM
0.28
1.80
0.42
2.00
0.011
0.071
0.017
0.079
A
H
E
q
0.05 (0.002)
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.635
0.025
0.025
1.092
0.043
0.178
0.007
0.457
0.018
0.711
0.028
0.254
0.010
mm
inches
0.66
0.026
ǒ
Ǔ
SCALE 20:1
0.66
0.026
mm
inches
ǒ
Ǔ
SCALE 20:1
Basic
Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
NTHD5904N
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD5904N/D
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