NTHLD040N65S3HF [ONSEMI]
功率 MOSFET，N 沟道，SUPERFET® III，FRFET®，650 V，65 A，40 mΩ，TO-247AD;
| 型号： | NTHLD040N65S3HF |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，N 沟道，SUPERFET® III，FRFET®，650 V，65 A，40 mΩ，TO-247AD |
| 文件： | 总10页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET – Power, N-Channel,
SUPERFET) III, FRFET)
650 V, 65 A, 40 mW
NTHLD040N65S3HF
Description
www.onsemi.com
SUPERFET III MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on-resistance and lower gate
charge performance. This advanced technology is tailored to minimize
conduction loss, provide superior switching performance, and
withstand extreme dv/dt rate.
V
R
MAX
I MAX
D
DSS
DS(ON)
650 V
40 mW @ 10 V
65 A
Consequently, SUPERFET III MOSFET is very suitable for the
various power system for miniaturization and higher efficiency.
SUPERFET III FRFET MOSFET’s optimized reverse recovery
performance of body diode can remove additional component and
improve system reliability.
D
G
Features
• 700 V @ T = 150°C
J
• Typ. R
= 32 mW
DS(on)
S
• Ultra Low Gate Charge (Typ. Q = 159 nC)
g
• Low Effective Output Capacitance (Typ. C
= 1367 pF)
oss(eff.)
• 100% Avalanche Tested
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
G
D
Applications
S
• Telecom / Server Power Supplies
• Industrial Power Supplies
• EV Charger
TO−247AD
CASE 340AL
• UPS / Solar
MARKING DIAGRAM
NTHD040
N65S3HF
AYWWG
A
Y
= Assembly Location
= Year
WW = Work Week
= Pb−Free Package
G
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2021 − Rev. 2
NTHLD040N65S3HF/D
NTHLD040N65S3HF
ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless otherwise noted)
C
Symbol
Parameter
Value
650
Unit
V
V
DSS
V
GSS
Drain to Source Voltage
Gate to Source Voltage
− DC
30
V
− AC (f > 1 Hz)
30
I
D
Drain Current
− Continuous (T = 25°C)
65
A
C
− Continuous (T = 100°C)
45
C
I
Drain Current
− Pulsed (Note 1)
162.5
1009
9
A
mJ
A
DM
E
Single Pulsed Avalanche Energy (Note 2)
Avalanche Current (Note 2)
Repetitive Avalanche Energy (Note 1)
MOSFET dv/dt
AS
AS
I
E
4.46
100
mJ
V/ns
AR
dv/dt
Peak Diode Recovery dv/dt (Note 3)
Power Dissipation
50
P
(T = 25°C)
446
W
W/°C
°C
D
C
− Derate Above 25°C
3.57
−55 to +150
300
T , T
Operating and Storage Temperature Range
J
STG
T
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 seconds
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse−width limited by maximum junction temperature.
2. I = 9 A, R = 25 W, starting T = 25°C.
AS
G
J
3. I ≤ 32.5 A, di/dt ≤ 200 A/ms, V ≤ 400 V, starting T = 25°C.
SD
DD
J
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.28
40
Unit
R
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
_C/W
q
JC
JA
R
q
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Packing Method
Reel Size
Tape Width
N/A
Quantity
NTHLD040N65S3HF
NTHLD040N65S3HF
TO−247
Tube
N/A
30 Units
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2
NTHLD040N65S3HF
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
650
700
V
V
V
V
I
= 0 V, I = 1 mA, T = 25_C
DSS
GS
D
J
= 0 V, I = 1 mA, T = 150_C
GS
D
J
DBV
/DT
Breakdown Voltage Temperature
Coefficient
= 15 mA, Referenced to 25_C
0.63
213
V/_C
DSS
J
D
I
Zero Gate Voltage Drain Current
V
DS
V
DS
V
GS
= 650 V, V = 0 V
10
mA
DSS
GS
= 520 V, T = 125_C
C
I
Gate to Body Leakage Current
=
30 V, V = 0 V
100
nA
GSS
DS
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
GS
V
GS
V
DS
= V , I = 2.1 mA
3.0
5.0
40
V
mW
S
GS(th)
DS(on)
DS
D
R
Static Drain to Source On Resistance
Forward Transconductance
= 10 V, I = 32.5 A
32
48
D
g
FS
= 20 V, I = 32.5 A
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 400 V, V = 0 V, f = 1 MHz
5945
135
1367
245
159
46
pF
pF
pF
pF
nC
nC
nC
W
iss
DS
GS
C
Output Capacitance
oss
C
Effective Output Capacitance
Energy Related Output Capacitance
Total Gate Charge at 10V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Equivalent Series Resistance
V
DS
V
DS
V
DS
= 0 V to 400 V, V = 0 V
GS
oss(eff.)
C
= 0 V to 400 V, V = 0 V
GS
oss(er.)
Q
= 400 V, I = 32.5 A, V = 10 V
D GS
g(tot)
(Note 4)
Q
gs
Q
64
gd
ESR
f = 1 MHz
1.2
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
V
V
= 400 V, I = 32.5 A,
40
32
ns
ns
ns
ns
d(on)
DD
GS
D
= 10 V, R = 2.2 W
g
t
r
(Note 4)
t
102
26
d(off)
t
f
SOURCE-DRAIN DIODE CHARACTERISTICS
I
Maximum Continuous Source to Drain Diode Forward Current
Maximum Pulsed Source to Drain Diode Forward Current
65
162.5
1.3
A
A
V
S
I
SM
V
SD
Source to Drain Diode Forward
Voltage
V
GS
= 0 V, I = 32.5 A
SD
t
Reverse Recovery Time
V
= 400 V, I = 32.5 A,
160
874
ns
rr
DD
F
SD
dI /dt = 100 A/ms
Q
Reverse Recovery Charge
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
NTHLD040N65S3HF
TYPICAL PERFORMANCE CHARACTERISTICS
200
100
300
VGS
=
10.0V
*Notes:
= 20V
8.0V
7.0V
6.5V
6.0V
5.5V
1. VDS
2. 250ms Pulse Test
100
150oC
10
10
25oC
−55oC
*Notes:
1. 250
ms Pulse Test
2. TC = 25oC
1
1
2
3
4
5
6
7
8
0.2
1
10
20
VDS, Drain−Source Voltage[V]
VGS, Gate−Source Voltage[V]
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.05
0.04
0.03
0.02
1000
100
10
*Note: TC = 25oC
*Notes:
1. V
GS= 0V
ms Pulse Test
2. 250
150oC
VGS = 10V
1
25oC
VGS = 20V
0.1
−55oC
0.01
0.001
0.0
0.5
1.0
1.5
2.0
0
50
100
150
200
ID, Drain Current [A]
VSD, Body Diode Forward Voltage [V]
Figure 3. On−Resistance Variation
Figure 4. Body Diode Forward Voltage
vs. Drain Current and Gate Voltage
Variation vs. Source Current and Temperature
10
1000000
100000
*Note: ID = 32.5A
V
DS = 130V
8
6
4
Ciss
10000
1000
100
VDS= 400V
Coss
*Note:
1. f = 1 MHz
2. V = 0 V
Crss
GS
2
0
C
+ C (C
= shorted)
= Cgs
iss
oss
rss
gd ds
= C + C
10
1
C
C
gd
ds
= C
gd
0.1
1
10
100
1000
0
32
64
96
128
160
VDS, Drain−Source Voltage [V]
Qg, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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4
NTHLD040N65S3HF
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
1.2
1.1
1.0
0.9
0.8
2.5
*Notes:
1. V = 10V
*Notes:
1. V = 0V
GS
GS
2. ID= 32.5A
2. ID = 15mA
2.0
1.5
1.0
0.5
0.0
−50
0
50
100
150
−50
0
50
100
150
TJ, Junction Temperature [oC]
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On−Resistance Variation
vs. Temperature
80
60
40
20
0
500
100
30ms
100ms
1ms
10ms
DC
10
1
Operation in This Area
is Limited by R
DS(on)
*Notes:
1. TC = 25oC
2. TJ = 150oC
3. Single Pulse
0.1
0.01
25
50
75
100
125
150
1
10
100
1000
TC, Case Temperature [oC]
VDS, Drain−Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
37
29.6
22.2
14.8
7.4
0
0
130
260
390
520
650
, Drain to Source Voltage [V]
VDS
Figure 11. Eoss vs. Drain to Source Voltage
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5
NTHLD040N65S3HF
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
P
DM
0.1
0.01
0.05
0.02
0.01
t
1
t
2
NOTES:
Z
(t) = r(t) x R
o
qJC
qJC
R
= 0.28 C/W
qJC
Peak T = P
Duty Cycle, D = t / t
x Z (t) + T
SINGLE PULSE
10−4
J
DM
qJC C
1
2
0.001
10−5
10−3
10−2
10−1
100
101
102
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Transient Thermal Response Curve
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6
NTHLD040N65S3HF
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 13. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 14. Resistive Switching Test Circuit & Waveforms
L
2
1
2
EAS
+
@ LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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7
NTHLD040N65S3HF
+
DUT
V
SD
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET and FRFET are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United
States and/or other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247
CASE 340AL
ISSUE D
DATE 17 MAR 2017
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. SLOT REQUIRED, NOTCH MAY BE ROUNDED.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH.
MOLD FLASH SHALL NOT EXCEED 0.13 PER SIDE. THESE
DIMENSIONS ARE MEASURED AT THE OUTERMOST
EXTREME OF THE PLASTIC BODY.
5. LEAD FINISH IS UNCONTROLLED IN THE REGION DEFINED BY
L1.
6. ∅P SHALL HAVE A MAXIMUM DRAFT ANGLE OF 1.5° TO THE
TOP OF THE PART WITH A MAXIMUM DIAMETER OF 3.91.
7. DIMENSION A1 TO BE MEASURED IN THE REGION DEFINED
BY L1.
SCALE 1:1
SEATING
PLANE
M
M
B A
0.635
B
A
NOTE 4
E
NOTE 6
P
A
E2/2
Q
S
E2
NOTE 4
D
NOTE 3
4
MILLIMETERS
DIM MIN
MAX
5.30
2.60
1.33
2.35
3.40
0.68
21.34
16.25
5.49
1
2
3
A
A1
b
4.70
2.20
1.07
1.65
2.60
0.45
20.80
15.50
4.32
2X
F
L1
b2
b4
c
NOTE 5
L
D
E
E2
e
5.45 BSC
2X b2
c
F
2.655
19.80
3.81
---
20.80
4.32
b4
3X b
A1
L
NOTE 7
L1
P
3.55
3.65
M
M
0.25
B A
e
Q
S
5.40
6.20
6.15 BSC
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON16119F
TO−247
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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