NV25256DWHFT3G [ONSEMI]
EEPROM Serial 256-Kb SPI - Automotive Grade 0 (+150°C);
| 型号： | NV25256DWHFT3G |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM Serial 256-Kb SPI - Automotive Grade 0 (+150°C) 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总13页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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EEPROM Serial 128/256 kb
SPI Automotive Grade 0
SOIC−8
DW SUFFIX
CASE 751BD
TSSOP−8
DT SUFFIX
CASE 948AL
NV25128, NV25256
Description
PIN CONFIGURATION
NV25128, NV25256 are EEPROM Serial 128/256 kb SPI
Automotive Grade 0 devices internally organized as 16K/32Kx8 bits.
It features a 64−byte page write buffer and supports the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
NV25xxx device. The device features software and hardware write
protection, including partial as well as full array protection. Byte
Level On−Chip ECC (Error Correction Code) makes the device
suitable for high reliability applications. The device offers an
additional Identification Page which can be permanently write
protected.
1
CS
SO
WP
V
CC
HOLD
SCK
SI
V
SS
SOIC (DW), TSSOP (DT)
V
CC
SI
CS
NV25xxx
SO
WP
Features
HOLD
SCK
• Automotive AEC−Q100 Grade 0 (−40°C to +150°C) Qualified
• 2.5 V to 5.5 V Supply Voltage Range
• 10 MHz SPI Compatible
V
SS
• SPI Modes (0,0) & (1,1)
Figure 1. Functional Symbol
• 64−byte Page Write Buffer
• Self−timed Write Cycle
PIN FUNCTION
• Hardware and Software Protection
• Additional Identification Page with Permanent Write Protection
Pin Name
Function
Chip Select
CS
SO
WP
• NV Prefix for Automotive and Other Applications Requiring Site and
Serial Data Output
Write Protect
Change Control
• Block Write Protection
1
1
− Protect / , / or Entire EEPROM Array
V
SS
Ground
4
2
• Low Power CMOS Technology
SI
Serial Data Input
Serial Clock
• Program/Erase Cycles:
− 4,000,000 at 25°C
− 1,200,000 at +85°C
− 600,000 at +125°C
− 300,000 at +150°C
SCK
HOLD
Hold Transmission Input
Power Supply
V
CC
• 200 Year Data Retention
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
• SOIC, TSSOP 8−lead Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
March, 2022 − Rev. 0
NV25128/D
NV25128, NV25256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Operating Temperature
−45 to +150
−65 to +150
−0.5 to +6.5
Storage Temperature
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Endurance
Test Condition
Max
4,000,000
1,200,000
600,000
300,000
200
Units
NEND
T
≤ 25°C
Write Cycles
(Note 3)
A
T = 85°C
A
T = 125°C
A
T = 150°C
A
TDR
Data Retention
T = 25°C
A
Year
2. Determined through qualification/characterization.
3. A Write Cycle refers to writing a Byte, a Page, the Status Register or the Identification Page.
Table 3. DC OPERATING CHARACTERISTICS
(V = 2.5 V to 5.5 V, T = −40°C to +150°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
I
Supply Current
(Read Mode)
Read, SO open
Write, CS = V
f
= 10 MHz
3
mA
CCR
SCK
I
Supply Current
(Write Mode)
2
mA
CCW
CC
I
Standby Current
V
= GND or V
,
T = −40°C to +125°C
3
7
mA
mA
mA
mA
mA
mA
V
SB1
IN
CC
A
CS = V , WP = V
,
CC
CC
T = −40°C to +150°C
A
HOLD = V , V = 5.5 V
CC
CC
I
Standby Current
V
IN
= GND or V
,
T = −40°C to +125°C
A
5
SB2
CC
CS = V , WP = GND,
CC
T = −40°C to +150°C
A
10
2
HOLD = GND, V = 5.5 V
CC
I
L
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
IN
= GND or V
−2
−2
CC
I
CS = V , V
= GND or V
CC
2
LO
CC
OUT
V
−0.5
0.3 V
IL1
IH1
CC
V
Input High Voltage
0.7 V
V
CC
+ 0.5
V
CC
V
Output Low Voltage
Output High Voltage
I
= 3.0 mA
0.4
V
OL1
OH1
OL
V
I
= −1.6 mA
V
CC
−0.8 V
V
OH
V
PORth
Internal Power−On
Reset Threshold
0.6
1.5
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NV25128, NV25256
Table 4. PIN CAPACITANCE (T = 25°C, f = 1.0 MHz, V = +5.0 V) (Note 2)
A
CC
Symbol
Test
Conditions
= 0 V
Min
Typ
Max
8
Unit
pF
C
Output Capacitance (SO)
V
OUT
OUT
C
Input Capacitance (CS, SCK, SI, WP, HOLD)
V
IN
= 0 V
8
pF
IN
Table 5. AC CHARACTERISTICS (Note 4)
V
. 2.5 V
CC
−405C to +1505C
Min
Max
Symbol
Parameter
Unit
MHz
ns
f
Clock Frequency
Data Setup Time
Data Hold Time
DC
10
10
40
40
10
SCK
t
SU
t
H
ns
t
SCK High Time
ns
WH
t
SCK Low Time
ns
WL
t
HOLD to Output Low Z
Input Rise Time
25
2
ns
LZ
t
RI
(Note 5)
(Note 5)
ms
t
FI
Input Fall Time
2
ms
t
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
ns
HD
CD
10
ns
t
V
40
ns
t
0
ns
HO
t
20
25
ns
DIS
t
ns
HZ
t
40
30
30
30
30
ns
CS
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
Write Cycle Time
t
t
(Note 6)
4
ms
WC
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V at V > 2.5 V, 0.2 V to 0.8 V at V < 2.5 V
CC
CC
CC
CC
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Table 6. POWER−UP TIMING (Notes 5, 7)
Symbol
Parameter
Max
0.35
0.35
Unit
t
Power−up to Read Operation
Power−up to Write Operation
ms
ms
PUR
t
PUW
7. t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
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3
NV25128, NV25256
Pin Description
Functional Description
The NV25xxx device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the NV25xxx is accomplished by
simply providing the READ command and an address.
Writing to the NV25xxx, in addition to a WRITE command,
address and data, also requires enabling the device for
writing by first setting certain bits in a Status Register, as will
be explained later.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and NV25xxx.
CS: The chip select input pin is used to enable/disable the
NV25xxx. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and NV25xxx must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
After a high to low transition on the CS input pin, the
NV25xxx will accept any one of the six instruction op−codes
listed in Table 7 and will ignore all other possible 8−bit
combinations. The communication protocol follows the
timing from Figure 2.
The NV25xxx features an additional Identification Page
(64 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
Op−code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
HOLD: The HOLD input pin is used to pause transmission
between host and NV25xxx, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
pausing, the HOLD input should be tied to V , either
WRSR
READ
CC
directly or through a resistor.
WRITE
t
CS
CS
t
t
t
WL
CSS
WH
t
t
t
CNS
CNH
CSH
SCK
SI
t
H
t
RI
t
FI
t
SU
VALID
IN
t
V
t
V
t
DIS
t
HO
HI−Z
HI−Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
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4
NV25128, NV25256
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations. The LIP
(Lock Identification Page) bit is set by the user with the
WRSR command and is non−volatile. When set to 1, the
Identification Page is permanently write protected (locked
in Read−only mode).
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
Note: The IPL and LIP bits cannot be set to 1 using the same
WRSR instruction. If the user attempts to set (“1”) both the
IPL and LIP bit in the same time, these bits cannot be written
and therefore they will remain unchanged.
Table 8. STATUS REGISTER
7
6
5
0
4
3
2
1
0
WPEN
IPL
LIP
BP1
BP0
WEL
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
BP0
0
Array Address Protected
Protection
None
No Protection
0
1
NV25128: 3000−3FFF,
NV25256: 6000−7FFF
Quarter Array Protection
1
1
0
1
NV25128: 2000−3FFF,
NV25256: 2000−7FFF
Half Array Protection
Full Array Protection
NV25128: 0000−3FFF,
NV25256: 0000−7FFF,
Table 10. WRITE PROTECT CONDITIONS
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
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5
NV25128, NV25256
WRITE OPERATIONS
Write Enable and Write Disable
The NV25xxx device powers up into a write disable state.
The device contains a Write Enable Latch (WEL) which
must be set before attempting to write to the memory array
or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the NV25xxx. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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6
NV25128, NV25256
Byte Write
Following completion of the write cycle, the NV25xxx is
automatically returned to the write disable state.
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. The number of significant bits
is as shown in Table 11. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
Write Identification Page
The additional 64−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be
set (IPL = 1) using the WRSR instruction, before
attempting to write to the IP. The address bits [A15:A5] are
Don’t Care and the [A4:A0] bits define the byte address
within the Identification Page. In addition, the Byte Address
must point to a location outside the protected area defined by
the BP1, BP0 bits from the Status Register. When the full
memory array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed. Also,
the write to the IP is not accepted if the LIP bit from the
Status Register is set to 1 (the page is locked in Read−only
mode).
Page Write
After sending the first data byte to the NV25xxx, the host
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Table 11. BYTE ADDRESS
Address Significant Bits
Address Don’t Care Bits
# Address Clock Pulses
NV25256
A14 − A0
A13 − A0
A4 − A0
A15
16
16
16
NV25128
A15 − A14
A15 − A5
Identification Page
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
OPCODE
DATA IN
BYTE ADDRESS*
D7 D6 D5 D4 D3 D2 D1 D0
SI
0
0
0
0
0
0
1
0
A
N
A
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
* Please check the Byte Address Table (Table 11)
Figure 5. Byte WRITE Timing
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7
NV25128, NV25256
CS
24+(N−1)x8−1 .. 24+(N−1)x8
21 22 23 24−31 32−39
0
1
2
3
4
5
6
7
8
24+Nx8−1
SCK
SI
Data Byte N
7..1
BYTE ADDRESS*
OPCODE
DATA IN
A
N
A
0
0
0
0
0
0
0
1
0
0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
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8
NV25128, NV25256
READ OPERATIONS
Read from Memory Array
internal write cycle is in progress, the RDSR command will
output the full content of the status register. For easy
detection of the internal write cycle completion, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the NV25xxx will
respond by shifting out data on the SO pin (as shown in
Figure 8). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
Reading the additional 64−byte Identification Page (IP) is
achieved using the same Read command sequence as used
for Read from main memory array (Figure 8). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A4:A0] are the
address significant bits that point to the data byte shifted out
on the SO pin. If the CS continues to be held low, the internal
address register defined by [A4:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 64−byte page
boundary.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
NV25xxx will shift out the contents of the status register on
the SO pin (Figure 9). The status register may be read at any
time, including during an internal write cycle. While the
CS
20 21 22 23 24 25 26 27 28 29 30
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
OPCODE
BYTE ADDRESS*
A
0
A
N
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
MSB
Figure 8. READ Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
3
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
5
7
6
4
2
1
0
SO
MSB
Figure 9. RDSR Timing
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9
NV25128, NV25256
Hold Operation
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The NV25xxx device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The HOLD input can be used to pause communication
between host and NV25xxx. To pause, HOLD must be taken
low while SCK is low (Figure 10). During the hold condition
the device must remain selected (CS low). During the pause,
the data output pin (SO) is tri−stated (high impedance) and
SI transitions are ignored. To resume communication,
HOLD must be taken high while SCK is low.
Design Considerations
The NV25xxx device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Dashed Line = mode (1, 1)
Figure 10. HOLD Timing
Error Correction Code
The NV25xxx incorporates on−board Error Correction
Code (ECC) circuitry, which makes it possible to detect and
correct one faulty bit in a byte. ECC improves data reliability
by correcting random single bit failures that might occur
over the life of the device.
Table 12. ORDERING INFORMATION (Notes 8, 9)
†
OPN
Density
128 kb
128 kb
Automotive Grade
Package Type
TSSOP−8 (Pb−Free)
SOIC−8 (Pb−Free)
Shipping
NV25128DTHFT3G
NV25128DWHFT3G
Grade 0 (−40°C to +150°C)
Grade 0 (−40°C to +150°C)
3,000 / Tape & Reel
3,000 / Tape & Reel
NV25256DTHFT3G
NV25256DWHFT3G
256 kb
256 kb
Grade 0 (−40°C to +150°C)
Grade 0 (−40°C to +150°C)
TSSOP−8 (Pb−Free)
SOIC−8 (Pb−Free)
3,000 / Tape & Reel
3,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
8. All packages are RoHS−compliant (Pb−Free, Halogen−free).
9. The standard lead finish is NiPdAu.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX = Specific Device Code
Y
= Year
WW = Work Week
A
G
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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