NV25M01DTUTG [ONSEMI]
EEPROM Serial 1-Mb SPI;型号: | NV25M01DTUTG |
厂家: | ONSEMI |
描述: | EEPROM Serial 1-Mb SPI 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总15页 (文件大小:277K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NV25M01
EEPROM Serial 1-Mb SPI
Description
The NV25M01 is a EEPROM Serial 1−Mb SPI device internally
organized as 128Kx8 bits. It features a 256−byte page write buffer and
supports the Serial Peripheral Interface (SPI) protocol. The device
features software and hardware write protection, including partial as
well as full array protection.
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On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• 10 MHz Capability
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
SOIC−8
DW SUFFIX
CASE 751BD
TSSOP−8
DT SUFFIX
CASE 948AL
• 256−byte Page Write Buffer
• Identification Page with Permanent Write Protection
• Self−timed Write Cycle
PIN CONFIGURATIONS
V
CS
SO
WP
1
CC
HOLD
SCK
SI
• Hardware and Software Protection
V
SS
• Block Write Protection –
Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
SOIC (DW),
TSSOP (DT)
(Top View)
• 100 Year Data Retention
• Automotive Grade 2 Temperature Range (105°C)
PIN FUNCTION
• 8 lead SOIC and TSSOP Packages
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Pin Name
CS
Function
Chip Select
SO
Serial Data Output
Write Protect
V
CC
WP
V
SS
Ground
SI
CS
SI
Serial Data Input
Serial Clock
SCK
NV25M01
SO
WP
HOLD
Hold Transmission Input
Power Supply
HOLD
SCK
V
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2018 − Rev. 1
NV25M01/D
NV25M01
MARKING DIAGRAMS
TM1A
W25M1A
AYMXXX
AYMXXX
G
(TSSOP−8)
(SOIC−8)
TM1A = Specific Device Code
A
= Assembly Location
W25M1A = Specific Device Code
Y
M
XXX
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of
A
Y
M
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Assembly Lot Number
= Pb−Free Microdot
XXX = Last Three Digits of
XXX = Assembly Lot Number
G
Table 1. MAXIMUM RATINGS
Parameter
Ratings
Units
°C
Operating Temperature
Storage Temperature
−45 to +130
−65 to +150
−0.5 to +6.5
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C
CC
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D. C. OPERATING CHARACTERISTICS (V = 1.8 V to 5.5 V, T = −40°C to +105°C, unless otherwise specified)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
1.2
1.8
3
Units
mA
I
Supply Current
(Read Mode)
SO open
V
CC
= 1.8 V, f
= 5 MHz
= 10 MHz
= 10 MHz
CCR
SCK
SCK
SCK
V
= 2.5 V, f
= 5.5 V, f
mA
CC
CC
V
mA
I
Supply Current
(Write Mode)
3
mA
CCW
I
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
= GND or V , CS = V
CC
3
2
2
mA
mA
mA
V
SB
IN
CC
I
L
V
IN
= GND or V
CC
−2
−2
I
LO
CS = V , V
= GND or V
CC
CC
OUT
V
V
CC
V
CC
V
CC
V
CC
≥ 2.5 V
−0.5
−0.5
0.3V
CC
IL
< 2.5 V
≥ 2.5 V
< 2.5 V
0.25V
CC
V
Input High Voltage
Output Low Voltage
Output High Voltage
0.7V
V
V
+ 0.5
+ 0.5
V
V
V
IH
CC
CC
CC
0.75V
CC
V
V
V
≥ 2.5 V, I = 3.0 mA
0.4
0.2
OL
CC
OL
< 2.5 V, I = 150 mA
CC
OL
V
V
≥ 2.5 V, I = −1.6 mA
V
V
− 0.8
− 0.2
OH
CC
CC
OH
CC
V
< 2.5 V, I = −100 mA
OH
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NV25M01
Table 4. PIN CAPACITANCE (T = 25°C, f = 1.0 MHz, V = +5.0 V) (Note 5)
A
CC
Symbol
Test
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Conditions
= 0 V
Min
Typ
Max
8
Units
pF
C
V
OUT
OUT
C
V
IN
= 0 V
8
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (T = −40°C to +105°C, unless otherwise specified.) (Note 6)
A
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
Min
DC
20
Max
Min
DC
10
Max
Symbol
Parameter
Units
MHz
ns
f
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
5
10
SCK
t
SU
t
H
20
10
ns
t
75
40
ns
WH
t
75
40
ns
WL
t
HOLD to Output Low Z
Input Rise Time
Input Fall Time
50
2
25
2
ns
LZ
t
RI
(Note 8)
(Note 8)
ms
t
FI
2
2
ms
t
t
HOLD Setup Time
HOLD Hold Time
0
0
ns
HD
CD
10
10
ns
t
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
75
40
ns
V
t
0
0
ns
HO
t
50
20
25
ns
DIS
t
100
ns
HZ
CS
t
80
60
60
60
60
10
10
40
30
30
30
30
10
10
ns
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
t
t
ns
ns
t
WP Hold Time
t
(Note 7)
Write Cycle Time
5
5
ms
WC
6. AC Test Conditions:
Input Pulse Voltages: 0.2 V to 0.8 V for V ≥ 2.5 V & 0.15 V to 0.85 V for V < 2.5 V
CC
CC
CC
CC
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
7. t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Table 6. POWER−UP TIMING (Notes 8 and 9)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
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3
NV25M01
Pin Description
Functional Description
The NV25M01 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the NV25M01 is accomplished by
providing the READ command and an address. Writing to
the NV25M01 requires a WRITE command, address and
data.
After a high to low transition on the CS input pin, the
NV25M01 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing illustrated in Figure 2.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and the NV25M01.
CS: The chip select input pin is used to enable/disable the
NV25M01. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and NV25M01 must be
preceded by a high to low transition and concluded with a
low to high transition of the CS input.
The NV25M01 features an Identification Page (256
bytes) which can be accessed for Read and Write operations
when the IPL bit in the Status Register is set to “1”. The user
can also choose to make the Identification Page permanently
write protected.
WP: The write protect input pin will allow all write
operations to the device when held high. When the WP pin
is tied low and the WPEN bit in the Status Register is set to
“1”, writing to the Status Register is disabled.
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
HOLD: The HOLD input pin is used to pause transmission
between host and NV25M01, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
RDSR
WRSR
READ
V , either directly or through a resistor.
CC
WRITE
t
CS
CS
t
t
WL
t
WH
CSS
t
t
t
CNS
CNH
CSH
SCK
t
H
t
RI
t
t
SU
FI
VALID
IN
SI
t
V
t
V
t
DIS
t
HO
HI− Z
HI− Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
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4
NV25M01
Status Register
The Status Register, described in Table 8, contains status
and control bits.
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the Identification Page (IPL = 1) or main memory
array (IPL = 0) will be accessed for Read or Write
operations. The IPL bit is set by the user with the WRSR
command and is volatile. The IPL bit is automatically reset
after a read/write operations.
The LIP bit is set by the user with the WRSR command
and is non−volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read−only mode).
Note: The IPL and LIP bits cannot be set within the same
WRSR instruction. If the user attempts to set both the IPL
and LIP bits at the same time, these bits will remain
unchanged.
The RDY (Ready) bit indicates whether the device is busy
executing a write operation. This bit is automatically set to
1 during an internal write cycle, and reset to 0 when the
device is ready to accept commands. For the host, this bit is
read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
Table 8. STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
IPL
0
LIP
BP1
BP0
WEL
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
None
Protection
0
0
1
1
0
1
0
1
No Protection
18000h−1FFFFh
10000h−1FFFFh
00000h−1FFFFh
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
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5
NV25M01
Write Enable and Write Disable
Write Operations
The internal Write Enable Latch and the correspon–ding
Status Register WEL bit are set by sending the WREN
instruction to the NV25M01. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior any WRITE or WRSR instruction.
The NV25M01 device powers up into a write disable
state. The Write Enable Latch (WEL) bit must be set before
attempting to write to memory or to the status register. In
addition, the address of the memory location(s) to be written
must be outside the protected area, as defined by the BP0 and
BP1 status register bits.
The internal Write Enable Latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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6
NV25M01
Byte Write
page, thus possibly overwriting previoualy loaded data.
Following completion of the write cycle, the NV25M01 is
automatically returned to the write disable state.
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 24−bit address
and a data byte as shown in Figure 5. Only 17 significant
address bits are used by the NV25M01. The rest are don’t
care bits, as shown in Table 11. Internal programming will
start after the low to high CS transition. During an internal
write cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY bit will indicate if the
internal write cycle is in progress (RDY high), or the device
is ready to accept commands (RDY low).
Write Identification Page
The 256−byte Identification Page (IP) can be written with
user data using the same Write commands sequences that are
used for writing to the main memory array (Figure 6). The
IPL Status Register bit must be set (IPL = 1), before
attempting to write to the IP.
Address bits [A23:A17] and [A14:A8] are Don’t Care and
address bits [A7:A0] determine the starting byte address
within the Identification Page. Address bits [A16:A15] must
point to a location outside the protected area defined by
Write Protection bits BP1 and BP0. When the entire memory
is write protected (BP1, BP0 = 1,1), write requests to the IP
will be ignored.
Page Write
After sending the first data byte to the NV25M01, the host
may continue sending data, up to a total of 256 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
A write request to the IP is also ignored if the LIP Status
Register bit is set to 1 (the page is locked in Read−only
mode).
Table 11. BYTE ADDRESS
Device
Address Significant Bits
A16 − A0
Address Don’t Care Bits
A23 – A17
# Address Clock Pulses
Main Memory Array
Identification Page
24
24
(A16:15) and A7 − A0
A23 – A17 & A14 − A8
CS
0
1
2
3
4
5
6
7
8
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
OPCODE
BYTE ADDRESS*
DATA IN
A
N
A
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 5. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
29 30 31 32−39 40−47 32+(N−1)x8−1....32+(N−1)x8
32+Nx8−1
SCK
SI
BYTE ADDRESS*
OPCODE
DATA IN
Data Data
Data Byte N
0
0
0
0
0
0
1
0
A
N
A
0
Byte 1
Byte 2
0
7..1
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 6. Page WRITE Timing
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7
NV25M01
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The Write Protect (WP) input can be used to protect
against inadvertently altering Block Protect bits BP0 and
BP1. When WP is low and the WPEN bit is set to “1”, write
operations to the Status Register are inhibited. WP going
low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to
the Status Register. The WP pin function is blocked when
the WPEN bit is set to “0”. The WP input timing is shown
in Figure 8.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1)
Figure 8. WP Timing
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8
NV25M01
Read Operations
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A7:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
address register defined by [A7:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 256−byte page
boundary.
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 24−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the NV25M01 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host sends a RDSR
command. After receiving the last bit of the command, the
NV25M01 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at any
time, including during an internal write cycle.
Read Identification Page
Reading the additional 256−byte Identification Page (IP)
is achieved using the same Read command sequence as used
CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCK
OPCODE
BYTE ADDRESS*
A
0
A
N
1
1
SI
0
0
0
0
0
0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
* Please check the Byte Address Table (Table 11).
Note: Dashed Line = mode (1, 1)
Figure 9. READ Timing
CS
0
1
2
3
4
5
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
1
SI
DATA OUT
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1)
5
SO
7
6
4
3
2
1
0
MSB
Figure 10. RDSR Timing
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9
NV25M01
Hold Operation
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The NV25M01 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The HOLD input can be used to pause communication
between host and NV25M01. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is
low.
Design Considerations
The NV25M01 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after V exceeds the POR trigger level
and will power down into Reset mode when V drops
CC
CC
CS
t
CD
t
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
ORDERING INFORMATION
Specific Device
Package
Type
Lead
Finish
†
Marking
Device Order Number
Temperature Range
Shipping
NV25M01DWUTG
W25M1A
SOIC−8
(−40°C to +105°C)
NiPdAu
3,000 Units / Tape & Reel
3,000 Units / Tape & Reel
(Pb−Free)
NV25M01DTUTG
TM1A
TSSOP−8
(Pb−Free)
(−40°C to +105°C)
NiPdAu
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
98AON34272E
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REFERENCE:
DESCRIPTION: SOIC 8, 150 MILS
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34272E
PAGE 2 OF 2
ISSUE
REVISION
DATE
19 DEC 2008
O
RELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
751BD
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
DATE 19 DEC 2008
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
98AON34428E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
REFERENCE:
DESCRIPTION: TSSOP8, 4.4X3
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34428E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
948AL
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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