NV34C04MUW3VTBG [ONSEMI]
4-Kb 串行 SPD EEPROM，用于 DDR4 DIMM;
| 型号： | NV34C04MUW3VTBG |
| 厂家： | 
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| 描述： | 4-Kb 串行 SPD EEPROM，用于 DDR4 DIMM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 双倍数据速率 光电二极管 |
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NV34C04
EEPROM Serial 4-Kb SPD
Automotive Grade 1 for
DDR4 DIMM
Description
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The NV34C04 is a EEPROM Serial 4−Kb, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
2
1
1
Fast (400 kHz) and Fast Plus (1 MHz) I C protocols.
UDFN8
UDFN8
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
MU3 SUFFIX
CASE 517AZ
MUW3 SUFFIX
CASE 517DH
PIN CONFIGURATION
1
V
A
A
A
CC
0
1
2
Features
WP
• JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
• Automotive Grade 1 Temperature Range: −40°C to +125°C
• Supply Range: 1.7 V − 3.6 V
(Top View)
SCL
SDA
V
SS
UDFN (MU3, MUW3)
2
• I C / SMBus Interface
For the location of Pin 1, please consult the
corresponding package drawing.
• Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
• 16−Byte Page Write Buffer
MARKING DIAGRAM
• Hardware Write Protection for Entire Memory
• Low Power CMOS Technology
XXX
AZZ
• 2 x 3 x 0.5 mm UDFN Package
UDFN8
YM
• These Devices are Pb−Free and are RoHS Compliant
G
V
CC
XXX
A
ZZ
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
SCL
NV34C04
SDA
A , A , A
2
1
0
PIN FUNCTIONS
WP
Pin Name
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
A , A , A
0
1
2
V
SS
SDA
Figure 1. Functional Symbol
SCL
WP
V
CC
V
SS
Ground
DAP
Backside Exposed DAP at V
SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2018 − Rev. 0
NV34C04/D
NV34C04
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
°C
°C
V
Operating Temperature
Storage Temperature
−45 to +130
−65 to +150
−0.5 to +6.5
−0.5 to +10.5
Voltage on any pin (except A ) with respect to Ground (Note 1)
0
Voltage on pin A with respect to Ground
V
0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. The A pin can be raised to a HV level for SWP
CC
0
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of V
.
CC
Table 2. RELIABILITY CHARACTERISTICS
Symbol
(Note 2)
Parameter
Min
1,000,000
100
Units
Write Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. Page Mode, V = 2.5 V, 25°C
CC
Table 3. THERMAL CHARACTERISTICS (Note 3)
Parameter
Test Conditions/Comments
Junction−to−Ambient (Still Air)
3. Power Dissipation is defined as P = (T − T )/q , where T is the junction temperature and T is the ambient temperature. The thermal
Max
Unit
Thermal Resistance q
92
°C/W
JA
J
J
A
JA
J
A
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (Vcc = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified)
Symbol
Parameter
Read Current
Test Conditions
Min
Max
Units
mA
I
Read, f
= 400 kHz or 1 MHz
1
CCR
SCL
I
Write Current
Write, during t
(Note 4)
1
mA
CCW
WR
I
Standby Current
All I/O Pins at
GND or Vcc
Vcc < 2.2 V
1
mA
SB
Vcc ≥ 2.2 V
2
2
I
L
I/O Pin Leakage
Pin at GND or V
mA
V
CC
V
Input Low Voltage
−0.5
0.3*Vcc
IL
V
IH
Input High Voltage
0.7*Vcc
V
CC
+ 0.5
V
V
V
Output Low Voltage
Output Low Voltage
Power On Reset Threshold
Power Off Reset Threshold
V
V
≥ 2.2 V, I = 20 mA
0.4
V
OL1
OL2
CC
OL
< 2.2 V, I = 6.0 mA
0.2
1.3
V
CC
OL
V
POR+
V
POR−
(Note 4)
(Note 4)
V
0.8
V
4. Tested initially and after a design or process change that affects this parameter
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NV34C04
Table 5. A.C. CHARACTERISTICS (Note 6) V = 1.7 V to 3.6 V, T = −40°C to +125°C, unless otherwise specified.
CC
A
Standard
= 1.7 V − 3.6 V
Fast
= 1.7 V − 3.6 V
Fast−Plus
V = 2.2 V − 3.6 V
CC
V
CC
V
CC
Min
10
4
Max
Min
10
Max
Min
10
Max
Symbol
(Note 5)
Parameter
Clock Frequency
Units
kHz
ms
F
SCL
100
400
1,000
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
0.6
1.3
0.6
0.6
0
0.26
0.50
0.26
0.26
0
HD:STA
t
4.7
4
ms
LOW
t
ms
HIGH
SU:STA
t
4.7
0
ms
t
ms
HD:DI
t
Data In Setup Time
250
100
50
ns
SU:DAT
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1,000
300
300
300
120
120
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
0.26
0.5
ms
SU:STO
t
Bus Free Time Between
STOP and START
4.7
ms
BUF
t
Data Out Hold Time
200
3450
50
200
900
50
0
350
50
ns
ns
HD:DAT
T (Note 7)
i
Noise Pulse Filtered at SCL
and SDA Inputs
t
WP Setup Time
0
0
0
1
ms
ms
SU:WP
t
WP Hold Time
2.5
2.5
HD:WP
t
Write Cycle Time
4
4
4
ms
ms
ms
ms
WR
t
(Notes 7, 8)
Power-up to Ready Mode
Warm power cycle off time
0.5
0.5
0.5
INIT
t
(Note 9)
0.2
25
0.2
25
0.2
25
POFF
t
(Note 10) Detect clock low timeout
35
35
35
TIMEOUT
5. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
2
time−out. The device also meets the Fast and Standard I C specifications, except that T and t are shorter, as required by the 1 MHz Fast
i
DH
Plus protocol.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
is the delay between the Power−On Reset threshold (V
) and the device is ready to accept commands.
INIT
POR+
9. Power−Off delay to ensure a proper Reset when the V drops below V
CC
POR−
10.A timeout condition can only be ensured if SCL is driven low for t
or longer; then, NV34C04 is reset and ready to receive a new
TIMEOUT(Max)
START condition. NV34C04 does not reset if SCL is driven low for less than t . The interface will reset itself and will release the
TIMEOUT(Min)
SDA line if the SCL line stays low beyond the t
START and STOP.
limit. The time−out count takes place when SCL is low in the time interval between
TIMEOUT
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
≤ 50 ns
0.3 x V , 0.7 x V
CC
CC
0.3 x V , 0.7 x V
CC
CC
Current Source: I = 6 mA; C = 100 pF
OL
L
Table 7. PIN CAPACITANCE (T = 25°C, V = 3.6 V, f = 1 MHz)
A
CC
Symbol
Parameter
Test Conditions/Comments
Min
Max
8
Unit
pF
C
SDA, Pin Capacitance
Input Capacitance (other pins)
V
= 0
= 0
IN
IN
IN
V
6
pF
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3
NV34C04
Table 8. INPUT IMPEDANCE
Symbol
Parameter
Test Conditions
Min
30
Max
Unit
kW
Z
IL
Input Impedance for A0, A1, A2, WP Pins
Input Impedance for A0, A1, A2, WP Pins
V
< 0.3 * Vcc
> 0.7 * Vcc
IN
IN
Z
IH
V
800
kW
Pin Description
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and transmits
data stored in the memory. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor. The Write Protect pin should be tied
directly either to Vcc or GND.
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
Power−On Reset (POR)
The NV34C04 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
undetermined logic state. As V exceeds the POR trigger
CC
level, the device will power up into standby mode. The
device will power down into Reset mode when V drops
CC
below the POR trigger level. This bi−directional POR
behavior protects the NV34C04 against brown−out failure
following a temporary loss of power. The POR trigger level
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) determine whether the command is a read/write
command (1010b) or a utility command (0110b), as
described in Table 9. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is being performed.
is set below the minimum operating V level.
CC
Device Interface
2
The NV34C04 supports the Inter−Integrated Circuit (I C)
and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data flow is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The NV34C04 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8 NV34C04
devices may be present on the bus simultaneously, and can be
individually addressed by matching the logic state of the
address inputs A0, A1, and A2.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9 clock
cycle (Figure 3). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
th
th
bytes in the 9 clock cycle. The Slave will stop transmitting
2
I C/SMBus Protocol
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 4.
2
The I C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the V
CC
SDA
SCL
START BIT
STOP BIT
Figure 2. Start/Stop Timing
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4
NV34C04
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 3. Acknowledge Timing
t
t
F
HIGH
t
R
t
LOW
70%
30%
70%
30%
70%
70%
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:STO
SU:DAT
70%
30%
70%
70%
70%
30%
SDA IN
30%
t
BUF
t
HD:DAT
70%
SDA OUT
30%
Figure 4. Bus Timing
Table 9. COMMAND SET (Notes 11, 12)
Function Specific Preamble
Select Address
R/W_n
A0 Pin
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
0
0
0
0
1
1
1
1
0
Function
Read EE Memory
Abbr
RSPD
WSPD
SWP0
SWP1
SWP2
SWP3
CWP
1
0
1
0
LSA2
LSA1
LSA0
0 or 1
Write EE Memory
Set Write Protection, block 0
Set Write Protection, block 1
Set Write Protection, block 2
Set Write Protection, block 3
Clear All Write Protection
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
V
HV
V
HV
V
HV
V
HV
V
HV
Read Protection Status, block 0
Read Protection Status, block 1
Read Protection Status, block 2
Read Protection Status, block 3
RPS0
RPS1
RPS2
RPS3
SPA0
0, 1 or V
0, 1 or V
0, 1 or V
0, 1 or V
0, 1 or V
HV
HV
HV
HV
HV
Set SPD Page Address to 0
(Select Lower Bank)
Set SPD Page Address to 1
(Select Upper Bank)
SPA1
1
1
1
1
1
0
0
1
0, 1 or V
0, 1 or V
HV
Read SPD Page Address
Reserved
RPA
−
HV
All Other Encodings
11. LSAx stands for Logic State of Address pin x.
12.If V is not applied on the A0 pin during SWP/CWP commands, the NV34C04 will respond with NoACK after the 3rd byte and will not execute
HV
the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence.
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5
NV34C04
EEPROM Bank Selection
OPERATIONS). The NV34C04 will not acknowledge the
Slave address as long as internal EEPROM Write is in
progress.
Upon power−up, the address pointer is initialized to 00h
pointing to the first location in the lower 2−Kb bank (SPD
page 0).
Hardware Write Protection
Only one SPD page is visible (active) at any given time.
The lower SPD page is automatically selected at power−up.
The upper SPD page can be activated (and the lower one
implicitly de−activated) by executing the SPA1 utility
command. The SPA0 utility command can then be used to
re−activate the lower SPD page without powering down.
The identity of the active SPD page can be retrieved with the
RPA command.
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the NV34C04. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 8). If the WP pin is HIGH during the strobe
interval, the NV34C04 will not acknowledge the data byte
and the Write request will be rejected.
SPD page selection related command details are
presented in Table 11c, Table 11d, Figure 12 and Figure 13.
Delivery State
The NV34C04 is shipped ‘unprotected’, i.e. none of the
Software Write Protection (SWP) flags is set. The entire
memory is erased, i.e. all bytes are 0xFF.
Write Operations
EEPROM Byte Write
To write data to the EEPROM, the Master creates a
START condition on the bus, and then sends out the
appropriate Slave address (with the R/W bit set to ‘0’),
followed by a starting data byte address, followed by data.
The matching Slave will acknowledge the Slave address,
EEPROM byte address and the data byte (Figure 5). The
Master then ends the session by creating a STOP condition
on the bus. The STOP starts the internal Write cycle for the
(non−volatile) EEPROM data (Figure 6).
Read Operations
Immediate Read
A NV34C04 presented with a Slave address containing a
‘1’ in the R/W position will acknowledge the Slave address
and will then start transmitting EEPROM data from the
current address pointer location. The Master stops this
transmission by responding with NoACK, followed by a
STOP (Figure 9).
EEPROM Page Write
Selective Read
Each of the two 2−Kb banks is organized as 16 pages of
16 bytes each (not to be confused with the SPD page, which
refers to the entire 2−Kb bank). One of the 16 memory pages
is selected by the 4 most significant bits of the byte address,
while the 4 least significant bits point to the byte position
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 7).
During data load, the internal byte position pointer is
automatically incremented after each data byte is loaded. If
the Master transmits more than 16 data bytes, then earlier
data will be replaced by later data in a ‘wrap−around’
fashion within the 16−byte wide data buffer. The internal
Write cycle then starts following the STOP.
The Read operation can be started from a specific address,
by preceding the Immediate Read sequence with a ‘data less’
Write sequence. The Master sends out a START, Slave
address and byte address, but rather than following up with
data (as in a Write operation), the Master then issues another
START and continuous with an Immediate Read sequence
(Figure 10).
Sequential EEPROM Read
EEPROM data can be read out indefinitely, as long as the
Master responds with ACK (Figure 11). The internal address
pointer is automatically incremented after every data byte
sent to the bus. If the end of the active 2−Kb bank is reached
during continuous Read, then the address count
‘wraps−around’ to the beginning of the active 2−Kb bank,
etc. Sequential Read works with either Immediate Read or
Selective Read, the only difference being that in the latter
case the starting address is intentionally updated.
Acknowledge Polling
Acknowledge polling can be used to determine if the
NV34C04 is busy writing to EEPROM, or is ready to accept
commands. Polling is executed by interrogating the device
with
a
‘Selective Read’ command (see READ
S
T
A
R
T
BUS ACTIVITY:
S
T
O
P
SLAVE
ADDRESS
BYTE
ADDRESS
MASTER
SDA LINE
DATA
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 5. EEPROM Byte Write
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6
NV34C04
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 6. EEPROM Write Cycle Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
O
DATA n
DATA n+1
DATA n+P
P
P
SDA LINE
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
NOTE: In this example n = XXXX 0000(B); X = 1 or 0
Figure 7. EEPROM Page Write
ADDRESS
BYTE
DATA
BYTE
1
1
8
9
8
d
SCL
a
a
0
d
7
SDA
WP
7
0
t
SU:WP
t
HD:WP
Figure 8. WP Timing
N
S
T
A
R
T
BUS ACTIVITY:
MASTER
O
A
C
K
S
T
O
P
SLAVE
ADDRESS
SDA LINE
SLAVE
S
P
A
C
K
DATA
Figure 9. EEPROM Immediate Read
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7
NV34C04
S
T
A
R
T
S
N
O
A
C
K
BUS ACTIVITY:
MASTER
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
SLAVE
S
S
P
A
C
K
A
C
K
A
C
K
DATA n
Figure 10. EEPROM Selective Read
N
O
A
C
K
BUS ACTIVITY:
S
T
A
C
K
A
C
K
A
C
K
SLAVE
O
P
MASTER ADDRESS
SDA LINE
P
A
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
SLAVE
Figure 11. EEPROM Sequential Read
Software Write Protection
Each 1−Kb memory block can be individually protected
against Write requests. Block identities are:
pin A0 before the START and maintained just beyond the
STOP. The D.C. OPERATING CONDITIONS for SWP
operations are shown in Table 10.
SWP command details are listed in Tables 11a and 11b.
2
SWP Slave addresses follow the standard I C convention,
Block 0: byte address 0x00...0x7F (SPD page address = 0)
Block 1: byte address 0x80...0xFF (SPD page address = 0)
Block 2: byte address 0x00...0x7F (SPD page address = 1)
Block 3: byte address 0x80...0xFF (SPD page address = 1)
i.e. to read the state of a SWP flag, the LSB of the Slave
address must be ‘1’, and to set or clear a flag, it must be ‘0’.
For Set/Clear commands a dummy byte address and dummy
data byte must be provided (Figure 12). In contrast to a
regular memory Read, a SWP Read does not return data.
Instead the NV34C04 will respond with NoACK if the flag
is set and with ACK if the flag is not set (Figure 13).
Block Software Write Protection (SWP) flags can be set
or cleared in the presence of a very high voltage V on
HV
address pin A0. The V condition must be established on
HV
Table 10. SWPn AND CWP D.C. OPERATION CONDITION
Symbol
Parameter
A Overdrive (V − V )
CC
Test Conditions
Min
Max
Units
V
DV
4.8
HV
0
HV
I
A High Voltage Detector Current
0.1
10
mA
V
1.7 V < V < 3.6 V
HVD
0
CC
V
A Very High Voltage
0
7
HV
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NV34C04
Table 11a. SWP SET COMMAND DETAIL (following Slave Address)
Block(x)
Protection
Slave
Response
Address
Byte
Slave
Response
Slave
Response
Write
Cycle
Command
Data Byte
(Dummy)
(Dummy)
(Dummy)
SWPx(Note 13)
Not Set
Set
ACK
NoACK
ACK
(Dummy)
(Dummy)
(Dummy)
ACK
NoACK
ACK
ACK
NoACK
ACK
Yes
No
CWP
X
Yes
Table 11b. SWP QUERRY COMMAND DETAIL (following Slave Address)
Block(x)
Slave
Master
Master
Protection
Response
(Response)
(Response)
Command
Data Byte
Dummy
Data Byte
Dummy
RPSx (Nots 13, 14)
Not Set
Set
ACK
(NoACK)
(NoACK)
(NoACK)
(NoACK)
NoACK
Dummy
Dummy
Table 11c. SPD PAGE SELECT COMMAND DETAIL (following Slave Address)
SPD Active
Page
Slave
Response
Address
Byte
Slave
Response
Slave
Response
Write
Cycle
Command
Data Byte
SPAx (Notes 15, 16)
X
ACK
(Dummy)
ACK
(Dummy)
ACK/NoACK*
No
Table 11d. SPD ACTIVE PAGE QUERRY COMMAND DETAIL (following Slave Address)
SPD Active
Page
Slave
Response
Master
(Response)
Master
(Response)
Command
Data Byte
Dummy
Data Byte
Dummy
RPA
0
1
ACK
(NoACK)
(NoACK)
(NoACK)
(NoACK)
(Notes 13, 14, 17)
NoACK
Dummy
Dummy
13.The Master can terminate the sequence by issuing a STOP once the NV34C04 responds with NoACK
14.The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte.
15.Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank.
16.The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up.
17.The device will respond with ACK when the lower 2−Kb EEPROM bank is active and with NoACK when the upper 2−Kb EEPROM bank is
active.
*The NV34C04MU3VTG will respond with NoACK following the dummy Data Byte, while the NV34C04MUW3VTG will respond with ACK
BUS ACTIVITY:
S
T
A
R
T
S
T
Dummy
ADDRESS
Dummy
DATA
SLAVE
O
P
MASTER
SDA LINE
SLAVE
ADDRESS
N
O
A
C
K
N
O
A
C
K
N
A
C
K
A
C
K
A
C
K
or
or
or
O
A
C
K
X = Don’t Care
Figure 12. SWP & SPA Timing
BUS ACTIVITY:
S
T
A
R
T
N
O
A
C
K
N
O S
A T
C O
K P
SLAVE
ADDRESS
MASTER
SDA LINE
SLAVE
Dummy
DATA
Dummy
DATA
N
O
A
C
K
A
C
K
or
X = Don’t Care
Figure 13. RPS & RPA Timing
www.onsemi.com
9
NV34C04
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
NOTES:
B
E
A
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.13 REF
0.10 C
A3
EXPOSED Cu
MOLD CMPD
0.10 C
0.20
0.30
TOP VIEW
D
2.00 BSC
D2
E
E2
e
L
L1
1.35
3.00 BSC
1.25
0.50 BSC
0.25
−−−
1.45
DETAIL B
A1
A
1.35
0.10
0.08
C
C
DETAIL B
A3
C
ALTERNATE
0.35
0.15
CONSTRUCTIONS
A1
SIDE VIEW
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 4
1.56
DETAIL A
D2
L
1
4
8X
0.68
1.45 3.40
E2
8
5
1
8X
b
8X
0.30
e
M
0.10
C A
B
0.50
PITCH
M
0.05
C
NOTE 3
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
NV34C04
PACKAGE DIMENSIONS
UDFN8 2x3, 0.5P
CASE 517DH
ISSUE O
NOTES:
A
B
E
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
PIN ONE
INDICATOR
0.05 C
0.05 C
MILLIMETERS
A3
DIM MIN
MAX
0.55
0.05
EXPOSED Cu
MOLD CMPD
A
A1
A3
b
D
D2
E
E2
e
L
0.45
0.00
TOP VIEW
0.13 REF
0.20
0.30
DETAIL B
A1
2.00 BSC
A
1.30
1.50
0.10
0.08
C
C
DETAIL B
ALTERNATE
CONSTRUCTIONS
A3
C
3.00 BSC
1.30
1.50
0.50 BSC
0.30
−−−
0.50
0.15
A1
SIDE VIEW
L1
SEATING
PLANE
NOTE 4
RECOMMENDED
DETAIL A
SOLDERING FOOTPRINT*
D2
L
1
4
1.56
8X
0.68
E2
1.55 3.40
8
5
8X
b
e
M
0.10
C A
B
1
M
0.05
C
NOTE 3
BOTTOM VIEW
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
XXXXX
AWLYWG
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
W
G
= Work Week
= Pb−Free Package
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11
NV34C04
ORDERING INFORMATION
Specific
Device Marking
Package
Type
Temperature
Range
Lead
Finish
Device Order Number
Shipping
NV34C04MU3VTG
V2U
UDFN−8
−40°C to +125°C
NiPdAu
Tape & Reel,
4,000 Units / Reel
NV34C04MUW3VTG
D2W
UDFN−8
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
18.All packages are RoHS−compliant (Lead−free, Halogen−free)
19.The standard lead finish is NiPdAu.
20.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2
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