NVD5414N [ONSEMI]
Power MOSFET 24 Amps, 60 Volts Single NâChannel; 功率MOSFET 24安培， 60伏特单娜????频道
| 型号： | NVD5414N |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 24 Amps, 60 Volts Single NâChannel |
| 文件： | 总6页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD5414N, NVD5414N
Power MOSFET
24 Amps, 60 Volts Single N−Channel
DPAK
Features
• Low R
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DS(on)
• High Current Capability
I
D
MAX
• Avalanche Energy Specified
V
R
MAX
DS(ON)
(Note 1)
(BR)DSS
• AEC Q101 Qualified − NVD5414N
• These Devices are Pb−Free and are RoHS Compliant
60 V
37 mW @ 10 V
24 A
Applications
N−Channel
• LED Lighting and LED Backlight Drivers
• DC−DC Converters
D
• DC Motor Drivers
• Power Supplies Secondary Side Synchronous Rectification
G
MAXIMUM RATINGS (T = 25°C Unless otherwise specified)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
60
Unit
V
S
V
DSS
Gate−to−Source Voltage − Continuous
V
$20
$30
V
GS
MARKING
DIAGRAMS
Gate−to−Source Voltage − Nonrepetitive
(T < 10 ms)
P
V
GS
V
4
Continuous Drain
Current R
Steady
State
T
= 25°C
= 100°C
= 25°C
I
24
16
55
A
C
D
Drain
q
JC
T
C
(Note 1)
4
DPAK
CASE 369AA
STYLE 2
Power Dissipation
Steady
State
T
C
P
W
D
R
(Note 1)
2
q
JC
1
3
Pulsed Drain Current
t = 10 ms
p
I
75
A
DM
2
1
Gate
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
3
J
stg
Drain
Source
Source Current (Body Diode)
I
24
A
S
5414N = Device Code
Single Pulse Drain−to−Source Avalanche
E
AS
86.4
mJ
Y
= Year
Energy − Starting T = 25°C
J
WW
G
= Work Week
= Pb−Free Device
(V = 50 V , V = 10 V, I = 24 A,
L(pk)
DD
dc
GS
L = 0.3 mH, R = 25 W)
G
Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
T
L
260
°C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
2.7
Unit
Junction−to−Case (Drain) Steady State
(Note 1)
°C/W
R
q
JC
R
58.6
q
JA
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [1 oz] including traces).
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011 − Rev. 1
NTD5414N/D
NTD5414N, NVD5414N
ELECTRICAL CHARACTERISTICS (T = 25°C Unless otherwise specified)
J
Characteristics
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
DS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage Temper-
ature Coefficient
V
/T
J
67.3
mV/°C
(BR)DSS
Zero Gate Voltage Drain Current
I
V
DS
= 0 V
= 60 V
mA
T = 25°C
1.0
50
DSS
GS
J
V
T = 150°C
J
Gate−Body Leakage Current
I
V
DS
= 0 V, V = $20 V
$100
nA
GSS
GS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
V
V
= V , I = 250 mA
2.0
3.2
0.74
0.7
4.0
1.16
37
V
mV/°C
V
GS(th)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On−Voltage
V
GS(th)
/T
J
V
DS(on)
V
= 10 V, I = 24 A
D
GS
V
= 10 V, I = 12 A, 150°C
0.7
GS
D
Drain−to−Source On−Resistance
R
V
= 10 V, I = 24 A
28.4
24
mW
DS(on)
GS
D
Forward Transconductance
g
FS
V
= 15 V, I = 20 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
V
= 25 V, V = 0 V,
pF
nC
Input Capacitance
C
800
165
75
1200
48
DS
GS
iss
f = 1 MHz
Output Capacitance
Transfer Capacitance
Total Gate Charge
C
oss
C
rss
V
GS
= 10 V, V = 48 V,
Q
25
DS
= 24 A
G(TOT)
I
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
1.1
4.8
11.3
G(TH)
Q
GS
Q
GD
SWITCHING CHARACTERISTICS, V = 10 V (Note 3)
GS
V
= 10 V, V = 48 V,
ns
Turn−On Delay Time
t
12
58
47
69
GS
D
DD
d(on)
I
= 24 A, R = 9.1 W
G
Rise Time
t
r
Turn−Off Delay Time
t
d(off)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 2)
V
SD
V
S
= 0 V
V
T = 25°C
0.92
0.8
1.15
GS
J
I
= 24 A
T = 125°C
J
I
S
= 24 A , V = 0 V ,
dc
ns
Reverse Recovery Time
Charge Time
t
45.7
31.7
14
dc
GS
rr
dI /dt = 100 A/ms
S
t
a
Discharge Time
t
b
Reverse Recovery Stored Charge
Q
76
nC
RR
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
3. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
Package
Shipping
NTD5414NT4G
NVD5414NT4G
DPAK
2500 / Tape & Reel
2500 / Tape & Reel
(Pb−Free)
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTD5414N, NVD5414N
TYPICAL PERFORMANCE CURVES
40
35
30
25
20
15
40
T = 25°C
10 V
J
V
DS
≥ 10 V
6 V
35
30
25
20
15
10
5
7 V
5.5 V
5 V
T = 125°C
J
4.8 V
10
5
T = 25°C
J
4.5 V
T = −55°C
J
V
= 4.2 V
GS
0
0
0
1
2
3
4
5
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.040
0.030
0.020
0.010
0.08
0.07
0.06
0.05
0.04
0.03
0.02
I
= 24 A
D
T = 25°C
J
T = 25°C
J
V
= 10 V
GS
5
6
7
8
9
10
10
15
20
25
30
35
40
45
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
V
= 24 A
V
= 0 V
D
GS
= 10 V
GS
T = 150°C
J
T = 125°C
J
−50 −25
0
25
50
75
100 125 150 175
5
10 15 20 25 30 35 40 45 50 55 60
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
V
DS
J
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NTD5414N, NVD5414N
TYPICAL PERFORMANCE CURVES
10
Q
T
V
= 0 V
GS
1500
1000
500
0
T = 25°C
J
8
6
4
Q
Q
2
1
C
C
iss
2
0
I
= 24 A
D
oss
T = 25°C
C
J
rss
0
10
20
30
40
50
60
0
5
10
15
20
25
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
1000
100
10
25
20
15
10
5
V
I
= 48 V
= 24 A
= 10 V
V
= 0 V
DD
GS
T = 25°C
J
D
V
GS
t
f
t
d(off)
t
r
t
d(on)
0
0.4
1
1
10
R , GATE RESISTANCE (W)
100
0.5
0.6
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
90
0 V ≤ V ≤ 10 V
Single Pulse
GS
I
D
= 24 A
80
70
60
50
40
30
20
10
0
T
C
= 25°C
1 ms
100 ms
10 ms
10 ms
dc
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
25
50
75
100
125
150
175
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
NTD5414N, NVD5414N
TYPICAL PERFORMANCE CURVES
100
D = 0.5
0.2
0.1
0.05
0.02
10
1
0.01
0.1
0.01
Single Pulse
Surface−Mounted on FR4 Board using 1 sq in pad size, 1 oz Cu
0.1 10 100 1000
0.001
0.000001
0.00001
0.0001
0.001
0.01
1
t, PULSE TIME (s)
Figure 13. Thermal Response
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5
NTD5414N, NVD5414N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
D
A
E
c2
b3
B
4
2
L3
L4
Z
H
DETAIL A
1
3
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
b2 0.030 0.045
b3 0.180 0.215
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
A
b2
c
b
b
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2 0.018 0.024
GAUGE
SEATING
PLANE
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
L2
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
0.020 BSC
DETAIL A
L3 0.035 0.050
ROTATED 905 CW
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
3.00
0.244
0.118
2.58
0.102
5.80
1.60
0.063
6.17
0.228
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTD5414N/D
相关型号：
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