NVMFD5C470NWFT1G [ONSEMI]
MOSFET â Power, Dual N-Channel;
| 型号： | NVMFD5C470NWFT1G |
| 厂家： | 
ONSEMI |
| 描述： | MOSFET â Power, Dual N-Channel |
| 文件： | 总7页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFD5C470N
MOSFET – Power, Dual
N-Channel
40 V, 11.7 mW, 36 A
Features
• Small Footprint (5x6 mm) for Compact Design
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• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
• NVMFD5C470NWF − Wettable Flank Option for Enhanced Optical
Inspection
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
40 V
11.7 mꢂ @ 10 V
36 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
Dual N−Channel
J
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
D1
D2
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
36
A
C
D
G1
G2
ꢀ
JC
T
C
25
(Notes 1, 2, 3)
Steady
State
S1
S2
Power Dissipation
T
C
P
28
W
A
D
R
(Notes 1, 2)
ꢀ
JC
T
C
= 100°C
= 25°C
14
Continuous Drain
Current R
T
A
I
D
11.7
8.3
3.1
1.5
108
MARKING
DIAGRAM
ꢀ
JA
T
A
= 100°C
= 25°C
(Notes 1, 2, 3)
Steady
State
D1 D1
Power Dissipation
T
A
P
W
D
S1
G1
S2
G2
D1
1
R
(Notes 1 & 2)
ꢀ
JA
D1
D2
D2
XXXXXX
AYWZZ
T
A
= 100°C
DFN8 5x6
(SO8FL)
Pulsed Drain Current
T
A
= 25°C, t = 10 ꢁ s
I
DM
A
p
CASE 506BT
D2 D2
Operating Junction and Storage Temperature
T , T
−55 to
+ 175
°C
J
stg
XXXXXX = 5C470N (NVMFD5C470N)
Source Current (Body Diode)
I
23
49
A
S
= or 470NWF (NVMFD5C470NWF)
= Assembly Location
= Year
A
Y
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (T = 25°C, I
= 2 A)
J
L(pk)
W
ZZ
= Work Week
= Lot Traceability
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
5.3
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
ꢀ
JC
R
49
ꢀ
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
July, 2019 − Rev. 1
NVMFD5C470N/D
NVMFD5C470N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 ꢁ A
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
24
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
10
DSS
GS
DS
J
V
= 40 V
ꢁ
A
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
V
V
= V , I = 250 ꢁ A
2.5
3.5
V
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−6.0
mV/°C
GS(TH)
J
R
V
GS
= 10 V
I = 10 A
D
9.75
11.7
mꢂ
DS(on)
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
420
210
11
ISS
Output Capacitance
C
V
V
= 0 V, f = 1 MHz, V = 25 V
pF
OSS
RSS
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
C
Q
8.0
1.6
2.5
1.5
4.7
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
nC
V
Q
= 10 V, V = 32 V; I = 10 A
GS
GD
GP
GS
DS
D
Q
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
8.0
14
d(ON)
Rise Time
t
r
V
= 10 V, V = 32 V,
DS
GS
D
ns
V
I
= 10 A, R = 1.0 ꢂ
G
Turn−Off Delay Time
t
16
d(OFF)
Fall Time
t
4.5
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T = 25°C
0.9
0.8
20
1.2
J
V
S
= 0 V,
GS
I
= 10 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
a
9.0
10
ns
V
= 0 V, dIS/dt = 100 A/ꢁ s,
GS
I
S
= 10 A
Discharge Time
t
b
Reverse Recovery Charge
Q
7.5
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ꢁ s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5C470N
TYPICAL CHARACTERISTICS
40
200
180
160
140
120
100
80
V
DS
= 3 V
10 V
9 V
35
30
25
20
15
10
8 V
7 V
T = 25°C
J
60
6 V
5 V
40
5
0
4 V
T = 125°C
J
20
0
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
40
35
30
25
20
15
14
13
12
11
10
9
I
= 10 A
D
T = 25°C
J
V
GS
= 10 V
15
10
8
7
5
0
6
5
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
80
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1.9
1.7
1.5
1.3
1.1
10K
1K
I
= 10 A
= 10 V
T = 150°C
J
D
V
GS
T = 125°C
J
T = 85°C
J
100
10
0.9
0.7
−50 −25
0
25
50
75 100 125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD5C470N
TYPICAL CHARACTERISTICS
1K
10
C
iss
9
8
7
6
5
4
3
C
oss
100
Q
Q
gd
gs
C
rss
10
1
T = 25°C
GS
f = 1 MHz
V
I
= 32 V
= 10 A
J
V
DS
2
1
0
= 0 V
D
T = 25°C
J
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
V
GS
= 0 V
t
d(off)
t
r
10
1
t
d(on)
t
f
V
GS
V
DS
= 10 V
= 32 V
T = 125°C
T = 25°C
T = −55°C
J
J
J
1
0.1
1
10
R , GATE RESISTANCE (ꢂ)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
10
T
= 25°C
≤ 10 V
C
V
GS
Single Pulse
T
= 25°C
J(initial)
10
10 ꢁ s
T
= 100°C
1.0E−04
J(initial)
1
1
0.5 ms
1 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.1
1
10
100
1000
1.0E−05
1.0E−03
1.0E−02
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD5C470N
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD5C470NT1G
5C470N
DFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFD5C470NWFT1G
470NWF
DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
1
DATE 26 FEB 2013
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
IDENTIFIER
E1
4X
h
MILLIMETERS
GENERIC
MARKING DIAGRAM*
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
1
2
3
4
XXXXXX
AYWZZ
−−−
TOP VIEW
5.15 BSC
4.90
4.10
1.70
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
DETAIL A
A
6.15 BSC
5.90
4.15
XXXXXX= Specific Device Code
5.70
3.90
6.10
4.40
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
1.27 BSC
0.55
DETAIL A
0.45
−−−
0.65
−−−
12
−−−
−−−
_
D2
D3
0.51
0.56
0.48
3.25
1.80
−−−
−−−
0.61
3.50
*This information is generic. Please refer
to device data sheet for actual part
marking.
0.71
3.75
2.20
4X L
K
e
2.00
1
4
DETAIL B
ALTERNATE
DETAIL B
CONSTRUCTION
4X
b1
N
SOLDERING FOOTPRINT*
E2
M
4.56
2X
2.08
2X
0.56
8X
0.75
8
5
4X
G
b
8X
0.10
0.05
C
C
A B
K1
NOTE 3
BOTTOM VIEW
4X
1.40
6.59
4.84
2.30
3.70
0.70
4X
1.27
PITCH
1.00
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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